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| ? eight 10/100 mbit/s ethernet ports, each using a smii interface single 1000 mbit/s ethernet port, using a parallel gmii interface (lead shared with smii interfaces) ethernet management interface for control and configuration of externally connected phys provides ieee 802.3 half duplex mode on 10/100 mbit/s and full duplex mode on 10/100/1000 mbit/s ethernet ports provides ieee 802.3 management statistics (rmon) ethernet frame encapsulation/decapsulation protocols: itu-t g.7041, generic framing procedure (gfp) itu-t x.86/x.85, link access procedure sdh (laps) itu-t q.922, link access procedure frame mode (lapf) rfc1662/3518, ppp bridging control protocol (bcp) performs mapping/demapping of encapsulated ethernet frames into/from low order (vt1.5 spe/vt2 spe/vc-11/vc- 12) and high order (sts-1 spe/vc-3) virtually concatenated payloads performs mapping/demapping of encapsulated ethernet frames into/from a single contiguous concatenated (sts-3c- spe/vc-4) payload or a single low/high order (vt1.5/vt2/vc-11/vc-12/sts-1/vc-3) payload dynamic bandwidth allocation using on-chip lcas processing (itu-t g.7042) for low and high order virtual concatenated payloads glueless memory interface to external 64/128/256 mbit sdrams low order poh and pointer processing for 84/63 vt1.5/vt2/tu-11/tu-12 and 3 tu-3 high order poh processing for sts-1 spe/vc-3/sts-3c spe/vc-4 byte-wide 19 mhz parallel add and drop telecom bus interfaces per-port ethernet side and sonet/sdh system side loopback for system level diagnostics 16-bit wide microprocessor interface, selectable between motorola or intel boundary scan (ieee 1149.1 standard) + 3.3v and +1.8v power supplies, 5v tolerant i/o leads 400-lead plastic ball grid array package (pbga, 27 mm x 27 mm) device driver document number: preliminary txc-04236-mb, ed. 3 july 2004 data sheet ethermap ? -3 plus device oc-3 ethernet over sonet mapper with rapid restoration txc-04236 the ethermap ? -3 plus is a highly integrated eos device that provides for mapping of 10/100/1000 mbit/s ethernet into sonet/sdh sts-3/stm-1 transport payloads. the device supports connection for up to eight 10/100 mbit/s ethernet ports, using smii interfaces, or a single 1000 mbit/s ethernet port, using a gmii interface. ethernet frames are encapsulated using either gfp, laps, lapf or ppp/bcp protocol. the encapsulated ethernet frames are then mapped into either virtually concatenated low or high order payloads, such as vt1.5 spe/vt2 spe/vc-11/vc-12/sts-1 spe/vc-3, or into contiguously concatenated payloads such as sts-3c spe/vc-4. low and high order sonet/sdh poh generation and processing/termination is performed. a byte-wide parallel interface telecom bus format provides the sonet/sdh interface and may support either drop bus or add bus timing modes. in addition to support for full-rate ethernet transfer, over-subscribed ethernet transfers are also supported using back pressure mechanisms (half and full duplex flow control) in order to prevent frame loss. external sdram is used for buffering ethernet frames to support bandwidth oversubscription and flow control operation as well as receive sonet/sdh container alignment and differential delay compensation of low and high order virtually concatenated payloads. for both low and high order virtually concatenated payloads, optional on- chip standards based lcas processing is provided to allow hitless dynamic bandwidth adjustments. a powerful hardware and rtos independent ethermap device driver provides full access to all the features of the device through apis. it utilizes matched get/set functions and can be easily ported. sonet/sdh add/drop and terminal multiplexers multi-service access platforms (msap) compact access or cpe platforms ip dslams wireless backhaul electronics (rnc/bsc) proprietary transwitch corporation information for use solely by its customers ethermap ? -3 plus microprocessor telecom bus side ethernet line side txc-04236 interface oc-3 ethernet over sonet mapper drop bus add bus sdram interface +3.3v +1.8v ho/lo ring ports ho/lo poh ports clocks (sonet/sdh ref, system, one sec.) ethernet management interface controls 10/100 mbit/s smii (port 1) 10/100 mbit/s smii (port 8) / 1000 mbit/s gmii boundary scan ? with rapid restoration u.s. and/or foreign patents issued or pending copyright ? 2004 transwitch corporation ethermap, phast, temx28, transwitch and txc are registered trademarks of transwitch corporation applications description features transwitch corporation ? 3 enterprise drive shelton, connecticut 06484 usa tel: 203-929-8810 fax: 203-926-9453 www.transwitch.com preliminary information documents contain information on products in the sampling, pre-production or early production phases of the product life cycle. characteristic data and other specifications are subject to change. contact transwitch applications engineering for current information on this product.
- 2 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table of contents section page list of figures ............................................................................................................... ............................................ 6 list of tables ................................................................................................................ ............................................ 8 features ...................................................................................................................... ........................................... 15 mappings ...................................................................................................................... ..................................... 15 encapsulation protocols ....................................................................................................... ............................. 15 ethernet ports ................................................................................................................ .................................... 16 10/100/1000 mbit/s ethernet media access controller (mac) block ............................................................... . 16 sdram interface ............................................................................................................... ................................ 16 telecom bus timing ............................................................................................................ .............................. 16 alarm indication port interface ............................................................................................... ........................... 17 poh port interface ............................................................................................................ ................................ 17 microprocessor interface ...................................................................................................... ............................. 17 jtag interface ................................................................................................................ ................................... 17 block diagram ................................................................................................................. ....................................... 18 block diagram description ..................................................................................................... ................................ 19 data processing/flow .......................................................................................................... .............................. 19 10/100/1000 mbit/s ethernet media access controller (mac) block ............................................................... . 22 sonet/sdh mapping ............................................................................................................. .......................... 23 mapper block .................................................................................................................. ................................... 23 demapper block ................................................................................................................ ................................ 25 ethernet ports ................................................................................................................ .................................... 27 microprocessor interface ...................................................................................................... ............................. 27 sdram memory interface ........................................................................................................ ......................... 27 parallel telecom bus interface ................................................................................................ .......................... 27 high and low order poh (path overhead byte) port interface .................................................................... ... 29 high and low order alarm indication port interface ............................................................................ ............. 29 alarms and performance monitoring blocks ...................................................................................... ................ 29 jtag interface ................................................................................................................ ................................... 29 power-up sequencing ........................................................................................................... ................................ 29 application example ........................................................................................................... .................................... 30 lead diagram .................................................................................................................. ....................................... 31 lead descriptions ............................................................................................................. ...................................... 32 absolute maximum ratings and environmental limitations (referenced to vss) ................................................ 47 thermal characteristics ....................................................................................................... .................................. 47 power requirements ............................................................................................................ .................................. 48 input, output and input/output parameters ..................................................................................... ...................... 49 timing characteristics ........................................................................................................ .................................... 54 operation ..................................................................................................................... ........................................... 93 sonet/sdh processing .......................................................................................................... ......................... 93 general ....................................................................................................................... .................................. 93 transmit high order path termination (vc-3/vc-4/sts-1/sts-3c poh generator) ...................................... 97 general ....................................................................................................................... .................................. 97 j1 ............................................................................................................................ ...................................... 97 b3 ............................................................................................................................ ...................................... 97 c2 ............................................................................................................................ ...................................... 97 g1 ............................................................................................................................ ..................................... 97 h4 ............................................................................................................................ ...................................... 98 f2, f3/z3, k3/z4, and n1/z5 ................................................................................................... ..................... 98 receive high order path termination (vc-3/vc-4/sts-1/sts-3c poh monitor) ........................................... 98 general ....................................................................................................................... .................................. 98 j1 ............................................................................................................................ ...................................... 98 b3 ............................................................................................................................ ...................................... 99 c2 ............................................................................................................................ .................................... 100 g1 ............................................................................................................................ ................................... 100 h4 ............................................................................................................................ .................................... 100 f2, f3/z3, k3/z4, and n1/z5 ................................................................................................... ................... 100 high order poh port interface ................................................................................................. ....................... 100 high order alarm indication port interface .................................................................................... .................. 101 au-4 and au-3 pointer generation .............................................................................................. ................... 102 drop bus timing mode .......................................................................................................... ..................... 102 add bus timing mode 1 ......................................................................................................... ..................... 102 add bus timing mode 2 ......................................................................................................... ..................... 103 tu-3 pointer generation ....................................................................................................... ........................... 103 tu-3 pointer tracking ......................................................................................................... ............................. 103 vc-3/sts-1/tug-3 timeslot interchange ......................................................................................... .............. 103 vt/tu pointer tracking ........................................................................................................ ........................... 103 vt/tu pointer generation ...................................................................................................... ......................... 103 low order timeslot interchange ................................................................................................ ..................... 103 - 3 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table of contents (cont.) section page transmit low order path termination (low order poh generator) ............................................................... 1 04 general ....................................................................................................................... ................................. 104 j2 ............................................................................................................................ ..................................... 104 bip-2 ......................................................................................................................... ................................... 104 signal label .................................................................................................................. ............................... 105 rei/rdi ....................................................................................................................... ................................ 105 k4/z7 bit 2 ................................................................................................................... ................................ 105 v5 rfi ........................................................................................................................ ................................. 105 n2/z6 ......................................................................................................................... .................................. 105 receive low order path termination (low order poh monitor) .................................................................... 106 general ....................................................................................................................... ................................. 106 j2 ............................................................................................................................ ..................................... 106 bip-2 ......................................................................................................................... ................................... 106 signal label .................................................................................................................. ............................... 107 rei/rdi/rfi ................................................................................................................... .............................. 107 k4/z7 bit 2 ................................................................................................................... ................................ 107 n2/z6 ......................................................................................................................... .................................. 107 low order and high order path monitor alarm registers ......................................................................... ...... 108 low order poh port interface .................................................................................................. ....................... 110 low order alarm indication port interface ..................................................................................... .................. 111 sonet/sdh protection switching recovery time .................................................................................. ............ 112 virtual concatenation and lcas ................................................................................................ .......................... 113 low order virtual concatenation without lcas .................................................................................. ............ 113 low order virtual concatenation with lcas ..................................................................................... .............. 115 high order virtual concatenation without lcas ................................................................................. ............ 116 high order virtual concatenation with lcas .................................................................................... .............. 119 configuration for virtual concatenation and lcas .............................................................................. ............. 120 general ....................................................................................................................... ................................. 120 configuring transmit vcat (ethernet to sonet/sdh) ............................................................................. . 121 configuring receive vcat (sonet/sdh to ethernet) .............................................................................. . 122 lcas-specific configuration - transmit ........................................................................................ .............. 123 assigning unused vcgs (when at least one vcg is lcas) .................................................................... 12 4 dynamic mapping and virtual concatenation changes ............................................................................. ...... 124 vcg tributary assignments (adding and removing members) ................................................................. 124 changing vcg encapsulation/decapsulation mode ................................................................................. .. 126 changing vcg sonet/sdh structure .............................................................................................. ......... 126 differential delay compensation ............................................................................................... ....................... 129 maximum differential delay allowed ............................................................................................ ............... 129 maximum differential delay detected ........................................................................................... .............. 130 ethernet support .............................................................................................................. ..................................... 131 smii and gmii interfaces ...................................................................................................... ........................... 131 ethernet mac blocks ........................................................................................................... ............................ 133 ethernet frame size ........................................................................................................... ......................... 134 ethernet half duplex .......................................................................................................... .............................. 134 carrier sense ................................................................................................................. ............................. 134 collision detection ........................................................................................................... ............................ 134 alternate beb truncation ...................................................................................................... ...................... 135 excessive collisions .......................................................................................................... .......................... 135 half-duplex flow control ...................................................................................................... ....................... 135 flow control operation ........................................................................................................ ................................. 136 overview ...................................................................................................................... .................................... 136 full duplex flow control ...................................................................................................... .............................. 136 definitions ................................................................................................................... ................................. 136 flow control algorithm ........................................................................................................ ........................ 136 txfifo overflow ............................................................................................................... .......................... 136 external pause frames ......................................................................................................... ...................... 136 configuring full duplex flow control .......................................................................................... ................ 137 changing configurations ....................................................................................................... ...................... 138 encapsulation/decapsulation ................................................................................................... ............................ 139 setting the encapsulation mode ................................................................................................ ...................... 139 changing the encapsulation mode ............................................................................................... ................... 140 gfp ........................................................................................................................... ....................................... 141 gfp host insertion/extraction of management/control frames .................................................................... .. 148 gfp linear frame mode operation ............................................................................................... .................. 150 transmit side linear extension header ......................................................................................... ............. 150 transmit side cid configuration tables ........................................................................................ ............. 150 receive side linear extension header .......................................................................................... ............. 152 receive side cid configuration tables ......................................................................................... ............. 152 laps .......................................................................................................................... ...................................... 153 - 4 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table of contents (cont.) section page lapf .......................................................................................................................... ...................................... 162 ppp (with bcp and lcp support) ................................................................................................ ................... 170 sdram controller .............................................................................................................. .................................. 183 sdram memory interface ........................................................................................................ ....................... 183 cas latency ................................................................................................................... ............................ 183 bank/row activation ........................................................................................................... ..................... 183 commands ...................................................................................................................... ............................ 184 reset configuration of sdram controller ....................................................................................... ............... 184 configuration changes/initialization .......................................................................................... ...................... 184 microprocessor access to sdram ................................................................................................ .................. 185 reset operation ............................................................................................................... .................................... 186 general ....................................................................................................................... ..................................... 186 external lead controlled hardware reset ....................................................................................... ............... 186 microprocessor controlled hardware reset ...................................................................................... .............. 186 microprocessor controlled soft reset .......................................................................................... ................... 186 microprocessor controlled global performance counter reset .................................................................... .. 186 telecom bus operation ......................................................................................................... ............................... 187 general ....................................................................................................................... ..................................... 187 drop bus interface ............................................................................................................ ............................... 187 drop bus parity selection ..................................................................................................... ........................... 187 add bus interface ............................................................................................................. ............................... 188 add bus timing modes .......................................................................................................... .......................... 188 add bus parity selection ...................................................................................................... ........................... 189 add bus delay ................................................................................................................. ................................ 190 telecom bus tributary activation/tri-state control ............................................................................ ............. 191 vc-3/vc-4 ..................................................................................................................... .............................. 191 tug-3 ......................................................................................................................... ................................ 191 tug-2 ......................................................................................................................... ................................ 191 tu-11/tu-12 ................................................................................................................... ............................ 191 loop backs .................................................................................................................... ....................................... 193 mac loopback .................................................................................................................. .............................. 193 telecom bus loopbacks ......................................................................................................... ........................ 194 boundary scan ................................................................................................................. .................................... 195 introduction .................................................................................................................. .................................... 195 boundary scan operation ....................................................................................................... ........................ 195 boundary scan schematic ....................................................................................................... ....................... 196 boundary scan chain ........................................................................................................... ........................... 196 memory information ............................................................................................................ ................................. 197 general device registers ...................................................................................................... .......................... 200 table 10 through 12 - general configuration and status of the device ..................................................... 200 ethernet mac registers ........................................................................................................ .......................... 201 tables 13 through 17 - status information of the mac ............................................................................... 201 tables 18 through 23 - configuration of the mac ....................................................................................... 210 tables 24 through 29 - mii management interface (used for mac0 only) .................................................. 215 ethernet mac registers ........................................................................................................ .......................... 217 tables 30 through 34 - configuration, alarms and interrupts of the ethernet macs .................................. 217 tx encapsulation registers .................................................................................................... ......................... 219 tables 35 through 47 - configuration, status and alarms of the encapsulation block ............................... 219 rx decapsulation registers .................................................................................................... ........................ 236 tables 48 through 61 - configuration, status and alarms of the decapsulation block ............................... 236 sdram control registers ....................................................................................................... ........................ 268 table 62 - sdram control and sdram interface configuration .............................................................. 268 table 63 and 64 - microprocessor access to the sdram (indirect access) .............................................. 269 tx virtual concatenation registers ............................................................................................ ..................... 270 tables 65 through 75 - configuration, status and alarms of the transmit (ethernet to sonet) virtual concatenation block .................................................................................................. ..................... 270 rx virtual concatenation registers ............................................................................................ ..................... 283 tables 76 through 85 - configuration, status and alarm of the receive (sonet to ethernet) virtual concatenation block ............................................................................... ....... 283 ethernet to sonet handling registers .......................................................................................... ................ 295 tables 86 through 90 - configuration and status of the ethernet frame format block (output of the ethernet mac) .................................................................................................. ................... 295 table 91 through 103 - ethernet buffering and flow control in transmit (ethernet to sonet) and receive (sonet to ethernet) paths ......................................................................................... ........... 296 tx mapper block registers ..................................................................................................... ......................... 302 tables 104 through 107 - configuration, status and interrupt handling of the transmit mapper block ...... 302 tables 108 through 118 - configuration of the transmit mapper block ...................................................... 302 rx demapper block registers ................................................................................................... ...................... 306 tables 119 through 131 - configuration, status and alarms for the receive demapper block .................. 306 - 5 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table of contents (cont.) section page tables 132 through 154 - configuration, status and alarms of the low order poh monitor ..................... 308 tables 155 through 162 - configuration, status and alarms of the low order tx alarm indication (ring) port ............................................................................................... ................... 316 table 163 - configuration of the low order rx alarm indication (ring) port ............................................ 317 tables 164 through 166 - configuration and status of the general low order interrupt controller ............ 318 table 167 - configuration of the high order rx alarm indication (ring) port ........................................... 318 tables 168 through 176 - configuration, status and alarms of the high order tx alarm indication (ring) port ............................................................................................... ................... 318 tables 177 through 209 - configuration, status and alarms of the high order poh monitor .................... 320 tables 210 through 222 - configuration, status and alarms of the tu-3 ptr tracker .............................. 332 tables 223 and 224 - configuration of tu-3 cross connect ...................................................................... 334 tables 225 through 237 - configuration, status and alarms of the tu-3 ptr generator .......................... 335 tables 238 through 242 - configuration of high order (vc-3 and vc-4) poh generator .......................... 337 tables 243 through 250 - configuration, status and alarms of the tu-3 retimer ...................................... 339 tables 251 through 258 - configuration, status and alarms of the au-3/4 retimer ................................... 341 tables 259 through 261 - configuration and status of the general high order interrupt controller .......... 342 tables 262 through 280 - configuration, status and alarms of the rx combus interface .......................... 343 tables 281 through 302 - configuration, status and alarms of the tx combus interface .......................... 347 tables 303 through 305 - configuration and status of the general combus interface interrupt controller 350 tables 306 through 308 - configuration and status of the general vtmapper interrupt controller ........ 351 alarms, performance and fault monitoring ...................................................................................... .................... 353 terminology ................................................................................................................... .................................. 353 system alarm (raw, unlatched alarm) ........................................................................................... ............ 353 alarm event ................................................................................................................... .............................. 353 latched alarm ................................................................................................................. ............................ 353 secondary alarm inhibition .................................................................................................... ...................... 353 interrupt mask ................................................................................................................ .............................. 354 performance and fault monitoring (pm and fm) .................................................................................. ...... 354 performance monitoring (pm) ................................................................................................... .................. 354 fault monitoring (fm) ......................................................................................................... ......................... 354 1-second clock ................................................................................................................ ........................... 354 performance counters .......................................................................................................... ...................... 354 unlatched alarms .............................................................................................................. ............................... 355 inhibition of secondary unlatched alarm generation ............................................................................ ...... 355 latched alarms ................................................................................................................ ................................ 355 latched alarm bits for interrupt generation (lalarm_name/l1alarm_name) .................................................. 356 latched alarm masking bits (malarm_name) ...................................................................................... ............ 357 secondary latched alarm inhibition ............................................................................................ .................... 358 latched alarm bits for pm/fm (l2alarm_name), performance monitoring (pm bits; palarm_name) and fault monitoring (fm bits; falarm_name) ........................................................ 359 positive edge events .......................................................................................................... ......................... 360 negative edge events .......................................................................................................... ....................... 361 positive or negative edge events .............................................................................................. ................. 362 overall alarm generation and pm/fm process diagram ............................................................................ .... 363 performance counters .......................................................................................................... ........................... 364 scheme a - counters with roll-over/saturation option .......................................................................... .... 364 scheme b - performance counters with 1-second shadow register option ............................................. 364 alarm feature combinations .................................................................................................... ....................... 365 system alarm, interrupt, and pm/fm hierarchy .................................................................................. ............ 366 alarm interrupt tree .......................................................................................................... ............................... 368 register tree ................................................................................................................. .................................. 376 mapper/demapper performance monitoring ........................................................................................ ............ 378 mapper/demapper interrupt tree ................................................................................................ ................ 379 mapper/demapper pm/fm tree per block .......................................................................................... ........ 383 mapper/demapper consequent actions per block .................................................................................. ... 390 package information ........................................................................................................... .................................. 394 ordering information .......................................................................................................... ................................... 395 related products .............................................................................................................. .................................... 395 standards documentation sources ............................................................................................... ....................... 396 list of data sheet changes .................................................................................................... .............................. 398 please note that transwitch provides documentation for all of its products. current editions of many documents are available from the products page of the transwitch web site at www.transwitch.com . customers who are using a transwitch product, or planning to do so, should register with the transwitch marketing department to receive relevant updated and supplemental documentation as it is issued. they should also contact the applications engineering department to ensure that they are provided with the latest available information about the product, especially before undertaking development of new designs incorporating the product. - 6 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers list of figures figure page 1 functional block diagram of the ethermap-3 plus .............................................................................. ........ 18 2 low order virtual concatenation structure for sonet/sdh ...................................................................... 19 3 high order virtual concatenation structure for sonet/sdh ..................................................................... 20 4 fixed stuff columns in high order vc-3-xv/sts-1-xv spe ....................................................................... . 21 5 mapping of ethernet frames over sonet/sdh .................................................................................... .... 23 6 typical application using the ethermap-3 plus and phast-3n devices .................................................... 30 7 ethermap-3 plus txc-04236 lead diagram ....................................................................................... ........ 31 8 drop bus timing (only ad, apar, and add are output) .......................................................................... . 54 9 drop bus timing (only ad, apar, and add are output) .......................................................................... . 56 10 drop bus timing (all add bus signals are outputs) ........................................................................... ........ 58 11 drop bus timing (all add bus signals are outputs) ........................................................................... ........ 59 12 add bus timing (timing signals are inputs) .................................................................................. ............ 60 13 add bus timing (timing signals are inputs) .................................................................................. ............ 61 14 add bus timing (timing signals are outputs) ................................................................................. .......... 62 15 tx gmii ethernet interface .................................................................................................. ........................ 63 16 rx gmii ethernet interface .................................................................................................. ........................ 64 17 tx/rx smii ethernet interface (sync as an output) ........................................................................... ....... 65 18 tx/rx smii ethernet interface (sync as an input) ............................................................................ ......... 66 19 ethernet management interface .............................................................................................. ................... 67 20 sdram interface - single word read .......................................................................................... .............. 68 21 sdram interface - single word write ......................................................................................... ................ 69 22 sdram interface - burst read ................................................................................................ .................... 70 23 sdram interface - burst write ............................................................................................... ..................... 71 24 rx vc-3 poh byte interface .................................................................................................. ..................... 72 25 tx vc-3 poh byte interface .................................................................................................. ...................... 73 26 rx low order poh byte interface ............................................................................................. .................. 74 27 tx low order poh byte interface ............................................................................................. .................. 75 28 rx vc-3 alarm indication port interface ..................................................................................... ................. 76 29 tx vc-3 alarm indication port interface ..................................................................................... ................. 77 30 rx low order alarm indication port interface ................................................................................ ............. 78 31 tx low order alarm indication port interface ................................................................................ .............. 79 32 asynchronous microprocessor interface: intel-type write cycle timing ..................................................... 80 33 asynchronous microprocessor interface: intel-type read cycle timing ..................................................... 82 34 asynchronous microprocessor interface: motorola 68360-type write cycle timing ................................... 84 35 asynchronous microprocessor interface: motorola 68360-type read cycle timing ................................... 86 36 synchronous microprocessor interface: motorola mpc860-type read cycle timing ................................. 88 37 synchronous microprocessor interface: motorola mpc860-type write cycle timing ................................. 90 38 boundary scan timing ........................................................................................................ ........................ 92 39 functional block diagram of the mapper/demapper ............................................................................. ...... 93 40 functional model of the mapper/demapper ..................................................................................... ........... 94 41 mapper/demapper bypass modes ................................................................................................ .............. 95 42 vt1.5-xv-spe structure ...................................................................................................... ...................... 113 43 lo sdh multiplexing structure 1 supported by the ethermap-3 plus ....................................................... 114 44 lo sdh multiplexing structure 3 supported by the ethermap-3 plus ....................................................... 114 45 lo sdh multiplexing structure 2 supported by the ethermap-3 plus ....................................................... 114 46 lo sdh multiplexing structure 4 supported by the ethermap-3 plus ....................................................... 115 47 lo sonet multiplexing structure supported by the ethermap-3 plus ..................................................... 115 48 high order sts-1-xv-spe/vc-3-xv structure ................................................................................... ....... 117 49 low order vc-3-xv structure ................................................................................................. ................... 118 50 ho sonet/sdh multiplexing structure supported by the ethermap-3 plus ............................................ 119 51 ethermap-3 plus to phy or switch interconnection using gmii interface ................................................ 132 52 format of gfp frame with an ethernet mac frame payload .................................................................. 141 - 7 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers list of figures (cont.) figure page 53 format of laps frame with an ethernet mac frame payload ................................................................. 153 54 format of lapf bridged frame with an ethernet mac frame payload .................................................... 162 55 format of ppp frame with an ethernet mac frame payload ................................................................... 17 0 56 mac loopback ................................................................................................................ ........................... 193 57 telecom bus loopbacks ....................................................................................................... ..................... 194 58 boundary scan schematic ..................................................................................................... .................... 196 59 latched alarm bit (l1alarm_name) transitions ................................................................................ ........ 357 60 positive edge event - pm/fm signal generation ............................................................................... ....... 360 61 negative edge event - pm/fm signal generation ............................................................................... ...... 361 62 positive/negative edge event - pm/fm signal generation ...................................................................... . 362 63 alarm, interrupt and pm/fm generation process ............................................................................... ....... 363 64 alarm, interrupt and pm/fm generation process (inhibition function) ..................................................... 363 65 alarm interrupt hierarchy ................................................................................................... ........................ 367 66 alarm interrupt tree part a ................................................................................................. ....................... 368 67 alarm interrupt tree part a to part b ....................................................................................... .................. 369 68 alarm interrupt tree part b to part c ....................................................................................... .................. 370 69 alarm interrupt tree part c to parts d1, d2 and d3 .......................................................................... ........ 371 70 alarm interrupt tree parts d1, d2 and d3 to parts e1 and e2 ................................................................. . 372 71 alarm interrupt tree parts e1 and e2 to parts f1 and f2 ..................................................................... .... 373 72 alarm interrupt tree parts f1 and f2 to part g .............................................................................. ........... 374 73 alarm interrupt tree part g ................................................................................................. ....................... 375 74 register tree parts a1, a2 and a3 ........................................................................................... ................. 376 75 register tree parts a1, a2 and a3 (continued) ............................................................................... .......... 377 76 mapper/demapper interrupt tree part a ....................................................................................... ............ 379 77 mapper/demapper interrupt tree part a to parts b1 and b2 .................................................................... 380 78 mapper/demapper interrupt tree parts b1 and b2 to part c .................................................................... 381 79 mapper/demapper interrupt tree part c ....................................................................................... ............ 382 80 mapper/demapper rx_vc3_poh_monitor pm/fm trees ................................................................... 383 81 mapper/demapper rx vc-4 poh monitor pm/fm trees .................................................................... 384 82 mapper/demapper tx combus pm/fm trees ....................................................................................... . 385 83 mapper/demapper rx_tu3_ptr pm/fm trees ...................................................................................... 386 84 mapper/demapper tx_tu3_ptr pm/fm trees ...................................................................................... . 386 85 mapper/demapper rx combus pm/fm trees ....................................................................................... . 387 86 mapper/demapper lodmp_pohmonitor pm/fm trees ...................................................................... 388 87 mapper/demapper lodmp_ptr pm/fm trees ....................................................................................... ... 389 88 ethermap-3 plus txc-04236 package diagram ................................................................................... .... 394 - 8 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers list of tables table page 1 tu-3 pointer tracker/retimer modes ........................................................................................... ............... 96 2 tu-3 pointer generator modes ................................................................................................. .................. 96 3 sonet/sdh protection switching recovery time ................................................................................. .. 112 4 configuration of rmaxdelvcg_x in low order vc ................................................................................ . 129 5 configuration of rmaxdelvcg_x in high order vc ............................................................................... . 129 6 allowed range for high/low watermark registers .............................................................................. .... 137 7 scheduling matrix ............................................................................................................ .......................... 150 8 scheduling matrix mapped in the ethermap-3 plus register map ............................................................ 151 9 memory map overview .......................................................................................................... .................... 197 10 general device configuration (rw) ........................................................................................... ............... 200 11 general device status (ro) .................................................................................................. .................... 200 12 id registers (ro) ........................................................................................................... ........................... 200 13 mac combined receive and transmit counters .................................................................................. .... 201 14 mac receive counters ........................................................................................................ ..................... 202 15 mac transmit counters ....................................................................................................... ..................... 204 16 mac interface status registers .............................................................................................. .................. 206 17 mac carry and carry mask registers .......................................................................................... ............ 207 18 mac configuration registers ................................................................................................. ................... 210 19 mac station address registers ............................................................................................... ................. 211 20 mac ipg / ifg registers ..................................................................................................... ..................... 212 21 mac half duplex registers ................................................................................................... .................... 213 22 mac maximum frame registers ................................................................................................. .............. 213 23 mac test registers .......................................................................................................... ......................... 214 24 mac mii mgmt configuration registers ........................................................................................ ............ 215 25 mac mii mgmt command registers .............................................................................................. ........... 215 26 mac mii mgmt address registers .............................................................................................. .............. 216 27 mac mii mgmt control registers .............................................................................................. ................ 216 28 mac mii mgmt status registers ............................................................................................... ................ 216 29 mac mii mgmt indicators registers ........................................................................................... ............... 216 30 mac block - general configuration (rw) ...................................................................................... ........... 217 31 mac block - alarms (ro) ..................................................................................................... ..................... 217 32 mac block - alarm and interrupt masks (rw) .................................................................................. ........ 218 33 mac block - latched alarms (rr) ............................................................................................. ............... 218 34 mac block - interrupts (ro) ................................................................................................. ..................... 218 35 encapsulation block - general configuration (rw) ............................................................................ ....... 219 36 encapsulation block - laps configuration (rw) ............................................................................... ....... 221 37 encapsulation block - lapf configuration (rw) ............................................................................... ....... 222 38 encapsulation block - gfp configuration (rw) ................................................................................ ........ 223 39 encapsulation block - ppp configuration (rw) ................................................................................ ........ 226 40 encapsulation block - control frame buffers (rw) ............................................................................ ...... 227 41 encapsulation block - status (rw) ........................................................................................... ................. 228 42 encapsulation block - status registers (ro) ................................................................................. ........... 228 43 encapsulation block - performance counters ................................................................................. ......... 228 44 encapsulation block - alarms (ro) ........................................................................................... ................ 231 45 encapsulation block - alarm and interrupt masks (rw) ........................................................................ .... 232 46 encapsulation block - interrupts (ro) ....................................................................................... ................ 233 47 encapsulation block - latched alarms (rr) ................................................................................... ........... 235 48 decapsulation block - general configuration (rw) ............................................................................ ...... 236 49 decapsulation block - laps configuration (rw) ............................................................................... ....... 238 50 decapsulation block - lapf configuration (rw) ............................................................................... ....... 240 - 9 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers list of tables (cont.) table page 51 decapsulation block - control buffer status (rw) ............................................................................ ......... 242 52 decapsulation block - link status (ro) ...................................................................................... ............... 242 53 decapsulation block - gfp configuration (rw) ................................................................................ ........ 243 54 decapsulation block - ppp configuration (rw) ................................................................................ ........ 245 55 decapsulation block - lmi buffers (ro) ...................................................................................... .............. 247 56 decapsulation block - alarms (ro) ........................................................................................... ................ 247 57 decapsulation block - alarm and interrupt masks (rw) ........................................................................ .... 251 58 decapsulation block - latched alarms (rr) ................................................................................... ........... 255 59 decapsulation block - interrupts (ro) ....................................................................................... ................ 258 60 decapsulation block - performance counters .................................................................................. ......... 259 61 decapsulation block - status (rr) ........................................................................................... .................. 266 62 sdram control - general configuration (rw) .................................................................................. ........ 268 63 sdram - access control registers (rw) ....................................................................................... .......... 269 64 sdram - access results registers (ro) ....................................................................................... .......... 269 65 tx virtual concatenation block - general configuration (rw) ................................................................. . 270 66 tx virtual concatenation block - lcas alarms (ro) ........................................................................... ..... 272 67 vt/vc address offsets ....................................................................................................... ....................... 273 68 tx virtual concatenation block - lcas alarm and interrupt masks (rw) ................................................. 275 69 tx virtual concatenation block - lcas latched alarms (rr) ................................................................... 277 70 tx virtual concatenation block - lcas interrupts (ro) ....................................................................... ..... 278 71 tx virtual concatenation block - low order tributary configuration (rw) ............................................... 279 72 tx virtual concatenation block - high order tributary configuration (rw) .............................................. 279 73 tx virtual concatenation block - lcas configuration (rw) .................................................................... .. 279 74 vt/vc address offsets (ctlok4vcen_x and ctlocrcerr_x only) ................................................... 280 75 tx virtual concatenation block - status (ro) ................................................................................ ............ 282 76 rx virtual concatenation block - general configuration registers (rw) .................................................. 283 77 rx virtual concatenation block - alarms (ro) ................................................................................ .......... 285 78 rx virtual concatenation block - alarm and interrupt masks (rw) ........................................................... 2 86 79 rx virtual concatenation block - latched alarms (rr) ........................................................................ ..... 290 80 rx virtual concatenation block - interrupts (ro) ............................................................................ .......... 291 81 rx virtual concatenation block - low order tributary configuration (rw) ............................................... 292 82 rx virtual concatenation block - high order tributary configuration (rw) .............................................. 293 83 rx virtual concatenation block - status (ro) ................................................................................ ........... 293 84 rx virtual concatenation block - frame counter status (ro) .................................................................. 294 85 rx virtual concatenation block - differential delay status (ro) ............................................................. .. 294 86 ethernet frame format block - general configuration (rw) .................................................................... 295 87 ethernet frame format block - alarms (ro) ................................................................................... .......... 295 88 ethernet frame format block - alarm and interrupt masks (rw) ............................................................. 29 5 89 ethernet frame format block - latched alarms (rr) ........................................................................... .... 295 90 ethernet frame format block - interrupts (ro) ............................................................................... .......... 295 91 sonet to ethernet - general configuration and watermarks (rw) ......................................................... 296 92 sonet to ethernet - sdram alarms (ro) ....................................................................................... ........ 297 93 sonet to ethernet - sdram alarm and interrupt masks (rw) ............................................................... 297 94 sonet to ethernet - sdram latched alarms rr) ................................................................................ ... 297 95 sonet to ethernet - sdram interrupts (ro) ................................................................................... ........ 298 96 sonet to ethernet - sdram performance counters (rr) ...................................................................... 29 8 97 sonet to ethernet - sdram fifo status (ro) .................................................................................. ..... 298 98 ethernet to sonet - flow control configuration (rw) ......................................................................... .... 298 99 sdram controller alarm (tx and rx) (ro) ..................................................................................... .......... 299 100 sdram controller (tx and rx direction) (rw) ................................................................................ ......... 300 101 sdram controller (tx and rx directions) (rr) ............................................................................... ......... 300 - 10 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers list of tables (cont.) table page 102 ethernet to sonet, sdram output - interrupts (ro) .......................................................................... .... 301 103 ethernet to sonet, sdram output - performance counters .................................................................. 30 1 104 mapper block - reset (rw) .................................................................................................. ..................... 302 105 mapper block - interrupt configuration (ro) ................................................................................ ............. 302 106 mapper block - interrupt mask (rw) ......................................................................................... ................ 302 107 mapper and demapper block - status (ro) .................................................................................... .......... 302 108 mapper block - timing configuration (rw) ................................................................................... ............ 302 109 mapper block - tug-3/vc-3 configuration (rw) ............................................................................... ....... 303 110 mapper block - tug-2 configuration (rw) .................................................................................... ........... 303 111 mapper block - pointer configuration (rw) .................................................................................. ............ 303 112 mapper block - general configuration, low order (rw) ....................................................................... ... 303 113 mapper block - tug-2 configuration (rw) .................................................................................... ........... 303 114 mapper block - poh configuration (rw) ...................................................................................... ............ 303 115 mapper block - cross connect configuration (rw) ............................................................................ ...... 304 116 mapper block - v4 configuration (rw) ....................................................................................... .............. 304 117 mapper block - poh byte values (rw) ........................................................................................ ............ 304 118 mapper block - bypass control (rw) ......................................................................................... ............... 305 119 demapper block - general configuration (rw) ................................................................................ ........ 306 120 demapper block - bypass control (rw) ....................................................................................... ............ 306 121 demapper block - tug-2 configuration (rw) .................................................................................. ........ 306 122 demapper block - performance counters shadow registers (ro) .......................................................... 306 123 demapper block - alarm control (rw) ........................................................................................ .............. 307 124 demapper block - interrupts (ro) ........................................................................................... .................. 307 125 demapper block - alarms (ro) ............................................................................................... .................. 307 126 demapper block - latched alarms (r/cow-1) .................................................................................. ....... 307 127 demapper block - alarm masks (rw) .......................................................................................... ............. 307 128 lodmp_ptr_defectcorrelations_lp (r/cow-0) .................................................................................. .... 308 129 lodmp_ptr_defectcorrelations_pm (ro) ....................................................................................... ........ 308 130 lodmp_ptr_defectcorrelations_fm (ro) ....................................................................................... ......... 308 131 demapper block - poh byte monitors (ro) .................................................................................... ......... 308 132 lo poh monitor - bypass control (rw) ....................................................................................... ............ 308 133 lo poh monitor - j2 trace message handling ................................................................................. ....... 309 134 lo poh monitor - poh byte monitors (ro) .................................................................................... ......... 309 135 lo poh monitor - accepted values (ro) ...................................................................................... ........... 309 136 lo poh monitor - expected values (rw) ...................................................................................... ........... 309 137 lo poh monitor - general configuration (rw) ................................................................................ ........ 310 138 lo poh monitor - channel configuration (rw) ................................................................................ ........ 311 139 lo poh monitor - channel status (ro) ....................................................................................... ............. 311 140 lo poh monitor - channel report (ro) ....................................................................................... ............ 311 141 lo poh monitor - channel defects (ro) ...................................................................................... ............ 311 142 lo poh monitor - defect correlations (ro) .................................................................................. ........... 312 143 lo poh monitor - latched defects (r/cow-1) ................................................................................. ....... 312 144 lo poh monitor - defect correlations latched for pmfm (r/cow-0) ................................................... 313 145 lo poh monitor - pm defect correlations monitor (ro) ....................................................................... ... 313 146 lo poh monitor - fm defect correlations monitor (ro) ....................................................................... ... 313 147 lo poh monitor - defect correlations mask (r/w) ............................................................................ ...... 314 148 lo poh monitor - defect correlations configuration (rw) .................................................................... .. 314 149 lo poh monitor - defect correlations summary (ro) .......................................................................... ... 315 150 lo poh monitor - defect correlations summary mask (rw) ................................................................... 3 15 151 lo poh monitor - defect correlations group summary (ro) .................................................................. 3 15 152 lo poh monitor - performance monitor one second latch (ro) ............................................................ 315 - 11 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers list of tables (cont.) table page 153 lo poh monitor - performance counters (rw) ................................................................................. ....... 315 154 lo poh monitor - performance counter shadow registers (ro) ............................................................ 315 155 tx lo ring port - general configuration (rw) ............................................................................... ........... 316 156 tx lo ring port - event latch (cow-1) ...................................................................................... .............. 316 157 tx lo ring port - performance counters (rw) ................................................................................ ......... 316 158 tx lo ring port - performance counter shadow registers (ro) ............................................................. 31 6 159 tx lo ring port - defects .................................................................................................. ........................ 317 160 tx lo ring port - interrupt mask (rw) ...................................................................................... ................ 317 161 tx lo ring port - event interrupt (ro) ..................................................................................... ................. 317 162 tx lo ring port - defect interrupt (ro) .................................................................................... ................. 317 163 rx lo ring port - configuration (rw) ....................................................................................... ................ 317 164 lo interrupt controller - interrupts (ro) .................................................................................. .................. 318 165 lo interrupt controller - interrupt masks (rw) ............................................................................. ............. 318 166 lo interrupt controller - summary (ro) ..................................................................................... ............... 318 167 rx ho ring port - configuration (rw) ....................................................................................... ............... 318 168 tx ho ring port - configuration (rw) ....................................................................................... ................ 318 169 tx ho ring port - counter configuration (rw) ............................................................................... .......... 319 170 tx ho ring port - event latch (cow-1) ...................................................................................... ............. 319 171 tx ho ring port - performance counters (rw) ................................................................................ ........ 319 172 tx ho ring port - performance counter shadow registers (ro) ............................................................ 319 173 tx ho ring port - defects .................................................................................................. ....................... 319 174 tx ho ring port - interrupt mask (rw) ...................................................................................... ............... 320 175 tx ho ring port - general interrupt (ro) ................................................................................... ............... 320 176 tx ho ring port - defect interrupt (ro) .................................................................................... ................ 320 177 ho poh monitor - received-64 byte trace message (ro) ...................................................................... 320 178 ho poh monitor - received 16-byte trace message (ro) ...................................................................... 321 179 ho poh monitor - accepted bytes (ro) ....................................................................................... ............ 321 180 ho poh monitor - expected j1 bytes (rw) .................................................................................... .......... 321 181 ho poh monitor - expected c2 bytes (rw) .................................................................................... ......... 321 182 ho poh monitor - received poh bytes (ro) ................................................................................... ....... 321 183 ho poh monitor - accepted poh bytes (ro) ................................................................................... ....... 322 184 ho poh monitor - configuration (rw) ........................................................................................ .............. 322 185 ho poh monitor - loopback control (rw) ..................................................................................... .......... 322 186 ho poh monitor - channel configuration (rw) ................................................................................ ........ 322 187 ho poh monitor - channel status (ro) ....................................................................................... ............ 324 188 ho poh monitor - channel defects (ro) ...................................................................................... ........... 324 189 ho poh monitor - j1 message status (ro) .................................................................................... ......... 324 190 ho poh monitor - defects (ro) .............................................................................................. .................. 325 191 ho poh monitor - latched defects (r/cow-1) ................................................................................. ....... 325 192 ho poh monitor - defect masks (rw) ......................................................................................... ............. 326 193 ho poh monitor - defects latched for pmfm (r/cow-0) ...................................................................... 3 26 194 ho poh monitor - defects pm (ro) ........................................................................................... .............. 327 195 ho poh monitor - defects fm (ro) ........................................................................................... ............... 327 196 ho poh monitor - defect configuration (rw) ................................................................................. .......... 328 197 ho poh monitor - defect summary (ro) ....................................................................................... .......... 328 198 ho poh monitor - defect summary mask (rw) .................................................................................. ..... 329 199 ho poh monitor - defect group summary (ro) ................................................................................. ..... 329 200 ho poh monitor - aps event (ro) ............................................................................................ ............... 329 201 ho poh monitor - latched aps event (r/cow-1) ............................................................................... .... 329 202 ho poh monitor - aps event mask (rw) ....................................................................................... ......... 329 203 ho poh monitor - aps interrupt (ro) ........................................................................................ .............. 330 - 12 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers list of tables (cont.) table page 204 ho poh monitor - performance counters (rw) ................................................................................. ...... 330 205 ho poh monitor - performance counters one second latch (ro) ......................................................... 330 206 ho poh monitor - performance counter shadow registers (ro) ........................................................... 330 207 ho poh monitor - performance counter configuration (rw) .................................................................. 3 31 208 ho poh monitor - counter reset (wo) ........................................................................................ ............ 331 209 ho poh monitor - pmfm configuration (rw) ................................................................................... ....... 331 210 tu-3 ptr tracker - general configuration (rw) .............................................................................. ........ 332 211 tu-3 ptr tracker - per channel configuration (rw) .......................................................................... .... 332 212 tu-3 ptr tracker - defects (ro) ............................................................................................ ................. 332 213 tu-3 ptr tracker - defects latched for interrupt (r/cow-1) ................................................................ 333 214 tu-3 ptr tracker - defects latched for pmfm (r/cow-0) ................................................................... 33 3 215 tu-3 ptr tracker - defects pm (ro) ......................................................................................... .............. 333 216 tu-3 ptr tracker - defects fm (ro) ......................................................................................... .............. 333 217 tu-3 ptr tracker - defect masks (rw) ....................................................................................... ............ 333 218 tu-3 ptr tracker - defect summary (ro) ..................................................................................... .......... 333 219 tu-3 ptr tracker - defect summary mask (rw) ................................................................................ .... 333 220 tu-3 ptr tracker - defect group summary (ro) ............................................................................... ..... 333 221 tu-3 ptr tracker - performance counters (rw) ............................................................................... ...... 334 222 tu-3 ptr tracker - performance counter shadow registers (ro) ......................................................... 334 223 transmit vc-3/sts-1/tug-3 time slot interchange (rw) ....................................................................... 334 224 receive vc-3/sts-1/tug-3 time slot interchange (rw) ........................................................................ 334 225 tu-3 ptr generator - general configuration (rw) ............................................................................ ...... 335 226 tu-3 ptr generator - per channel configuration (rw) ........................................................................ .. 335 227 tu-3 ptr generator - defects (ro) .......................................................................................... ............... 335 228 tu-3 ptr generator - defects latched for interrupt (r/cow-1) ............................................................ 33 6 229 tu-3 ptr generator - defects latched for pmfm (r/cow-0) ............................................................... 336 230 tu-3 ptr generator - defects pm (ro) ....................................................................................... ............ 336 231 tu-3 ptr generator - defects fm (ro) ....................................................................................... ............ 336 232 tu-3 ptr generator - defect mask (rw) ...................................................................................... ........... 336 233 tu-3 ptr generator - defect summary (ro) ................................................................................... ........ 336 234 tu-3 ptr generator - defect summary mask (rw) .............................................................................. .. 336 235 tu-3 ptr generator - defect group summary (ro) ............................................................................. ... 336 236 tu-3 ptr generator - performance counters (rw) ............................................................................. .... 337 237 tu-3 ptr generator - performance counter shadow registers (ro) ..................................................... 337 238 ho poh generator - channel control (rw) .................................................................................... ......... 337 239 ho poh generator - configuration (rw) ...................................................................................... ........... 338 240 ho poh generator - j1 message bytes (rw) ................................................................................... ...... 338 241 ho poh generator - poh insertion values (rw) ............................................................................... ..... 338 242 ho poh generator - poh port monitors (ro) .................................................................................. ....... 339 243 tu-3 retimer - general configuration (rw) .................................................................................. ........... 339 244 tu-3 retimer - per channel configuration (rw) .............................................................................. ........ 339 245 tu-3 retimer - defects (ro) ................................................................................................ ..................... 339 246 tu-3 retimer - defects latched for interrupt (r/cow-1) ..................................................................... ... 339 247 tu-3 retimer - defect masks (rw) ........................................................................................... ................ 340 248 tu-3 retimer - defect group summary (ro) ................................................................................... ........ 340 249 tu-3 retimer - sequencer configuration (rw) ................................................................................ ......... 340 250 tu-3 retimer - sequencer data (rw) ......................................................................................... .............. 340 251 au-3/4 retimer - general configuration (rw) ................................................................................ .......... 341 252 au-3/4 retimer - per channel configuration (rw) ............................................................................ ....... 341 253 au-3/4 retimer - defects (ro) .............................................................................................. .................... 341 254 au-3/4 retimer - defects latched for interrupt (r/cow-1) ................................................................... .. 341 - 13 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers list of tables (cont.) table page 255 au-3/4 retimer - defect masks (rw) ......................................................................................... ............... 341 256 au-3/4 retimer - defect group summary (ro) ................................................................................. ........ 341 257 au-3/4 retimer - ptr leak reset value (rw) ................................................................................. ........... 342 258 au-3/4 retimer - performance counters (ro) ................................................................................. ......... 342 259 ho interrupt controller - interrupts (ro) .................................................................................. .................. 342 260 ho interrupt controller - interrupt masks (rw) ............................................................................. ............ 343 261 ho interrupt controller - interrupt group summary (ro) ..................................................................... ..... 343 262 rx combus interface - general configuration (rw) ........................................................................... ....... 343 263 rx combus interface - per channel configuration (rw) ....................................................................... ... 344 264 rx combus interface - per channel status (ro) .............................................................................. ........ 344 265 rx combus interface - defects (ro) ......................................................................................... ................ 344 266 rx combus interface - defects latched for interrupt (r/cow-1) ............................................................ 3 44 267 rx combus interface - defects latched for pmfm (r/cow-0) ............................................................... 344 268 rx combus interface - defects pm (ro) ...................................................................................... ............. 344 269 rx combus interface - defects fm (ro) ...................................................................................... ............. 344 270 rx combus interface - defect masks (rw) .................................................................................... ........... 345 271 rx combus interface - defect group summary (ro) ............................................................................ .... 345 272 rx combus interface - per channel defects (ro) ............................................................................. ....... 345 273 rx combus interface - per channel defects latched for interrupt (r/cow-1) ....................................... 345 274 rx combus interface - per channel defects latched for pmfm (r/cow-0) .......................................... 345 275 rx combus interface - per channel defects pm (ro) .......................................................................... .... 345 276 rx combus interface - per channel defects fm (ro) .......................................................................... .... 345 277 rx combus interface - per channel defect masks (rw) ........................................................................ .. 346 278 rx combus interface - per channel defect summary (ro) ...................................................................... 346 279 rx combus interface - per channel defect summary masks (rw) .......................................................... 346 280 rx combus interface - per channel defect group summary (ro) ........................................................... 346 281 tx combus interface - general configuration (rw) ........................................................................... ....... 347 282 tx combus interface - aug1 configuration (rw) .............................................................................. ....... 347 283 tx combus interface - au-3 configuration (rw) .............................................................................. ......... 347 284 tx combus interface - tug-2 configuration (rw) ............................................................................. ....... 348 285 tx combus interface - tu-11/tu-12 configuration (rw) ....................................................................... ... 348 286 tx combus interface - defects (ro) ......................................................................................... ................. 348 287 tx combus interface - defects latched for interrupt (r/cow-1) ............................................................. 348 288 tx combus interface - defect masks (rw) .................................................................................... ........... 348 289 tx combus interface - defects latched for pmfm (r/cow-0) ................................................................ 34 8 290 tx combus interface - defects pm (ro) ...................................................................................... ............. 348 291 tx combus interface - defects fm (ro) ...................................................................................... ............. 348 292 tx combus interface - defect group summary (ro) ............................................................................ .... 349 293 tx combus interface - per channel defects (ro) ............................................................................. ........ 349 294 tx combus interface - per channel defects latched for interrupt (r/cow-1) ........................................ 349 295 tx combus interface - per channel defect masks (rw) ........................................................................ .. 349 296 tx combus interface - per channel defects latched for pmfm (r/cow-0) ........................................... 349 297 tx combus interface - per channel defects pm (ro) .......................................................................... .... 349 298 tx combus interface - per channel defects fm (ro) .......................................................................... .... 349 299 tx combus interface - per channel defect summary (ro) ...................................................................... 350 300 tx combus interface - per channel defect summary masks (rw) .......................................................... 350 301 tx combus interface - per channel defect group summary (ro) ........................................................... 350 302 tx combus interface - defect configuration (rw) ............................................................................ ........ 350 303 combus interrupt controller - interrupts (ro) .............................................................................. .............. 350 304 combus interrupt controller - interrupt masks (rw) ......................................................................... ........ 351 305 combus interrupt controller - interrupt group summary (ro) ................................................................. . 351 - 14 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers list of tables (cont.) table page 306 mapper interrupt controller - interrupts (ro) .............................................................................. .............. 351 307 mapper interrupt controller - interrupt masks (rw) ......................................................................... ......... 351 308 mapper interrupt controller - interrupt group summary (ro) ................................................................. .. 351 309 reserved registers ......................................................................................................... .......................... 351 310 latched alarm bit (l1alarm_name) transition selection ...................................................................... .... 356 311 latched alarm bit (l2alarm_name) transition selection ...................................................................... .... 359 - 15 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers features the ethermap-3 plus supports the following features: mappings ethermap-3 plus maps ethernet traffic of up to (8) 10/100 mb/s smii ports or (1)1000 mb/s gmii port onto sonet/sdh performs virtual concatenation for sonet/sdh, compensating for up to 48 ms of differential delay implements link capacity adjustment scheme (lcas) to allow the size of the virtual concatenation groups to be changed dynamically with hitless switching. ? supports both high order and low order virtual concatenation sts-3c spe sts-3 / sts-1 spe, sts-1-xv sts-3 / sts-1 / vt1.5 spe, vt1.5-xv sts-3 / sts-1 / vt2 spe, vt2-xv stm-1 / aug-1 / au-4 / vc-4 stm-1 / aug-1 / au-4 / vc-4 / tug-3 / tu-3 / vc-3, vc-3-xv 1 stm-1 / aug-1 / au-4 / vc-4 / tug-3 / tug-2 / tu-12 / vc-12, vc-12-xv stm-1 / aug-1 / au-4 / vc-4 / tug-3 / tug-2 / tu-11 / vc-11, vc-11-xv stm-1 / aug-1 / au-3 / vc-3, vc-3-xv stm-1 / aug-1 / au-3 / vc-3 / tug-2 / tu-12 / vc-12, vc-12-xv stm-1 / aug-1 / au-3 / vc-3 / tug-2 / tu-11 / vc-11, vc-11-xv all supported virtual concatenation mappings can be mixed according to the [g.707] multiplexing structure up to a total payload rate equivalent to one sts-3/stm-1 signal. supports a mix of 100 mbit/s and 10 mbit/s traffic (up to 8 ports). for 10/100 mb/s operation (up to 8 ports), can virtually concatenate up to 63 vc-12/vt2 spes or 64 vc-11/vt1.5-spes. for 100 mb/s operation, a single vc-4 or a single sts-3c spe can be used, or can virtually concatenate up to 64 vc-11s or up to 63 vc-12s or up to 3 vc-3s can virtually concatenate up to 64 vt1.5-spes or up to 63 vt2-spes or up to 3 sts-1-spes for 1000 mb/s supports either a single vc-4, or can virtually concatenate up to 3 vc-3s supports either a single sts-3c-spe, or can virtually concatenate up to 3 sts-1-spes encapsulation protocols ethermap-3 plus supports one of four encapsulation protocols per ethernet mac: laps (link access procedure sdh) lapf (link access procedure for framed mode service) gfp (generic framing procedure) ppp (with bcp support) 1. note: in itu-t sdh a vc-3 can either be high order (au-3/sts-1) or low order (tu-3). in the remainder of the ethermap-3 plus data sheet high order and low order refers to the type of path overhead bytes rather than the order of the path in the multiplexing hierarchy. though both low and high order vc-3 mapping is supported, vc-3 operation will be covered in the high order path sections. - 16 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ethernet ports the ethermap-3 plus provides the following ethernet port features: eight independent smii (serial medial independent interfaces) for 10/100 mbit/s ethernet global 125 mhz reference clock global synchronization signal lead selects phy or switch connection to external client single gmii (gigabit mii) for 1000 mbit/s ethernet lead shared with the smii ports selection of gmii or smii is selected through a lead ethernet management interface phy or switch selection 10/100/1000 mbit/s ethernet media access controller (mac) block compliant to ieee 802.3, 802.3u, 802.3x, 802.3z, and 802.3ac full duplex operation in 10/100/1000 mbit/s half duplex operation in 10/100 mbit/s mac control sub layer provides support for control frames including pause frames provides support for statistics gathering based on rmon mib group 1, rmon mib group 2, rmon mib group 3, rmon mib group 9, rmon mib 2, and the dot 3 ethernet mib sdram interface glueless interface to external 64 mbits, 128 mbits, or 256 mbits sdram devices 32 data, 13 address, 1 chip select, 1 clock, 1 clock enable, 1 row address strobe, 1 column address strobe, 1 write enable strobe, 1 data bus mask, and 2 bank address leads buffers tx/rx data transfers clock frequency of 100 mhz programmable refresh period cas latency of 3 supported refresh operation is transparent to the user trp timing of the selected sdram must be below 30 ns. telecom bus timing a single telecom bus interface is provided for interfacing to the sonet/sdh line through one of transwitch ? s toh/poh terminator devices such as the phast ? -3n or the phast-12e/pop-12 chip set. timing for adding tributaries to the add bus is derived from either the drop bus or the add bus. the ethermap-3 plus provides the following timing modes for the add bus: drop bus timing add bus timing is derived from the drop bus timing input signals drop bus: c1j1, spe, optional v1, data, clock and parity signal leads are inputs add bus: c1j1, spe, optional v1, data, clock, parity and add indication signal leads are outputs. the c1j1, spe, optional v1, and clock can be optionally disabled. add bus timing (two modes) add bus timing is derived from the add bus timing input signals - 17 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers drop bus: c1j1, spe, optional v1, data, clock, and parity signal leads are inputs add bus: c1j1, clock, optional v1 and spe signal leads are inputs; data, parity and add indication signal leads are outputs add bus timing is derived from an external reference clock drop bus: c1j1, spe, optional v1, data, clock and parity signal leads are inputs add bus: c1j1, spe, optional v1, data, clock, parity and add indication signal leads are outputs alarm indication port interface high order alarm indication port to support ring applications low order alarm indication port to support ring applications poh port interface high order poh port for access to poh bytes low order poh port for access to poh bytes microprocessor interface 16-bit address and data bus motorola or intel style split bus supported interrupt request lead interrupt mask bits for controlling generation of hardware interrupt requests jtag interface ieee 1149.1 compliant tap is provided for board level testing. - 18 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers block diagram figure 1. functional block diagram of the ethermap-3 plus receive ethernet side frame format block transmit ethernet side gfp, laps, lapf, ppp decapsulation block 8 x 10/100/1000 mbit/s ethernet media access controllers (macs); half and full duplex operation; rmon statistics counters; ethernet line side loopbacks 8 x 10/100 mbit/s ethernet mac smii i/fs; 1 x 1000 mbit/s ethernet mac gmii i/f (shared) tr a n s m i t ethernet side frame reinterleave logic block micro- processor interface transmit sonet/sdh side gfp, laps, lapf, ppp encapsulation block transmit sonet/sdh virtual concatenation and lcas processing block mapper block sonet/sdh (vt1.5/vc-12/ vc-3/vc-4) receive sonet/sdh virtual concatenation and lcas processing block demapper block sonet/sdh (vt1.5/vc-12/ vc-3/vc-4) clock generator block jtag block rx high order poh port ref clocks tx high order poh port drop telecom bus add telecom bus parallel telecom bus interface ethernet ports rx low order poh port rx high order alarm indication port rx low order alarm indication port tx low order poh port tx high order alarm indication port tx low order alarm indication port address data sdram controller block sdram interface block alarm processing block performance and statistics counters block operation control block ethernet client perspective telecom bus perspective to external sdram memory - 19 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers block diagram description the following sections describe the functional block diagram of the ethermap-3 plus shown in figure 1 above: data processing/flow in general, the ethermap-3 plus provides functionality for mapping and demapping of ethernet frames to and from sonet/sdh virtual concatenated tributary structures in both lcas/non-lcas mode. the figures below represent the virtual tributary structures that are supported by the ethermap-3 plus device. figure 2 shows the low order virtual concatenation structure for vt1.5-xv spe, vt2-xv spe, vc-11-xv and vc-12-xv. a vc-11-xv/vt1.5-xv spe provides a payload area of x vc-11/vt1.5 spe payload capacity as shown. the ethernet payload is mapped into x individual vc-11s/vt1.5 spes which form the vc-11- xv/vt1.5-xv spe. each vc-11/vt1.5 spe has its own poh and can be sent throughout the sonet/sdh network individually and then reassembled at the destination. the same principle applies for a vc-12-xv/vt2- xv spe. figure 2. low order virtual concatenation structure for sonet/sdh figure 3 shows the high order virtual concatenation structure for sts-1-xv and vc-3-xv. this structure provides a contiguous payload area of x vc-3/sts-1 spe with a payload capacity of x*48384 kbit/s as shown. the payload capacity (i.e., the encapsulated ethernet frames) is mapped into x individual vc-3s/sts-1 spes which form the vc-3-xv/sts-1-xv spe. for high order vc-3s and sts-1 spes fixed stuff column are added ( figure 4 ). each vc-3/sts-1 spe has its own poh. just like for the low order case above, the vc-3s/sts-1- spes can travel through the sonet/sdh network independently and are reassembled at their destination to recover the ethernet data. v5 j2 1 1 26 vc-11/vt1.5 spe #x 1 1 4 x x x 25 v5 j2 n2 k4 1 4 1 c-11-xc/vt1.5-xc spe vc-11/vt1.5 spe #1 500 s 500 s vc-11-xv/ payload capacity x x 34 c-12-xc/vt2-xc spe payload capacity vc-12/vt2 spe #x vc-12/vt2 spe #1 vt1.5-xv spe vc-12-xv/ vt2-xv spe 35 - 20 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 3. high order virtual concatenation structure for sonet/sdh j1 b3 1 1 85 vc-3/sts-1 spe #x 1 1 9 x x x 84 j1 b3 c2 g1 1 9 1 c-3-xc/sts-1-xc spe vc-3/sts-1 spe #1 125 s 125 s vc-3-xv/ n1 k3 f2 f3 h4 125 s sts-1-xv spe payload capacity - 21 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 4. fixed stuff columns in high order vc-3-xv/sts-1-xv spe on the sonet/sdh side, the ethermap-3 plus supports an stm-1/sts-3/sts-3c like structure using a single transwitch defined telecom bus operating at 19.44 mhz. on the ethernet line side, the ethermap-3 plus supports up to eight 10/100 mbit/s ethernet ports or one 1000 mbit/s (gigabit) ethernet port. the eight 10/100 mbit/s ethernet ports each support the industry standard smii interface. the single gigabit ethernet port supports the industry standard gmii interface and is lead shared with the smii interfaces. in the transmit direction (ethernet-to-sonet/sdh), the ethermap-3 plus terminates the 10/100/1000 mbit/s ethernet traffic. the ethernet frames from configured port(s) are extracted and buffered in an external sdram memory. the external sdram is primarily used for implementing flow control when the ethernet line side bandwidth is greater than the allocated bandwidth on the sonet/sdh side (i.e., an over-subscription situation). based on system configuration, ethernet frames from each of the ethernet ports are encapsulated using one of the supported link layer protocols: gfp, laps, lapf or ppp independently. the encapsulated j1 b3 1 1 87 1 1 9 x x x 84 1 c-3-xc/sts-1-xc spe 125 s 125 s vc-3-xv/ 125 s sts-1-xv spe payload capacity vc-3/sts-1 spe #x j1 b3 c2 g1 1 9 n1 k3 f2 f3 h4 vc-3/sts-1 spe #1 30 59 fixed stuff - 22 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ethernet frames are then byte interleaved over preselected sonet/sdh containers and transported using virtual concatenation. the ethermap-3 plus provides complete high and low order path overhead generation for the sonet/sdh containers. the bandwidth of sonet/sdh containers using virtual concatenation, are allowed to increase or decrease in a hitless fashion through the use of an integrated link capacity adjustment scheme (lcas). the sonet/sdh containers carrying ethernet frames are then transmitted to an upstream sonet/sdh overhead terminator device such as transwitch ? s phast-3n, using a parallel telecom bus. in the receive direction (sonet/sdh-to-ethernet), the ethermap-3 plus terminates a parallel telecom bus with sonet/sdh containers carrying encapsulated (gfp, laps, lapf, ppp) ethernet frames. the ethermap-3 plus provides complete high and low order path overhead processing for the sonet/sdh tributaries. the sonet/sdh containers are then extracted and buffered using the external sdram memory. this memory is primarily used for providing alignment and differential delay compensation for the select sonet/sdh containers which form part of the virtual concatenation group. once alignment and delay compensation has been achieved, the ethernet frames are byte reinterleaved from the sonet/sdh containers to form their original frame structure on a per port basis. the ethernet frames are then extracted from one of the encapsulations (gfp, laps, lapf or ppp) used at the transmit side and passed onto the ethernet port for transmission to the external client(s). 10/100/1000 mbit/s ethernet media access controller (mac) block the interface for the 10/100 mbit/s ethernet ports and a 1000 mbit/s ethernet port are supported by an integrated ethernet mac block. this block supports the eight 10/100 mbit/s ports and the single 1000 mbit/s port. the 10/100/1000 mbit/s ethernet mac block is ieee 802.3, 802.3x, 802.3z and 802.3ac compliant and supports full duplex/half duplex for 10/100 mbit/s ethernet mac and only full duplex for 1000 mbit/s ethernet mac (mac implements the ieee 802.3 mac control layer and pause operation for flow control) mode of operation. the main features which are supported by this block are as follows: connection to external 10/100/1000 mbit/s ethernet phys or 10/100/1000 mbit/s ethernet switch devices via either 8 smii interfaces or a single gmii interface line side loopbacks for diagnostic capability verify frame integrity (fcs and length checks) egress ethernet frame encapsulation, such as, padding to achieve minimum length and fcs generation programmable ipg/ifg maximum frame size - 9600 bytes in smii mode, 1650 bytes in gmii mode transparent to ieee 802.3-1998 vlan (virtual lan) byte supports ieee 802.3 mandatory control and management registers over subscription support by device configuration and flow control option to support ieee 802.3-1998 flow control at each ethernet port programmable watermarks for fifo full conditions in full duplex mode, automatic generation of pause frames based on fifo fill levels. in half duplex mode, automatic back pressure flow control based on fifo fill levels. control to disable acting on received pause frames, that enables transparent transmission of the ethernet pause frame and reconciliation of frames. control and statistics (to ieee 802.3z-1998) that includes among others: detection of device, initialization, device id standard control and status registers grouped by function: mac receive and transmit control registers, mac receive and transmit status registers, rmon registers (for network management), flow control registers, mii management registers, ethernet interface control and status registers performance counters to ensure roll-over compliance with standards - 23 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers provides statistic counters to support rmon implementations (minimum support for ethernet statistics group, ethernet history group, alarm group, event group). sonet/sdh mapping the ethermap-3 plus device supports mapping of ethernet frames over sonet/sdh containers using the mappings shown in figure 5 . figure 5. mapping of ethernet frames over sonet/sdh mapper block this block provides mapping and multiplexing for low order and high order tributaries (carrying ethernet framed data) into sts-3/sts-3c/stm-1 structures transmitted on the add side telecom bus. a range of sonet/sdh rates and format mappings are supported as indicated below: sts-3c spe sts-3 / sts-1 spe sts-3 / sts-1 / vt1.5 spe sts-3 / sts-1 / vt2 spe stm-1 / aug-1 / au-4 / vc-4 stm-1 / aug-1 / au-4 / vc-4 / tug-3 / tu-3 / vc-3 stm-1 / aug-1 / au-4 / vc-4 / tug-3 / tug-2 / tu-12 / vc-12 stm-1 / aug-1 / au-4 / vc-4 / tug-3 / tug-2 / tu-11 / vc-11 stm-1 / aug-1 / au-3 / vc-3 stm-1 / aug-1 / au-3 / vc-3 / tug-2 / tu-12 / vc-12 stm-1 / aug-1 / au-3 / vc-3 / tug-2 / tu-11 / vc-11 vt1.5-xc payload c-11-xc vt2-xc payload c-12-xc sts-1-xc payload c-3-xc aug-1 tug-3 tug-2 au-4 sts-3c au-3 sts-1 tu-3 tu-12 vt2 sts-3c spe vc-4 vt2 spe vc-12 vt1.5 spe vc-11 vc-3 vt1.5 payload c-11 vt2 payload c-12 sts-1 payload c-3 sts-3c payload c-4 x3 x7 x3 x4 x1 x3 x7 x1 1/x 1/x 1/x encapsulated ethernet frames vt group sonet sdh multiplexing mapping aligning 1/x virtual concatenation pointer processing sts-1 spe vc-3 tu-11 vt1.5 - 24 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers sonet low order: supports up to 84 x vt1.5s or up to 63 vt2s sonet high order: supports up to 3 x sts-1 spes sdh low order: up to 84 x vc-11s or supports up to 63 x vc-12s or up to vc-3s sdh high order: supports up to 3 x vc-3s low order vt/vc tributaries are formatted into an sts-3 or stm-1 structure. the pointer value carried in the v1 and v2 bytes is transmitted with a fixed value of 78 for tu-11/vt1.5 and 105 for tu-12/vt2. the microprocessor writes the signal label, and the value of the j2 message as a 16-byte message. the device provides either single-bit or extended rdi using the v5 and k4/z7 bytes. local alarms, or the microprocessor, can generate the remote payload, server, or connectivity defect indications. the remote error indication (rei) is inserted from the bip-2 errors detected on the receive side, and bip-2 parity is generated for the v5 byte. control bits are provided for generating unequipped status, generating vt/tu ais, and inserting rei and bip- 2 errors in the v5 byte. control bits are also provided that enable the microprocessor to insert overhead byte test values, including the v4 byte. a list of the vt/tu overhead byte generation functions is listed below: j2 byte 16 byte microprocessor written message j2 forced to zero option v5 and k4/z7 byte signal label insertion rei insertion (from receive side) rfi insertion host processor control bip-2 calculation and insertion rdi insertion (from receive side) enable bits for alarms and host processor control single or extended rdi (bit 8 in v5 byte and bits 5, 6, 7 in k4/z7 byte) generate rdi for at least 20 superframes mask alarm bits from sending rdi microprocessor control control spare bits in k4/z7 byte all bits in single bit rdi bits 1 through 4, and bit 8 in k4/z7 byte n2/z6 byte: no tandem connection support unequipped channel generation supervisory unequipped generation vt/tu ais generation low order vt/tu pointer generation fixed to 105 for tu-12/vt2 asynchronous format fixed to 78 for tu-11/vt1.5 asynchronous format high order vc-3/sts-1 spe overhead byte generation insertion of the poh bytes into the sts-1s and vc-3s that are being mapped with the asynchronous line signals j1 byte 16-byte message insertion - etsi applications 64-byte message insertion - ansi applications h4 byte the ability to generate the v1 sequence for lower order tributaries should be provided when not in the higher order virtual concatenation mode - 25 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers c2 byte signal label insertion b3 byte bip-8 calculation and insertion mask bit g1 byte single-bit (etsi) or extended rdi generation (ansi) rei (path febe) insertion bit 8 insertion n1/z5 byte: no tandem connection support transmit path ais generation for the sts-1/au-3/tug-3 overrides unequipped generation transmit unequipped generation for the sts-1/au-3/tug-3 supervisory unequipped generation option high order tu-3 (vc-3)/sts-1 pointer generation: in drop bus timing mode the pointer bytes follow the drop c1j1 pulses in add bus timing mode 1 the pointer bytes follow the add c1j1 pulses in add bus timing mode 2 the pointer bytes are fixed at 0 high order vc-4/sts-3c spe overhead byte generation can be generated by phast-3n or ethermap-3 plus high order vc-4/sts-3 spe pointer generation all pointer generation is handled by an external overhead terminator device such as phast-3n or pop-12 demapper block the demapper block provides the demapping and demultiplexing of the low order and high order tributaries from sts-3/sts-3c/stm-1 structures received on the drop side telecom bus. the range of formats that are supported by the mapper block are also supported by the demapper block as shown below: sts-3c spe sts-3 / sts-1 spe sts-3 / sts-1 / vt1.5 spe sts-3 / sts-1 / vt2 spe stm-1 / aug-1 / au-4 / vc-4 stm-1 / aug-1 / au-4 / vc-4 / tug-3 / tu-3 / vc-3 stm-1 / aug-1 / au-4 / vc-4 / tug-3 / tug-2 / tu-12 / vc-12 stm-1 / aug-1 / au-4 / vc-4 / tug-3 / tug-2 / tu-11 / vc-11 stm-1 / aug-1 / au-3 / vc-3 stm-1 / aug-1 / au-3 / vc-3 / tug-2 / tu-12 / vc-12 stm-1 / aug-1 / au-3 / vc-3 / tug-2 / tu-11 / vc-11 sonet low order: supports up to 84 x vt1.5s or up to 63 vt2s sonet high order: supports up to 3 x sts-1 spes sdh low order: up to 84 x vc-11s or supports up to 63 x vc-12s or up to 3 x vc-3s sdh high order: supports up to 3 x vc-3s - 26 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers the ethermap-3 plus device provides processing of the sonet/sdh overhead bytes as follows: microprocessor access to all vt/tu overhead bytes, the v1/v2 pointer bytes, and the v4 byte for each channel are available for a microprocessor read cycle, as well as the h4 and v5/k4 bytes. h4 byte multiframe detectors or v1 pulse (c1j1v1) reference input determines location of v1/v2 pointer bytes pointer tracking for v1/v2 pointer bytes etsi/itu/ansi state machine incorrect size bits detection positive/negative justification 8-bit counters for low order tributaries, this demapper block performs pointer processing based on the location of the v1 and v2 bytes. the pointer bytes are monitored for loss of pointer and alarm indication signal (ais). the pointer tracking process is based on etsi/itu-t standards, which also meets ansi requirements. pointer increments and decrements are also counted, and the size bits are monitored for the correct value. this block also processes and monitors the various alarms found in the four overhead bytes. these operations including signal label mismatch detection, unequipped status detection, bip-2 parity error detection and bit/block error counter, rei error counting, rfi detector, and single-bit or extended remote defect indications (rdi). the rx demapper performs a 16-byte j2 trail trace comparison on the channels selected. n2/z6 byte processing is not supported. below is a bullet list of the high order vc-3/sts-1 spe overhead byte processing that is performed by the demapper block: all received poh bytes and applicable alarm indications are made accessible for the micro-processor. j1 byte trace mismatch detection 16-byte trail trace alignment (mfas pattern) and comparison - etsi applications 64-byte message alignment (multiframe alignment on mfas pattern or cr/lf alignment) h4 byte the ability to detect and generate a v1 pulse from the h4 byte sequence for lower order tributaries is supported. c2 byte signal label mismatch unequipped detection and generation vc ais detection g1 byte single-bit (etsi) or extended rdi detection (ansi) rei (path febe) calculation with 16-bit bit or block error count bit 8 access for host processor access n1/z5 byte: not supported the demapper provides complete tu-3 pointer tracking state machines including applicable alarm indications. other higher order poh processing can be done by an external device such as the phast-3n or pop-12 device; high order pointer processing must be done by an external device such as the phast-3n or pop-12. - 27 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ethernet ports the ethermap-3 plus provides eight independent full duplex/half duplex serial media independent interfaces (smii) to support 10/100 mbit/s ethernet traffic and a single full duplex gmii port to support 1000 mbit/s ethernet traffic. please note, the smii interfaces are signal-shared with the gmii interface and they cannot be used together. on power-up, the gmii/smii lead (see ? lead descriptions ? on page 32 ) selects between smii and gmii interfaces. the smii ports allow the ethermap-3 plus to be connected to an external 10/100 mbit/s ethernet client (phy/switch). the configuration choice (phy/switch) is made on power-up/initialization through the phy/mac signal lead (see ? lead descriptions ? on page 32 ). the smii interface is comprised of two signals per port (tx data and rx data), a global synchronization signal and a global 125 mhz reference clock. up to eight 10/100 mbit/s ethernet signals (or any combination). the gigabit media independent interface (gmii) is used to allow the mapper to connect to an external 1000 mbit/s ethernet client (phy/switch). the ethermap-3 plus device supports a single gmii interface. please note, the gmii interface is signal-shared with the smii interfaces and the configuration choice is made on power-up/initialization. the gmii interface is comprised of two independent rx and tx 8-bit data paths, a transmit enable signal, and a receive data valid signal. status outputs report when coding violations are detected. network status inputs are provided for reporting errored frames and frame received in error. all signals are synchronous to the clock. a single ethernet management interface is provided on the ethermap-3 plus to connect to an external ethernet phy in order to configure and control its operation. this interface is used by both of the eight 10/100 mbit/s ports or a single 1000 mbit/s port. it is comprised of an output management data clock signal and a bidirectional management data signal that allows serial data to be clocked in and out of the external phy device. all data transfers are synchronous to the clock signal and provides support for up to 32 phys. microprocessor interface the ethermap-3 plus ? s microprocessor interface provides support for either a standard motorola, or a intel split address/data bus interface which allows access to the ethermap-3 plus ? s memory map register locations through a 16-bit data bus. there is a 16-bit address bus. a15 is the most significant bit in the location ? s address. a0 of the device will correspond to a1 of the microprocessor address bus. the mode of operation is configurable via two external package signal leads. an interrupt request lead is provided to allow the maskable interrupt bits to generate interrupts to the external microprocessor, thus reducing required host cpu bandwidth. sdram memory interface this interface is used to allow the mapper to connect an external sdram memory device. the external sdram memory device is used for buffering of ethernet traffic in both directions and provides a ? glueless ? interface to 64 mbits, 128 mbits and 256 mbits external sdram memory devices. virtually concatenated vcs are realigned and differential delay is accommodated by the sdram during the reconstruction process of the received frame. parallel telecom bus interface the telecom bus interface enables the ethermap-3 plus to connect to an upstream sonet/sdh line overhead terminator such as transwitch ? s phast-3n for oc-3/stm-1 applications. for oc-12/stm-4 applications, the ethermap-3 plus would connect to transwitch ? s pop-12/phast-12e chip set. the telecom bus interface is collectively comprised of a single drop (rx) and a single add (tx) bus. the ethermap-3 plus supports a single telecom bus architecture which consists of a single drop and a single add bus. this is the same bus architecture supported by other transwitch mappers (e.g., tl3m) and - 28 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers sonet/sdh overhead terminators (e.g., phast-3n, phast-12e, pop-12) products. the telecom bus operates at 19.44 mhz rate. the telecom bus interface consists of byte wide data, 19.44 mhz (stm-1/sts-3) clock, spe indication, c1j1(v1) pulses, even or odd parity indication, and an add bus active indicator. the ethermap-3 plus supports either drop bus or add bus timing modes. the abust (see ? lead descriptions ? on page 32 ) lead is used to provide this selection. this approach prevents bus contention upon power up or device reset. drop bus timing mode: in this mode, the add bus timing is derived from the drop bus timing input signals. when drop bus timing mode is selected, the add bus interface output leads are byte-wide data, a parity indicator, and an add-to-bus indicator. the add bus clock, spe and c1j1v1 signals, which are derived from the drop bus, can be output or disabled. the selection is performed by a package lead. note the following restrictions apply when using drop bus timing mode: 1) in sonet (sts-3 / sts-1-spes) mode, high order virtual concatenation is not supported. 2) in sonet (sts-3 / sts-1 spes / vt1.5s) mode, selection of low order tributaries (vt1.5s) for a virtual concatenation group is restricted to the same sts-1 spe. note that this means that any virtual concatenation group in this mode is limited to a maximum of 28 vt1.5s. 3) in sdh (stm-1 / au-3 / vc-3 / tug-2s / tu-12s / vc-12s) mode, selection of low order tributaries (vc-12s) for a virtual concatenation group is restricted to the same vc-3. note that this means that any virtual concatenation group in this mode is limited to a maximum 21 vc-12s. add bus timing mode(s): in these modes, the add bus interface timing is independent of the drop bus interface timing and the above restrictions do not apply. using a control bit, the add bus interface timing signals can be configured as follows: add bus timing mode 1: byte clock, 19.44 mhz (input); spe indicator (input); c1j1v1 indicator (input); byte-wide data (output); parity indicator (output); add-to-bus indicator (output); note: in this timing mode, the external timing source must ensure the three pointers (j1 pulses) when operating in sts-3/au-3 mode, are synchronized and fixed relative to each other (i.e., there must not be any pointer movements relative to each other). the same principle applies when operating in stm-1 or sts-3c mode; no pointer adjustments are allowed on the add bus. the transwitch phast-3n overhead terminator device can provide the external timing required for this mode. add bus timing mode 2: the add bus interface signals are as follows: byte clock, 19.44 mhz (output), derived from input clock lead; spe indicator (output); c1j1v1 indicator (output); byte-wide data (output); parity indicator (output); add-to-bus indicator (output); note: in this timing mode, the ethermap-3 plus sources the timing signals. drop bus parity can be configured to be checked over data only or over all bus signals, and to check for even or odd parity. the drop bus clock is monitored for stuck high and stuck low conditions. add bus parity can be generated as odd or even and can be generated over data only or over all signals. the add to bus indicator - 29 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers goes active to indicate when vt/tu/vc/spe data is being added to the add telecom bus. when data is not being added to the add telecom bus, the add data and parity are tristated. high and low order poh (path overhead byte) port interface the poh byte interface provides an alternative access to all of the sonet/sdh low order and high order tributary poh bytes for external processing. there are two interfaces. one interface is for vt1.5/vt2/vc- 11/vc-12 poh and the second interface is for sts-1/vc-3 poh or sts-3c/vc-4 poh. individual poh fields except tti, signal label and bip-2/bip-8 fields can be inserted into the poh from the transmit poh byte interface. all poh bytes are provided at their respective receive poh byte interface for external processing. high and low order alarm indication port interface the alarm indication port is provided to transport the remote information (ri) signal from a mate poh monitor to the poh generator. the remote information includes rei, rdi and various extended rdi indications. there are two separate alarm indication ports; one for vt1.5/vt2/vc-11/vc-12 ri, and one for sts-1/vc-3 ri or sts-3c/vc-4 ri. alarms and performance monitoring blocks this block maintains and updates the statistics/performance counters for gfp, laps, lapf, ppp (for all ethernet ports) and is accessible by the host. the following types of statistics/performance counters are provided by this block: flag error counters payload size violation counters fcs error counters control field mismatch counters total number of payload frames/octets transmitted counters total number of payload frames/octets received counters mapper/demapper statistics/performance counters (for all tributaries) are grouped within and are a part of the mapper/demapper block. jtag interface this interface provides a five signal boundary scan capability that conforms to the ieee 1149.1 standard. this standard provides external boundary scan functions to read and write the external input/output leads from the tap for board and component test. in addition to the tap, a lead is provided to place the output buffers in a high impedance state for systems that do not support the ieee 1149.1 standard. power-up sequencing during power-up, i/o supply voltage vdd33 (3.3v) must lead the vdd18 (1.8v), vddp18 (1.8v) and vddpa18 (1.8v) supplies. in addition, the core supply voltage (vdd18) needs to be brought up after i/o supply voltage, and can be brought up together with vddp18 and vddpa18 supplies. after power up, the i/o supply voltage must not go below the core supply voltage by more than 0.5v at any time, including power down. the maximum interval that vdd18, vddp18 and vddpa18, must be powered up after vdd33 depends on the slew rate of power ramp-up in customer ? s application. - 30 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers application example the ethermap-3 plus can be used in a broad array of telecommunications applications, such as: sonet/sdh add/drop and terminal multiplexers multi-service access platforms (msap) compact access or cpe platforms ip dslams wireless backhaul electronics (rnc/bsc) figure 6. typical application using the ethermap-3 plus and phast-3n devices figure 6 shows a multiservice stm-1/sts-3 application using the ethermap-3 plus . the temx28 ? device provides access to 28xds1 or 21 e1 channels of the sts-3/stm-1 signal. the two ethermap-3 plus devices are used to map gigabit ethernet into an sts-1-spe/vc-3 container and a mix of 10/100 mbit/s ethernet traffic into vt1.5-spe/vt-2-spe/vc-11/vc-12. as is demonstrated by this application, a very small number of transwitch components enables a board to be developed which can be used to simultaneously support a mixture of 10/100/1000 mbit/s ethernet traffic and t1/e1 traffic. by adding transwitch ? s tl3m device to the telecom bus, ds3 and e3 can also be supported. phast ? -3n ethermap ? -3 plus temx28 ? oc-3/stm-1 up to 28xds1 / 21xe1 sdram multi-service ethernet aggregation with oc-3/stm-1 uplink ethermap ? -3 plus sdram 10/100 mbit/s 10/100 mbit/s 1000 mbit/s gigabit ethernet phy 1000 mbit/s smii interfaces smii interfaces gmii interface line add bus drop bus x8 x16 ethernet switch (24 ports) txc-04236 txc-04236 - 31 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers lead diagram figure 7. ethermap-3 plus txc-04236 lead diagram bottom view 123 y w v u t r p n m l k j h g f e d c b a notes: 1. this is the bottom view. the leads are solder balls. see figure 88 for package information. this view is rotated relative to the bottom view in figure 88 . 2. power supply leads are shown as solid black circles, ground leads as cross-hatched circles. 4 5 6 7 8 9 101112 1314 1516 17181920 - 32 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers lead descriptions power supply, ground, and no connect leads symbol lead no. i/o/p* name/function vdd33 e7, e9, e12, e14, g5, g16, j5, j16, m5, m16, p5, p16, t7, t9, t12, t14 p vdd33: +3.3 volt power supply, 5% ( see ? power-up sequencing ? on page 29 ). vdd18 e6, e8, e10, e11, e13, e15, f5, f16, h5, h16, k5, k16, l5, l16, n5, n16, r5, r16, t6, t8, t10, t11, t13, t15 p vdd18: +1.8 volt power supply, 5% ( see ? power-up sequencing ? on page 29 ). vss a1, a20, b2, b19, c3, c18, d4, d17, e5, e16, f6, f7, f8, f9, f10, f11, f12, f13, f14, f15, g6, g7, g8, g9, g10, g11, g12, g13, g14, g15, h6, h7, h8, h9, h10, h11, h12, h13, h14, h15, j6, j7, j8, j9, j10, j11, j12, j13, j14, j15, k6, k7, k8, k9, k10, k11, k12, k13, k14, k15, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, m6, m7, m8, m9, m10, m11, m12, m13, m14, m15, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, t5, t16, u4, u17, v3, v18, w2, w19, y1, y20 p ground: 0 (zero) volts reference. vddp18 y3 p vddp18: +1.8 volt digital power supply for the pll, 5% ( see ? power-up sequencing ? on page 29 ). vddpa18 u6 p vddpa18: +1.8 volt analog power supply for the pll, 5% ( see ? power-up sequencing ? on page 29 ). vssp18 w4 p vssp18: digital ground for the pll. vsspa18 w5 p vsspa18: analog ground for the pll. nc a2, a6, a10, a11, a19, b1, b3, b7, b11, b15, b18, b20, c2, c4, c8, c14, c17, c19, d5, d13, d16, d18, u8, u18, v2, v4, v7, v17, v19, w1, w3, w10, w14, w18, w20, y2, y9, y10, y15, y19 - no connect: these leads are not to be connected, not even to another no connect lead, and must be left floating. connection of an nc lead may impair performance or cause damage to the device. nc leads that are currently unused may be assigned functions in a future version of the device, affecting its usability in applications which have not left them floating. * note: i = input; o = output; od=open drain output; p = power; t = tristate: - 33 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers drop side low order tributary telecom bus interface symbol lead no. i/o/p type name/function dd(7-0) d10, a9, b9, c10, a12, c9, a8, b10 i lvttl-5 drop bus data in: byte wide data corresponding to the stm-1/sts-3c/sts-3 signal from the drop bus. the first bit received (dropped) corresponds to bit 7. dclk b12 i lvttl-5 drop bus clock: this clock operates at 19.44 mhz for stm- 1/sts-3c/sts-3 operation and is used to clock data and other signals into the ethermap-3 plus . drop bus byte wide data, the parity bit, spe indication, and the c1j1(v1) signals are clocked into the ethermap-3 plus core on negative transitions of this clock. this clock is also used for timing and may be used to derive the like named add bus byte wide data, add, vt/tu indications, and parity bits. in drop timing mode, this clock is used to source the add traffic and should therefore be +/- 20 ppm maximum. if drop timing mode is selected, this clock must be present before the initial configuration of the device. dc1j1v1 a13 i lvttl-5 drop bus spe indicator/multiframe pulse: an active high timing signal that carries frame and spe information. is high during the j0 and j1 bytes in the stm- 1/sts-3c/sts-3 payload. three j1 pulses are present for sts-3 operation and one j1 pulse is present for stm-1/sts-3c operation. the v1 pulse is optional in the c1j1 signal. when the v1 pulse is not provided, the ethermap-3 plus core provides h4 detectors to determine the location of the v1/v2 bytes in place of using the v1 pulse. when the v1 pulses are provided, there will up to three v1 pulses for sts-3 operation and one v1 pulse for stm-1/sts-3c operation. the dc1j1v1 signal works in conjunction with the dspe signal. the c1 pulse identifies the location of the j0 byte in the stm-1/sts-c/sts-3 signals, when dspe signal is low. the j1 pulses identify the starting location of the j1 bytes in the stm-1/sts-3c/sts-3 signal when dspe is high. the v1 pulses occur every four frames (after the frame where the h4 byte is set to 00h) following the j1 pulse(s). dspe d11 i lvttl-5 drop bus spe indicator: a signal that is active high during each byte of the stm-1/sts-3c/sts-3 poh and payload bytes, and low during transport overhead byte times. dpar c11 i lvttl-5 drop bus parity bit: parity bit input signal that represents the parity calculation for each data byte, spe, and c1j1v1 signal from the bus. even or odd parity may be detected, and an option for checking the parity over dd(7-0) only or over all of the drop bus signals is provided. a parity error is reported but otherwise has no effect on the operation of the ethermap-3 plus core. - 34 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers add side low order tributary telecom bus interface symbol lead no. i/o/p type name/function ad(7-0) d6, d7, c6, b5, a4, b6, c7, a5 o(t) lvcmos 8 ma add bus data byte in: byte wide data that corresponds to the selected vt/tu//vc. aclk b8 i/o lvttl-5/ lv c m o s 12 ma add bus clock: this clock operates at 19.44 mhz. when add bus timing is selected and ctbadd =0, a clock on this input must be provided for add bus timing. in this case ac1j1v1 and aspe are clocked in on negative transitions of this clock while ad(7-0), apar, and add are clocked out on positive transitions of this clock. this above case is the default value for ctbadd. when add bus timing is selected and ctbadd =1, a clock is output on this lead. ac1j1v1, aspe, ad(7-0), apar, and add are clocked out on positive transitions of this clock. in that case, rtclk and dclk clock inputs must be active. when drop bus timing is selected, an option (abte is low) is provided for outputting this clock along with the other add bus signals, which are derived from dclk, otherwise this lead is disabled. if add slave timing mode is selected, this input clock must be already present during the initial configuration of the device. if add master timing mode is selected, this output clock must be pulled high with a weak pull-up (like 10k ohm). after a hard reset, the first microprocessor access must be to set the ctbadd register to 1. at this moment, the ethermap-3 plus will be able to drive the clock. ac1j1v1 a7 i/o lvttl-5/ lv c m o s 8 ma add bus spe indicator/multiframe pulse: when add bus timing is selected and ctbadd =0, this signal is an input and must be provided for add bus timing. when add bus timing is selected and ctbadd =1, this signal is output by the device for add bus timing. composite active high input timing signal that carries stm-1, sts-3c, or sts-3 starting frame and j1 byte location information. this timing signal functions in conjunction with the aspe signal. the c1 (j0) pulse identifies the location of the first c1 (j0) byte in the sonet/sdh frame when aspe is low. a j1 pulse identifies the starting location of the j1 byte for the vc-4 signal or sts-3c-spe or three j1 pulses identify the starting location of the three j1 bytes for the sts-1-spe signals when aspe is high. one or more v1 pulses may be present for asynchronous vt/tu mappings to determine the starting location of the v1 byte. when drop bus timing is selected, an option (abte is low) is provided for outputting this signal, otherwise this lead is disabled. - 35 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ethernet gmii/ 8xsmii interfaces the control lead gmii/smii selects when low, the group of eight smii ethernet interfaces, and when high, selects the single gmii interface. the gmii interface is described in the section below, and also how the leads are shared with the smii interface leads. each smii interface is comprised of a 125 mhz serial data transmit output (smii_don) and serial data receive input (smii_din); where n = 1-8. the smii data interface is a serial streaming of the standard 100 mbit/s (fast ethernet) mii interface (media independent interface). aspe d9 i/o lvttl-5/ lv c m o s 8 ma add bus spe indicator: when add bus timing is selected and ctbadd =0, this signal is an input and must be provided for add bus timing. when add bus timing is selected and ctbadd =1, this signal is output by the device for add bus timing. this signal is active high during each byte of the sts-3/stm-1/sts-1 payload, and low during transport overhead times. when drop bus timing is selected, an option (abte is low) is provided for outputting this signal, otherwise this lead is disabled. apar d8 o(t) lvcmos 8ma add bus parity bit: an odd or even parity output signal which is calculated over the byte wide add data. this 3-state lead is only active when there is data being added to the add bus. a control bit is provided that allows even parity to be calculated. add c5 o lvcmos 8 ma add bus add data present indicator: this active low signal is present when output data to the add bus is valid. it identifies the location of all of the vt/tu/vc time slots being added to the add bus. when in vc-4/sts-3c mode, when the highz_au3 bits are set to ? 0 ? for all 3 timeslots, the entire vc-4/sts-3c spe will be indicated as active. additionally in the add bus master mode, the h1, h2, h3 pointer bytes that are output will be indicated as active. symbol lead no. i/o/p type name/function gtx_clk y13 o lvcmos 12 ma gigabit ethernet transmit clock output: the gtx_clk is used to drive the txd(7-0), tx_en, and tx_er signals; runs at 125 mhz. tx_clk u11 i lvttl-5 transmit clock: this is a 125 mhz input clock, required only in gmii mode, and only in these two cases: 1) when control lead phy/mac is low. 2) when the mac loopback (see page 193 ) is selected. to comply with 802.3ab, the frequency tolerance must be +/- 0.01%. symbol lead no. i/o/p type name/function - 36 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tx_en /(smii_ gsync) w13 i/o lvttl-5/ lv c m o s 12 ma gmii transmit enable/global smii sync: when gmii/smiin control lead is high, this lead is used to output a control signal to indicate valid data is being presented on the gmii txd(7-0) leads. when gmii/smiin control lead is low and sync_dir control lead is high, this lead is used to output a global sync signal (i.e., common for all eight smii interfaces). when gmii/smiin control lead is low and sync_dir control lead is low, this lead is used to input a global sync signal (i.e., common for all eight smii interfaces). tx_er v12 o lvcmos 8 ma transmit error: this output signal is asserted to indicate to the phy that a coding violation was received in the input data stream. txd(7-0) /(smii_ do(8-1) u12, y14, v13, u13, w15, y16, v14, u14 olvcmos 12 ma transmit data out: data output is transmitted as a group of eight data signals, by the rs to the phy. when gmii/smii control lead is low, these leads operate as the eight smii interface data out signals - smii_don (n = 1 - 8) and correspond to the mac # (i.e., txd7 corresponds to smiido8). rxd(7-0) /(smii_ di(8-1) y11, y8, u10, v10, v9, w9, w8, u9 i lvttl-5 receive data in: data received by the phy is passed as a group of eight data signals to the dte. when gmii/smii control lead is low, these leads operate as the eight smii interface data in signals - smii_din (n = 1 - 8) and correspond to the mac # (i.e., rxd7 corresponds to smiidi8). rx_dv w11 i lvttl-5 receive data valid: this signal is asserted by the phy to indicate to the dte that valid data (octets) are being presented on the rxd(7-0) inputs. rx_er y12 i lvttl-5 receive data error: this signal is asserted to indicate to the dte a frame received in error. rx_clk /(smii_ gclk) v11 i lvttl receive clock: the clock is recovered by the phy from the incoming data stream, and passed onto the dte. rx_clk runs at either 2.5 mhz for 10 mbit/s ethernet or 25 mhz for 100 mbit/s operation. when gmii/smii control lead is low, operates as the 125 mhz smii_gclk. note: the duty cycle should be 40% to 60%. to comply with 802.3ab, the frequency tolerance must be +/- 0.01%. mdio y7 i/o lvttl-5/ lv c m o s 8 ma management data i/o: data input/output for the ieee 802.3u compliant management and status interface. mdc v8 o lvcmos 8 ma management data interface clock: the management data i/o (mdio) is clocked into and out of the ethermap-3 on the rising edge of this clock. the frequency for this clock is derived from the microprocessor clock input (micclk) divided by a factor of 4 to 28 (max = 12.5 mhz, see mgmt clock select table 24, on page 215 ). symbol lead no. i/o/p type name/function - 37 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers sdram interface the following table shows a standard 32 bit wide data, sdram interface. there are thirteen address bits, that include bank selection as needed; input mask bits (byte-wise); write enable, ras/cas, clock and clock enable. symbol lead no. i/o/p type name/function data(31-0) n18, r20, p18, t20, r18, u20, t18, v20, t17, u19, r17, t19, p17, r19, n17, p19, e17, d19, f17, e19, g17, f19, h17, g19, h18, f20, g18, e20, f18, d20, e18, c20 i/o(t) lvttl/ lv 3 c m o s 16 ma sdram controller external data i/o: 32 bits wide data bus; byte wise tristateable. bit 0 is the least significant bit. addr(12-0) k18, k19, n20, j20, k20, l19, l18, l17, m18, m17, p20, n19, m19 olv3cmos 16 ma address bus: 13 bits wide. bit 0 is the least significant bit. ba(1-0) m20, l20 o lv3cmos 16 ma bank select: these signals are used to select the banks in a standard sdram. - 38 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ras j19 o lv3cmos 16 ma row address strobe: for control of external sdram. this signal along with cas and we define the command being given to the external sdram. cas h19 o lv3cmos 16 ma column address strobe: for control of external sdram. his signal along with we and ras define the command being given to the external sdram. refer to the table in the ras lead description. we j17 o lv3cmos 8 ma write enable: for control of external sdram. this signal along with cas and ras define the command being given to the external sdram. refer to the table in the ras lead description. cs h20 o lv3cmos 16 ma chip select: for control of external sdram. used to select and deselect external sdram. mask g20 o lv3cmos 8 ma mask bits: this control output is used to mask out the standard 32 bit wide sdram memory interface. it is used to tristate the sdram data bus during a read cycle and to mask the sdram data bus during a write cycle. symbol lead no. i/o/p type name/function ras cas we function 111 nop: no operation 01 1 active: used to activate a row in a particular bank. the ba(1-0) selects the bank, and addr(12-0) selects the row. 101 read: used to initialize the sdram for a burst read. 100 write: used to initialize the sdram for a burst write. 010 precharge: deactivate open row in a bank or banks. 001 auto refresh: this command is performed every 2480 sysclk period, to ensure that all of the sdram rows are refreshed. this default setting can be changed by sdrarp at register address 0x1d604. 000 load mode register: this command is issued at the end of the configuration step, to configure the internal mode register of the sdram. it is the last command before the sdram to be ready for read/write accesses. - 39 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers receive vc-3 path overhead (vc-3poh) byte interface transmit vc-3 path overhead (vc-3poh) byte interface clk j18 o lv3cmos 16 ma interface clock: for control of external sdram. all sdram interface signals are sampled/output on the rising edge of this clock, which runs at 100 mhz. clke k17 o lv3cmos 16 ma interface clock enable: tied high internally. can be used to drive the clock enable pin of an external sdram. symbol lead no. i/o/p type name/function rpclk c13 o lvcmos 12 ma receive vc-3poh interface clock: the receive vc-3poh address (rpadd), address latch enable (rpale), data (rpdat), and data latch enable (rpdle) signals are clocked out on falling edges of this clock (2.43 mhz). rpale a14 o lvcmos 4 ma receive vc-3poh interface address latch enable: a positive 8 (rpclk) clock cycle-wide pulse that indicates a valid address (eight consecutive bits) present on rpadd. rpadd d12 o lvcmos 4 ma receive vc-3poh interface address: the states present on this lead during address latch enable time indicate the output vc-3poh byte and the sdh/sonet format. eight consecutive bits make up a valid address. rpdle b13 o lvcmos 4 ma receive vc-3poh interface data latch enable: a positive 8 (rpclk) clock cycle-wide pulse that indicates valid data present on rpdat. rpdat c12 o lvcmos 4 ma receive vc-3poh interface data: the states present on this lead over eight consecutive bits, during data latch enable time constitute the output byte data selected by the address. symbol lead no. i/o/p type name/function tpclk d3 o lvcmos 12 ma transmit vc-3poh interface clock: the transmit poh address (tpadd), address latch enable (tpale), and data latch enable (rpdle) signals are clocked out on falling edge of tpclk (2.43 mhz). data (tpdat), is clocked in on the rising edge of this clock. tpale e4 o lvcmos 4 ma transmit vc-3poh interface address latch enable: a positive 8 (tpclk) clock cycle-wide pulse that indicates a valid address (eight consecutive bits) present on tpadd. tpadd c1 o lvcmos 4 ma transmit vc-3poh interface address: the states present on this lead during address latch enable time indicate the output poh byte and the sdh/sonet format. eight consecutive bits make up a valid address. tpdle d2 o lvcmos 4 ma transmit vc-3poh interface data latch enable: a positive 8 (tpclk) clock cycle-wide pulse that indicates valid data present on tpdat. symbol lead no. i/o/p type name/function - 40 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers receive lower order path overhead (lopoh) byte interface transmit lower order path overhead (lopoh) byte interface tpdat e3 i lvttl-5 transmit vc-3poh interface data: the states present on this lead over eight consecutive bits, during data latch enable time, constitute the input byte data selected by the address. symbol lead no. i/o/p type name/function rpclk1 d15 o lvcmos 12 ma receive lopoh interface clock: the receive lopoh address (rpadd1), address latch enable (rpale1), data (rpdat1), and data latch enable (rpdle1) signals are clocked out on falling edges of this clock (19.44 mhz). rpale1 a17 o lvcmos 4 ma receive lopoh interface address latch enable: a positive 12 (rpclk1) clock cycle-wide pulse that indicates a valid address (twelve consecutive bits) present on rpadd1. rpadd1 b16 o lvcmos 4 ma receive lopoh interface address: the states present on this lead during address latch enable time indicate the output lopoh byte and the sdh/sonet format. twelve consecutive bits make up a valid address. rpdle1 c15 o lvcmos 4 ma receive lopoh interface data latch enable: a positive 8 (rpclk1) clock cycle-wide pulse that indicates valid data present on rpdat1. rpdat1 d14 o lvcmos 4 ma receive lopoh interface data: the states present on this lead over eight consecutive bits, during data latch enable time constitute the output byte data selected by the address. symbol lead no. i/o/p type name/function tpclk1 f3 o lvcmos 12 ma transmit lopoh interface clock: the transmit lopoh address (tpadd1), address latch enable (tpale1), and data latch enable (rpdle1) signals are clocked out on falling edge of tpclk1 (19.44 mhz). data (tpdat1), is clocked in on the rising edge of this clock. tpale1 g4 o lvcmos 4 ma transmit lopoh interface address latch enable: a positive 12 (tpclk1) clock cycle-wide pulse that indicates a valid address (twelve consecutive bits) present on tpadd1. tpadd1 e1 o lvcmos 4 ma transmit lopoh interface address: the states present on this lead during address latch enable time indicate the output lopoh byte and the sdh/sonet format. twelve consecutive bits make up a valid address. tpdle1 f2 o lvcmos 4 ma transmit lopoh interface data latch enable: a positive 8 (tpclk1) clock cycle-wide pulse that indicates valid data present on tpdat1. tpdat1 g3 i lvttl-5 transmit lopoh interface data: the states present on this lead over eight consecutive bits, during data latch enable time, constitute the input byte data selected by the address. symbol lead no. i/o/p type name/function - 41 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers receive (vc-3) high order alarm indication port transmit (vc-3) high order alarm indication port receive low order alarm indication port transmit low order alarm indication port symbol lead no. i/o/p type name/function raipf a16 o lvcmos 4 ma receive ho alarm indication port frame pulse: a active high one (raipc) clock cycle-wide frame pulse that identifies bit 1 in the data stream. raipc a15 o lvcmos 12 ma receive ho alarm indication port clock: a 19.44 mhz output clock used for clocking the frame pulse (raipf) and the serial data (raipd) into the mate device. raipd b14 o lvcmos 4 ma receive ho alarm indication port data: a serial frame that contains the rei count and rdi alarm states for the high order spe/vcs. symbol lead no. i/o/p type name/function taipf f4 i lvttl-5 transmit ho alarm indication port frame pulse: a active high one (taipc) clock cycle-wide frame pulse that identifies bit 1 in the data stream. connected to raipf on mate device. taipc d1 i lvttl-5 transmit ho alarm indication port clock: a 19.44 mhz output clock used for clocking in the frame pulse (taipf1) and the serial data (taipd1). connected to raipc on mate device. taipd e2 i lvttl-5 transmit ho alarm indication port data: a serial frame that contains the rei count, rdi alarm states, and the tandem connection monitoring and alarm states for the individual tu-3 vc-3 paths. connected to raipd on mate device. symbol lead no. i/o/p type name/function raipf1 a18 o lvcmos 4 ma receive lo alarm indication port frame pulse: a active high one (raipc) clock cycle-wide frame pulse that identifies bit 1 in the data stream. raipc1 b17 o lvcmos 12 ma receive lo alarm indication port clock: a 19.44 mhz output clock used for clocking the frame pulse (raipf1) and the serial data (raipd1) into the mate device. raipd1 c16 o lvcmos 4 ma receive lo alarm indication port data: a serial frame that contains the rei count and rdi alarm states for the vt/tus. symbol lead no. i/o/p type name/function taipf1 h4 i lvttl-5 transmit lo alarm indication port frame pulse: a active high one (taipc) clock cycle-wide frame pulse that identifies bit 1 in the data stream. connected to raipf1 on mate device. - 42 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers controls taipc1 f1 i lvttl-5 transmit lo alarm indication port clock: a 19.44 mhz output clock used for clocking in the frame pulse (taipf1) and the serial data (taipd1). connected to raipc1 on mate device. taipd1 g2 i lvttl-5 transmit lo alarm indication port data: a serial frame that contains the rei count, rdi alarm states, and the tandem connection monitoring and alarm states for the individual lo vt/tu paths. connected to raipd1 on mate device. symbol lead no. i/o/p type name/function gmii/smii w16 i lvttl-5p gmii/smii interface select: a low selects 8x smii ethernet interfaces in place of a single gmii. this lead has an internal pull-up resistor. highz y17 i lvttl-5p high impedance select: a low forces all output leads, except for the boundary scan data output tdo, to the high impedance state for testing purposes. this lead has an internal pull-up resistor. reset v16 i lvttl-5p reset: an active low signal used for resetting the internal cores and performance counters within the ethermap-3 plus to preset values. the reset must be applied only after power is applied and stable, and the clocks are also stable. the reset must be present for a minimum of 250 ns. this lead has an internal pull-up resistor. after de-assertion of this lead, a 2 microsecond wait period must be observed, where no microprocessor access can be made. abte w17 i lvttl-5p add bus timing signals enabled: an active low signal enables the aclk, aspe, ac1j1v1 to be outputs when drop bus timing is selected. this lead has an internal pull up resistor. a high on this lead causes those signals to be tristated. abust y18 i lvttl-5p add bus timing selection: a low selects the add bus timing mode. when add bus timing is selected, aclk, aspe, and ac1j1v1, can be programmed to be inputs and used to source the ad(7-0), apar, and add signal, or they can be generated internally and be provided as output signals. a high selects drop bus timing. the signals for the add direction are derived from the drop bus. this lead has an internal pull up resistor. phy/mac u16 i lvttl-5p phy/mac interface select: in smii mode, a low selects the mac-to-mac interconnection type for the ethernet side, while a high selects the mac-to-phy interconnection. in gmii mode, a high, selects rx_clk as the source for gtx_clk and a low, selects tx_clk as the source for gtx_clk. note: in gmii mode, if the mac loopback is enabled, tx_clk is always required as the source of gtx_clk, independent of phy/mac state. this lead has an internal pull-up resistor. in smii mode, whatever the value of this input, rx_clk is used as reference clock. symbol lead no. i/o/p type name/function - 43 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers clock interfaces host processor interface sync_dir w12 i lvttl-5p global sync direction select: in smii mode and when low, the smii_gsync signal is an input. in smii mode and when high, the smii_gsync signal is an output. in gmii mode, this lead must be kept high. this lead has an internal pull-up resistor. symbol lead no. i/o/p type name/function rtclk a3 i lvttl-5d reference mapper/demapper clock: this clock is a 19.44 mhz clock, (40% - 60% max. duty cycle) used by the mapper/demapper blocks. the rtclk signal is required for all operating modes, but in add bus master mode (ctbadd = 1, lead abust = low) this input should be +/- 20 ppm maximum, since in that mode it is the source of aclk. this clock does not have to have any relationship to aclk. sysclk w7 i lvttl-5 system reference clock: a 50 mhz input clock, with max. 40% - 60% duty cycle and minimum accuracy of +/- 100 ppm. this clock is internally doubled via a pll to 100 mhz and is used as the system clock for all other functions except the mapper/demapper block. onesec b4 i lvttl-5d one second performance measurement clock: this clock input is used for the one second shadow counters, and pm/fm alarm registers. this input can be either below: a) 1.0 hz (+/- 32 ppm) clock, b) 1.0 hz pulse, with a minimum 51.44 ns high time. symbol lead no. i/o/p type name/function micclk h3 i lvttl-5 microprocessor clock: this clock should come from the microprocessor being interfaced to this device. for intel and motorola 68360 modes, it is recommended that this lead be connected to the microprocessor bus clock. in motorola mpc860 mode, this clock must be synchronous to the microprocessor bus clock. a(15-0) v1, u1, r4, u2, t3, p2, n2, r1, r3, t2, p4, n4, m4, m3, t1, p3 i lvttl-5 address bus: these leads are active high address line inputs that are used by the host processor for accessing the ethermap-3 plus for a read/write cycle. a15 is the most significant bit in the location ? s address. a0 of the device will correspond to a1 of the microprocessor address bus. symbol lead no. i/o/p type name/function - 44 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers d(15-0) l2, h1, g1, j4, k4, k3, m1, h2, l1, l3, j1, j3, k2, j2, n1, k1 i/o(t) lvttl-5/ lv c m o s 8 ma data bus: bidirectional data lines used for transferring data between the ethermap-3 plus and the host processor. d15 is the most significant bit. sel n3 i lvttl-5p select: a low enables data transfers between the host processor and the ethermap-3 plus a read/write cycle. this lead has an internal pull-up resistor. wr / ds /ts m2 i lvttl-5 write enable (intel mode)/data strobe (motorola mode)/transfer start (motorola mode): an active low signal. intel mode: asserted low to initiate a write cycle. motorola 68360 mode: this is the data strobe signal which indicates that the host processor is ready to accept data during a read cycle or has put valid data on the bus during a write cycle. motorola mpc860 mode: indicates the start of a new bus cycle when it becomes asserted. rd / (rd/wr ) r2 i lvttl-5 read (intel mode) or read/write (both motorola modes): an active low signal that is asserted low to initiate a read cycle in the intel mode. in either of the motorola modes, high on this lead is initiates a read, and low initiates a write. ready/ dtack /ta p1 od lvcmos 24 ma ready (intel mode)/data transfer acknowledge (motorola mode)/transfer acknowledge (motorola mode): intel mode: a high indicates that a transfer to/from the memory can be accomplished. the high (active) state is kept for two micclk cycles. motorola 68360 mode: this lead is an active low, and indicates either that the data on the bus is valid during a read operation, or, indicates data acceptance during a write operation. the low (active) state is kept for two micclk cycles. motorola mpc860 mode: this lead is an active low, and indicates either that the data on the bus is valid during a read operation, or, indicates data acceptance during a write operation. the low (active) state is synchronous to micclk and is one micclk cycle wide. note: this output is an open-drain buffer which requires an external pull-up resistor. int/irq l4 o lvcmos 8 ma interrupt: intel mode: a high on this output lead signals an interrupt request to the host processor. both motorola modes: a low on this output lead signals an interrupt request to the host processor. symbol lead no. i/o/p type name/function - 45 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers boundary scan (ieee standard 1149.1) moto(1-0) u3, t4 i lvttl-5 intel/motorola: selector lead for selecting the intel/motorola interface: symbol lead no. i/o/p type name/function tck v6 i lvttl-5 test boundary scan clock: this signal is used to shift data into tdi on its rising edge and out of tdo on its falling edge. the maximum clock frequency is 10 mhz. tdi u7 i lvttl-5p test boundary scan data input: serial test instructions and data are clocked into this lead on the rising edge of tck. this lead has an internal pull-up resistor. tdo y5 o lvcmos 8 ma test boundary scan data output: serial data test instructions and data are clocked out of this lead on the falling edge of tck. when inactive, this lead goes to a high impedance state. tms w6 i lvttl-5p test boundary scan mode select: this input lead is sampled on the rising edge of tck. it is used to place the test access port controller into various states, as defined in ieee 1149.1. an internal pull-up holds this lead high during normal operation. this lead has an internal pull-up resistor. trs y6 i lvttl-5p test boundary scan reset: an active low signal that asynchronously resets the test access port controller. the reset must be present for a minimum of 50 ns. specific control of this lead is required in order to ensure normal operation of the device. this lead should be held low whenever boundary scan operations are not being performed. this lead has an internal pull-up resistor. symbol lead no. i/o/p type name/function moto1 moto0 interface 0 0 intel processor interface. 0 1 motorola 68360 processor interface. 1 0 motorola mpc860 processor interface. 11do not use. - 46 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers test symbol lead no. i/o/p type name/function scan_en v15 i lvttl-5d scan enable: this lead is used for transwitch testing purposes only. this lead has an internal pull-down to vss and should be held low. mbist_mode u5 i lvttl-5d memory bist: this lead is used for transwitch testing purposes only. this lead has an internal pull-down to vss and should be held low. pll_bypass v5 i lvttl-5d pll bypass: this lead is used for transwitch testing purposes only. this lead has an internal pull-down to vss and should be held low. pllout y4 o lvcmos 4 ma pll output: this lead is used for transwitch testing purposes only. this lead should be left open (floating). scan_mode u15 i lvttl-5d scan mode: this lead is used for transwitch testing purposes only. this lead has an internal pull-down to vss and should be held low. - 47 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers absolute maximum ratings and environmental limitations ( referenced to vss ) notes: 1. conditions exceeding the min or max values may cause permanent failure. exposure to conditions near the min or max values for extended periods may impair device reliability. 2. pre-assembly storage in non-drypack conditions is not recommended. please refer to the instructions on the ? caution ? label on the drypack bag in which devices are supplied. 3. test method for esd per jedec jesd22-a114-b. 4. device core is 1.8 v only. all input signals leads accept 5v signals except for smii/gmii and sdram memory interface signals which accept only 3.3v signals. thermal characteristics parameter symbol min max unit conditions i/o supply voltage (3.3v) v dd33 -0.3 3.9 v note 1, 4 core supply voltage (1.8v) v dd18 -0.3 2.1 v note 1, 4 dc input voltage lvttl input voltage lvttl-5 input voltage v in 0 -0.5 3.3 5.5 v note 1, 4 storage temperature range t s -55 +150 o c note 1 ambient operating temperature t a -40 +85 o c 0 ft/min linear airflow moisture exposure level me 5 level per ipc/jedec j-std-020b relative humidity, during assembly rh 30 60 % note 2 relative humidity, in-circuit rh 0 100 % non-condensing esd classification esd 2 kv note 3 parameter min typ max unit test conditions thermal resistance: junction to ambient 14.7 o c/w test performed with package assem- bled on jedec standard multilayer test board with 0 ft/min linear airflow. - 48 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers power requirements gmii mode (traffic running on one single port) smii mode (traffic running on one single port) smii mode (traffic running on all eight ports) notes: 1. for i dd33 and i dd18 , the figure reported represents the absolute minimum and maximum across all the following variations: 1.7 < v dd18 < 1.9 and 3.15 < v dd33 < 3.45 and -40 o c < t (temperature) < 85 o c. 2. for the total power, the maximum consumption occurs when both v dd33 and v dd18 are at their maximum test value. the minimum consumption occurs when both v dd33 and v dd18 are at their minimum test value. very small effect of temperature on the power consumption has been observed. 3. the figure for typical power was measured at v dd33 = 3.3 v and v dd18 = 1.8 v. 4. the max and min values of power have been rounded to the nearest higher 0.01 w. 5. p ddtotal5 represent the p ddtotal value reported on the above, line plus 5% to cover the process and temperature variations that may exist. 6. measurement taken with traffic injected at 1 gbps, with flow control enabled. packet size was 64 bytes. 7. measurement taken with traffic injected at 100 mbps, with flow control enabled. packet size was 1514 bytes. parameter min typ max unit test conditions v dd33 3.15 3.30 3.45 v i dd33 84.8 90.9 98.7 ma note 1 v dd18 1.71 1.80 1.89 v i dd18 840 900 980 ma note 1 power dissipation, p ddtotal 1700 1920 2203 mw note 2, 3, 4, 6 power dissipation, p ddtotal5 1785 2016 2313 mw note 4, 5 parameter min typ max unit test conditions v dd33 3.15 3.30 3.45 v i dd33 60.0 63.5 90 ma note 1 v dd18 1.71 1.80 1.89 v i dd18 700 740 860 ma note 1 power dissipation, p ddtotal 1379 1547 1945 mw note 2, 3, 4, 7 power dissipation, p ddtotal5 1448 1619 2043 mw note 4, 5 parameter min typ max unit test conditions v dd33 3.15 3.30 3.45 v i dd33 84.6 90.7 112 ma note 1 v dd18 1.71 1.80 1.89 v i dd18 760 810 870 ma note 1 power dissipation, p ddtotal 1559 1758 2020 mw note 2, 3, 4, 7 power dissipation, p ddtotal5 1637 1846 2122 mw note 4, 5 - 49 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers input, output and input/output parameters input parameters for lvttl-5 (5 volt tolerant) input parameters for lvttl-5p (5 volt tolerant, with pull-up resistor) input parameters for lvttl-5d (5 volt tolerant, with pull-down resistor) input parameters for lvttl (3.3 volt tolerant) parameter min typ max unit test conditions v ih 2.0 5.0 v 3.15 < v dd33 < 3.45 v il 0.8 v 3.15 < v dd33 < 3.45 input leakage current 15 a av dd33 = 3.45, vin = v dd or gnd input capacitance 5 pf parameter min typ max unit test conditions v ih 2.0 5.0 v 3.15 < v dd33 < 3.45 v il 0.8 v 3.15 < v dd33 < 3.45 input leakage current 28 105 av dd33 =3.45; input = 0 volts input capacitance 5 pf parameter min typ max unit test conditions v ih 2.0 5.0 v 3.15 < v dd33 < 3.45 v il 0.8 v 3.15 < v dd33 < 3.45 input leakage current 28 105 av dd33 = 3.45; input = 3.45 volts input capacitance 5 pf parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd33 < 3.45 v il 0.8 v 3.15 < v dd33 < 3.45 input leakage current 15 av dd33 = 3.45, vin = v dd or gnd input capacitance 5 pf - 50 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers output parameters for lvcmos 24ma (open drain) note: open drain requires use of a 4.7 k ? external pull-up resistor to v dd33 . output parameters for lvcmos 12ma output parameters for lvcmos 8ma parameter min typ max unit test conditions output capacitance 30 pf v oh 2.4 v v dd33 = 3.15; i oh = -24 v ol 0.4 v v dd33 = 3.15; i ol = 24 i ol 24 ma i oh -24 ma t rise 1.17 2.25 ns c load = 30 pf t fall 0.87 1.77 ns c load = 30 pf leakage tristate 15 a 0 to 3 v input parameter min typ max unit test conditions output capacitance 30 pf v oh 2.4 v v dd33 = 3.15; i oh = -12 v ol 0.4 v v dd33 = 3.15; i ol = 12 i ol 12 ma i oh -12 ma t rise 1.43 2.71 ns c load = 30 pf t fall 1.22 2.45 ns c load = 30 pf leakage tristate 15 a 0 to 3 v input parameter min typ max unit test conditions output capacitance 30 pf v oh 2.4 v v dd33 = 3.15; i oh = -8 v ol 0.4 v v dd33 = 3.15; i ol = 8 i ol 8ma i oh -8 ma t rise 1.78 3.38 ns c load = 30 pf t fall 1.65 3.22 ns c load = 30 pf leakage tristate 15 a 0 to 3 v input - 51 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers output parameters for lvcmos 4ma output parameters for lv3cmos 16ma (do not use pull-ups to more than 3.3v with these outputs) output parameters for lv3cmos 8ma (do not use pull-ups to more than 3.3v with these outputs) parameter min typ max unit test conditions output capacitance 30 pf v oh 2.4 v v dd33 = 3.15; i oh = -4 v ol 0.4 v v dd33 = 3.15; i ol = 4 i ol 4ma i oh -4 ma t rise 2.97 5.54 ns c load = 30 pf t fall 2.95 5.66 ns c load = 30 pf leakage tristate 15 a 0 to 3 v input parameter min typ max unit test conditions output capacitance 30 pf v oh 2.4 v v dd33 = 3.15; i oh = -16 v ol 0.4 v v dd33 = 3.15; i ol = 16 i ol 16 ma i oh -16 ma t rise 1.28 2.87 ns c load = 30 pf t fall 1.04 2.65 ns c load = 30 pf leakage tristate 15 a 0 to 3 v input parameter min typ max unit test conditions output capacitance 30 pf v oh 2.4 v v dd33 = 3.15; i oh = -8 v ol 0.4 v v dd33 = 3.15; i ol = 8 i ol 8ma i oh -8 ma t rise 1.78 3.41 ns c load = 30 pf t fall 1.65 3.38 ns c load = 30 pf leakage tristate 15 a 0 to 3 v input - 52 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers input/output parameters for lvttl-5 input and lvcmos output 12ma (5 volt tolerant input) input/output parameters for lvttl-5 input and lvcmos output 8ma (5 volt tolerant input) parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd33 < 3.45 v il 0.8 v 3.15 < v dd33 < 3.45 input leakage current 15 a 0 to 3.3 v input input capacitance 5 pf v oh 2.4 v v dd33 = 3.15; i oh = -12 v ol 0.4 v v dd33 = 3.15; i ol = 12 i ol 12 ma i oh -12 ma t rise 1.44 2.72 ns c load = 30 pf t fall 1.23 2.45 ns c load = 30 pf parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd33 < 3.45 v il 0.8 v 3.15 < v dd33 < 3.45 input leakage current 15 a 0 to 3.3 v input input capacitance 5 pf v oh 2.4 v v dd33 = 3.15; i oh = -8 v ol 0.4 v v dd33 = 3.15; i ol = 8 i ol 8ma i oh -8 ma t rise 1.79 3.40 ns c load = 30 pf t fall 1.67 3.24 ns c load = 30 pf - 53 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers input/output parameters for lvttl input and lv3cmos output 16ma (3.3v volt tolerant input) input/output parameters for lvttl input and lv3cmos output 8ma (3.3v volt tolerant input) parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd33 < 3.45 v il 0.8 v 3.15 < v dd33 < 3.45 input leakage current 15 a 0 to 3.3 v input input capacitance 5 pf v oh 2.4 v v dd33 = 3.15; i oh = -16 v ol 0.4 v v dd33 = 3.15; i ol = 16 i ol 16 ma i oh -16 ma t rise 1.76 2.85 ns c load = 25 pf t fall 1.60 2.64 ns c load = 25 pf parameter min typ max unit test conditions v ih 2.0 v 3.15 < v dd33 < 3.45 v il 0.8 v 3.15 < v dd33 < 3.45 input leakage current 15 a 0 to 3.3 v input input capacitance 5 pf v oh 2.4 v v dd33 = 3.15; i oh = -8 v ol 0.4 v v dd33 = 3.15; i ol = 8 i ol 8ma i oh -8 ma t rise 1.80 3.39 ns c load = 25 pf t fall 1.78 3.36 ns c load = 25 pf - 54 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers timing characteristics this section presents the detailed timing characteristics for the ethermap-3 plus in figures 8 through 38 with values of the timing parameters tabulated below each waveform diagram. all outputs are measured with a max- imum load capacitance of 50 pf unless otherwise stated. timing parameters are measured at the voltage lev- els of (v oh +v ol )/2 for output signals and (v ih + v il )/2 for input signals. figure 8. drop bus timing (only ad, apar, and add are output) 50 pf load notes: 1. stm-1 mode with tug-3 mapping is shown (tug-3 #a selected). 2. if sts-3 mode was used there would be three j1 pulses that would be asynchronous with respect to each other. however the timing (i.e., setup and hold, and propagation delays) would not change. 3. transmit timingdelay = 1 (see register 0x184c8 ). see parameter table on next page. j0 j1 z0 z0 j1 fixed h1(2) h1(1) dclk (input) dd(7-0) dpar dspe (input) dc1j1v1 (input) data ad(7-0)/ (outputs) add (output) data data data fixed stuff stuff j0 vc-4 j1 byte tug-3 tug-3 (inputs) apar t cyc t pwh t su(1) t su(2) t h(1) t h(2) t h(3) t su(3) t d(1) t d(2) t d(3) t d(4) t d(5) - 55 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers note: 1. the inputs dd(7-0)/dpar, dc1j1v1 and dspe are sampled on the falling edge of dclk according to the setting of configuration bit active edge (see table 281, on page 347 ). parameter symbol min typ max unit dclk clock period t cyc 51.44 ns dclk duty cycle t pwh /t cyc 45 55 % dd(7-0)/dpar setup time to dclk t su(1) 5ns dd(7-0)/dpar hold time after dclk t h(1) 0ns dspe setup time to dclk t su(2) 6ns dspe hold time after dclk t h(2) 0ns dc1j1v1 setup time to dclk t su(3) 6ns dc1j1v1 hold time after dclk t h(3) 0ns ad(7-0)/apar stable from dclk t d(1) 730ns ad(7-0)/apar tristated from dclk t d(2) 820ns ad(7-0)/apar turn on from dclk t d(3) 2.5 20 ns ad(7-0)/apar valid from dclk t d(4) 530ns add delay after dclk t d(5) 530ns - 56 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 9. drop bus timing (only ad, apar, and add are output) 50 pf load notes: 1. stm-1 mode with tug-3 mapping is shown (tug-3 #a selected). 2. if sts-3 mode was used there would be three j1 pulses that would be asynchronous with respect to each other. however the timing (i.e., setup and hold, and propagation delays) would not change. 3. transmit timingdelay = 1 (see register 0x184c8 ). see parameter table on next page. j0 j1 z0 z0 j1 fixed h1(2) h1(1) dclk (input) dd(7-0) dpar dspe (input) dc1j1v1 (input) data ad(7-0)/ (outputs) add (output) data data data fixed stuff stuff j0 tug-3 tug-3 (inputs) apar t cyc t pwh t su(1) t su(2) t h(1) t h(2) t h(3) t su(3) t d(1) t d(2) t d(3) t d(4) t d(5) vc-4 j1 byte - 57 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers note: 1. the inputs dd(7-0)/dpar, dc1j1v1 and dspe are sampled on the rising edge of dclk according to the setting of configuration bit active edge (see table 281, on page 347 ). parameter symbol min typ max unit dclk clock period t cyc 51.44 ns dclk duty cycle t pwh /t cyc 45 55 % dd(7-0)/dpar setup time to dclk t su(1) 5ns dd(7-0)/dpar hold time after dclk t h(1) 2ns dspe setup time to dclk t su(2) 10 ns dspe hold time after dclk t h(2) 5ns dc1j1v1 setup time to dclk t su(3) 10 ns dc1j1v1 hold time after dclk t h(3) 5ns ad(7-0)/apar stable from dclk t d(1) 730ns ad(7-0)/apar tristated from dclk t d(2) 820ns ad(7-0)/apar turn on from dclk t d(3) 2.5 20 ns ad(7-0)/apar valid from dclk t d(4) 530ns add delay after dclk t d(5) 530ns - 58 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 10. drop bus timing (all add bus signals are outputs) 50 pf load notes: 1. a single vt/tu is shown for illustration purposes (last vt of sts-1 #3 selected). 2. sts-3 mode is shown. if stm-1 mode was used there would be one j1 pulse and three tug-3s, or three j1 pulses and three au-3s. however the timing (i.e., setup and hold, and propagation delays) would not change. 3. transmit timingdelay = 1 (see register 0x184c8 ). note: 1. the inputs dd(7-0)/dpar, dc1j1v1 and dspe are sampled on the falling edge of dclk according to the setting of configuration bit active edge (see table 281, on page 347 ). parameter symbol min typ max unit dclk clock period t cyc 51.44 ns dclk duty cycle t pwh /t cyc 40 50 60 % dd(7-0)/dpar setup time before dclk t su(1) 5ns dd(7-0)/dpar hold time after dclk t h(1) 0ns dspe setup time before dclk t su(2) 6ns dspe hold time after dclk t h(2) 0ns dc1j1v1 setup time before dclk t su(3) 6ns dc1j1v1 hold time after dclk t h(3) 0ns aclk delay from dclk t d(1) 210ns ac1j1v1 delay from aclk t d(2) 330ns aspe delay from aclk t d(3) 330ns ad(7-0)/apar turn on from aclk t d(4) 330ns add delay from aclk t d(5) 330ns ad(7-0)/apar out valid delay from aclk t d(6) 330ns t h(2) t pwh t su(1) t h(1) c1(1) add (output) ad(7-0) (output) dc1j1v1 (input) dspe (input) dclk (input) c1(2) c1(3) data vt/tu selected j1 byte sts-1 #1 sts-1 #2 sts-1 #3 data sts-1 #1 j1 sts-1 #2 j1 sts-1 #3 v1 sts-1 #1 j1 sts-1 #1 c1(1) occurs every four frames when provided in place of the h4 byte t su(3) t h(3) t cyc t su(2) t d(4) t d(2) t d(5) t d(3) dd(7-0) (input) dpar apar aclk (output) ac1j1v1 (output) c1(1) aspe (output) j1 sts-1 #1 j1 sts-1 #2 j1 sts-1 #3 t d(1) t d(6) vt selected v1 sts-1 #2 v1 sts-1 #3 v1 sts-1 #1 v1 sts-1 #2 v1 sts - 59 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 11. drop bus timing (all add bus signals are outputs) 50 pf load notes: 1. a single vt/tu is shown for illustration purposes (last vt/tu of sts-1/vc-3 #3 selected). 2. sts-3 mode is shown. if stm-1 mode was used there would be one j1 pulse and three tug-3s, or three j1 pulses and three au-3s. however the timing (i.e., setup and hold, and propagation delays) would not change. 3. transmit timingdelay = 1 (see register 0x184c8 ). note: 1. the inputs dd(7-0)/dpar, dc1j1v1 and dspe are sampled on the rising edge of dclk according to the setting of configuration bit active edge (see table 281, on page 347 ). parameter symbol min typ max unit dclk clock period t cyc 51.44 ns dclk duty cycle t pwh /t cyc 40 50 60 % dd(7-0)/dpar setup time before dclk t su(1) 5ns dd(7-0)/dpar hold time after dclk t h(1) 2ns dspe setup time before dclk t su(2) 10 ns dspe hold time after dclk t h(2) 5ns dc1j1v1 setup time before dclk t su(3) 10 ns dc1j1v1 hold time after dclk t h(3) 5ns aclk delay from dclk t d(1) 210ns ac1j1v1 delay from aclk t d(2) 330ns aspe delay from aclk t d(3) 330ns ad(7-0)/apar turn on from aclk t d(4) 330ns add delay from aclk t d(5) 330ns ad(7-0)/apar out valid delay from aclk t d(6) 330ns t h(2) t pwh t su(1) t h(1) c1(1) add (output) ad(7-0) (output) dc1j1v1 (input) dspe (input) dclk (input) c1(2) c1(3) data vt/tu selected j1 byte sts-1 #1 sts-1 #2 sts-1 #3 data sts-1 #1 j1 sts-1 #2 j1 sts-1 #3 v1 sts-1 #1 j1 sts-1 #1 c1(1) occurs every four frames when provided in place of the h4 byte t su(3) t h(3) t cyc t su(2) t d(4) t d(2) t d(5) t d(3) dd(7-0) (input) dpar apar aclk (output) ac1j1v1 (output) c1(1) aspe (output) j1 sts-1 #1 j1 sts-1 #2 j1 sts-1 #3 t d(1) t d(6) vt selected v1 sts-1 #2 v1 sts-1 #3 v1 sts-1 #1 v1 sts - 60 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 12. add bus timing (timing signals are inputs) 50 pf load notes: 1. a single tributary is shown for illustration purposes (sts-1 #1). 2. a delay of ? 1 ? clock cycle is shown (selected in register 0x184c8 ). 3. sts-3 mode is shown. if stm-1 mode was used there would be one j1 pulse and three tug-3s, or three j1 pulses and three au-3s. however the timing (i.e., setup and hold, and propagation delays) would not change. note: 1. the inputs ac1j1v1 and aspe are sampled on the falling edge of aclk according to the setting of configuration bit active edge (see table 281, on page 347 ). parameter symbol min typ max unit aclk clock period t cyc 51.44 ns aclk duty cycle, t pwh /t cyc 40 50 60 % ac1j1v1 setup time before aclk t su(1) 5ns ac1j1v1 hold time after aclk t h(1) 0ns aspe setup time before aclk t su(2) 5ns aspe hold time after aclk t h(2) 0ns ad(7-0)/apar out valid delay from aclk t d(2) 530ns ad(7-0)/apar to tristate delay from aclk t d(3) 530ns add add indicator delayed from aclk t d(1) 530ns ad(7-0)/apar out tristate to driven delay from aclk t d(4) 2.5 30 ns t h(2) t pwh add (output) ad(7-0) (output) ac1j1v1 (input) aspe (input) aclk (input) j1 sts-1 #2 j1 sts-1 #3 v1 sts-1 #1 j1 sts-1 #1 c1(1) occurs every four frames t su(1) t h(1) t cyc t su(2) t d(2) t d(3) t d(1) v1 sts-1 #2 v1 sts-1 #3 t d(4) apar j1 byte from sts-1 #1 - 61 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 13. add bus timing (timing signals are inputs) 50 pf load notes: 1. a single tributary is shown for illustration purposes (sts-1 #1). 2. a delay of ? 1 ? clock cycle is shown (selected in register 0x184c8 ). 3. sts-3 mode is shown. if stm-1 mode was used there would be one j1 pulse and three tug-3s, or three j1 pulses and three au-3s. however the timing (i.e., setup and hold, and propagation delays) would not change. note: 1. the inputs ac1j1v1 and aspe are sampled on the rising edge of aclk according to the setting of configuration bit active edge (see table 281, on page 347 ). parameter symbol min typ max unit aclk clock period t cyc 51.44 ns aclk duty cycle, t pwh /t cyc 40 50 60 % ac1j1v1 setup time before aclk t su(1) 15 ns ac1j1v1 hold time after aclk t h(1) 1ns aspe setup time before aclk t su(2) 15 ns aspe hold time after aclk t h(2) 1ns ad(7-0)/apar out valid delay from aclk t d(2) 530ns ad(7-0)/apar to tristate delay from aclk t d(3) 530ns add add indicator delayed from aclk t d(1) 530ns ad(7-0)/apar out tristate to driven delay from aclk t d(4) 2.5 30 ns t h(2) t pwh add (output) ad(7-0) (output) ac1j1v1 (input) aspe (input) aclk (input) j1 sts-1 #2 j1 sts-1 #3 v1 sts-1 #1 j1 sts-1 #1 c1(1) occurs every four frames t su(1) t h(1) t cyc t su(2) t d(2) t d(3) t d(1) v1 sts-1 #2 v1 sts-1 #3 t d(4) apar j1 byte from sts-1 #1 - 62 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 14. add bus timing (timing signals are outputs) 50 pf load notes: 1. a single tributary is shown for illustration purposes (sts-1 #1). 2. a delay of ? 0 ? clock cycle is shown (selected in register 0x184c8 ). 3. sts-3 mode is shown. if stm-1 mode was used there would be one j1 pulse and three tug-3s, or three j1 pulses and three au-3s. however the timing (i.e., setup and hold, and propagation delays) would not change. note: 1. aclk is derived from rtclk input (lead a3) and should be a sonet/sdh clock of +/- 20 ppm or better. parameter symbol min typ max unit aclk clock period t cyc 51.44 ns aclk duty cycle, t pwh /t cyc 40 50 60 % ac1j1v1out valid delay from aclk t d(5) 430ns aspe out valid delay from aclk t d(6) 430ns ad(7-0)/apar out valid delay from aclk t d(2) 430ns ad(7-0)/apar to tristate delay from aclk t d(3) 3.5 30 ns add add indicator delayed from aclk t d(1) 530ns ad(7-0)/apar out tristate to driven delay from aclk t d(4) 320ns t d(5) t pwh add (output) ad(7-0) (output) ac1j1v1 (output) aspe (output) aclk (output) j1 sts-1 #2 j1 sts-1 #3 v1 sts-1 #1 j1 sts-1 #1 c1(1) occurs every four frames t cyc t d(2) t d(3) t d(1) v1 sts-1 #2 v1 sts-1 #3 t d(4) apar t d(6) j1 byte corresponding tosts-1 #1 - 63 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 15. tx gmii ethernet interface 5 pf load parameter symbol min typ max unit gtx_clk clock period t cyc 8ns gtx_clk duty cycle, t pwh /t cyc 40 60 % tx_en out valid delay from gtx_clk t d(1) 1.4 4.5 ns txd(7-0) out valid delay from gtx_clk t d(2) 1.4 4.5 ns tx_er out valid delay from gtx_clk t d(3) 1.4 4.5 ns (output) txd(7-0) (output) tx_en (output) gtx_clk (output) t cyc tx_er t pwh t d(1) t d(3) t d(2) - 64 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 16. rx gmii ethernet interface 10 pf load parameter symbol min typ max unit rx_clk clock period t cyc 8ns rx_clk duty cycle, t pwh /t cyc 45 55 % rx_dv setup time before rx_clk t s(1) 2ns rx_dv hold time after rx_clk t h(1) 0ns rxd(7-0) setup time before rx_clk t s(2) 2ns rxd(7-0) hold time after rx_clk t h(2) 0ns rx_er setup time before rx_clk t s(3) 2ns rx_er hold time after rx_clk t h(3) 0ns (input) rxd(7-0) (input) rx_dv (input) rx_clk (input) t cyc rx_er t pwh t h(1) t s(2) t s(1) t h(2) t s(3) t h(3) - 65 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 17. tx/rx smii ethernet interface (sync as an output) 10 pf load parameter symbol min typ max unit smii_gclk clock period t cyc 8ns smii_gclk duty cycle, t pwh /t cyc 40 60 % smii_gsync out valid delay from smii_gclk t d(1) 1.5 4.5 ns smii_don out valid delay from smii_gclk t d(2) 1.5 4.5 ns smii_din setup time before smii_gclk t s 2.0 ns smii_din hold time after smii_gclk t h 1ns (input) smii_don (output) smii_gsync (output) smii_gclk (input) t cyc smii_din t pwh t s t d(2) t d(1) tx_er tx_en txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 tx_er txd0 tx_en txd1 txd2 txd7 txd6 crs rx_dv rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 crs rxd0 rx_dv rxd1 rxd2 rxd7 rxd6 t h n = 1 - 8 - 66 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 18. tx/rx smii ethernet interface (sync as an input) 10 pf load parameter symbol min typ max unit smii_gclk clock period t cyc 8ns smii_gclk duty cycle, t pwh /t cyc 40 60 % smii_gsync setup time before smii_gclk t s1 2.0 ns smii_gsync hold time after smii_gclk t h1 1 smii_don out valid delay from smii_gclk t d(2) 1.5 4.5 ns smii_din setup time before smii_gclk t s 2.0 ns smii_din hold time after smii_gclk t h 1ns (input) smii_don (output) smii_gsync (input) smii_gclk (input) t cyc smii_din t pwh t s t d(2) tx_er tx_en txd0 txd1 txd2 txd3 txd4 txd5 txd6 txd7 tx_er txd0 tx_en txd1 txd2 txd7 txd6 crs rx_dv rxd0 rxd1 rxd2 rxd3 rxd4 rxd5 rxd6 rxd7 crs rxd0 rx_dv rxd1 rxd2 rxd7 rxd6 t h n = 1 - 8 t s1 t h1 - 67 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 19. ethernet management interface 10 pf load parameter symbol min typ max unit mdc clock period t cyc 160 ns mdc pulse width t pwh 80 ns mdio out valid delay from mdc t d 10 50 ns mdio setup time before mdc t s 10 ns mdio hold time after mdc t h 5ns mdio (output) mdc (output) t cyc t pwh t d t h mdio (input) t s read operation write operation - 68 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 20. sdram interface - single word read 30 pf load parameter symbol min typ max unit clk clock period t cyc 10 ns clk duty cycle, t pwh /t cyc 45 55 % cs valid delay from clk t d(1) 2.9 7 ns ras valid delay from clk t d(2) 2.9 7 ns cas valid delay from clk t d(3) 2.9 7 ns we valid delay from clk t d(4) 2.9 7 ns ba(1-0) valid delay from clk t d(5) 2.9 7 ns addr(12-0) valid delay from clk t d(6) 2.9 7 ns data(31-0) setup time to clk t s 2.5 ns data(31-0) hold time from clk t h 1ns read* d0 d1 clk ras cas mask ba(1-0) addr(12-0) data(31-0) (command) cs we cas latency = 3 t s t h note*: all read commands enable the auto precharge feature with addr(10)=1 active nop nop n n * t cyc t pwh t d(1) t d(2) t d(3) t d(4) t d(5) t d(6) - 69 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 21. sdram interface - single word write 30 pf load parameter symbol min typ max unit clk clock period t cyc 10 ns clk duty cycle, t pwh /t cyc 45 55 % cs valid delay from clk t d(1) 2.9 7 ns ras valid delay from clk t d(2) 2.9 7 ns cas valid delay from clk t d(3) 2.9 7 ns we valid delay from clk t d(4) 2.9 7 ns mask valid delay from clk t d(5) 2.9 7 ns ba(1-0) valid delay from clk t d(6) 2.9 7 ns addr(12-0) valid delay from clk t d(7) 2.9 7 ns data(31-0) tristate to driven from clk t d(8) 2.8 7 ns data(31-0) valid delay from clk t d(9) 2.8 7 ns data(31-0) valid hold from clk t h 2.9 7 ns data(31-0) driven to tristate from clk t d(10) 2.9 7 ns active write* nop nop n n * d clk ras mask ba(1-0) addr(12-0) data(31-0) (command) cs we cas note*: all write commands enable the auto precharge feature with addr(10)=1 active write* nop nop m m * d ? t cyc t pwh t d(1) t d(2) t d(3) t d(4) t d(5) t d(6) t d(7) t d(8) t d(9) t h t d(10) - 70 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 22. sdram interface - burst read 30 pf load parameter symbol min typ max unit clk clock period t cyc 10 ns clk duty cycle, t pwh /t cyc 45 55 % cs valid delay from clk t d(1) 2.9 7 ns ras valid delay from clk t d(2) 2.9 7 ns cas valid delay from clk t d(3) 2.9 7 ns we valid delay from clk t d(4) 2.9 7 ns ba(1-0) valid delay from clk t d(5) 2.9 7 ns addr(12-0) valid delay from clk t d(6) 2.9 7 ns data(31-0) setup time to clk t s 2.5 ns data(31-0) hold time from clk t h 1ns active read* read* nop active active active read* nop read* 1 0 2 3 1 * * * d0 d1 d3 d2 d4 3 d5 d6 d7 clk ras cas mask ba(1-0) addr(12-0) data(31-0) (command) cs 2 we cas latency = 3 t s t h * note*: all read commands enable the auto precharge feature with addr(10)=1 0 t cyc t pwh t d(1) t d(2) t d(3) t d(4) t d(5) t d(6) - 71 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 23. sdram interface - burst write 30 pf load note: for burst accesses t d(8) and t h apply as the delay and hold parameters between successive data bytes. parameter symbol min typ max unit clk clock period t cyc 10 ns clk duty cycle, t pwh /t cyc 45 55 % cs valid delay from clk t d(1) 2.9 7 ns ras valid delay from clk t d(2) 2.9 7 ns cas valid delay from clk t d(3) 2.9 7 ns we valid delay from clk t d(4) 2.9 7 ns ba(1-0) valid delay from clk t d(5) 2.9 7 ns addr(12-0) valid delay from clk t d(6) 2.9 7 ns data(31-0) tristate to driven from clk t d(7) 2.8 7 ns data(31-0) valid delay from clk t d(8) 2.8 7 ns data(31-0) valid hold from clk t h 2.9 7 ns data(31-0) driven to tristate from clk t d(9) 2.9 7 ns active write* nop active active active nop 1 0 2 3 1 * * * d0 d1 d3 d2 d4 3 d5 d6 d7 clk ras mask ba(1-0) addr(12-0) data(31-0) (command) cs 2 we cas write* write* write* * note*: all write commands enable the auto precharge feature with addr(10)=1 0 t cyc t pwh t d(1) t d(2) t d(3) t d(4) t d(5) t d(6) t d(7) t d(8) t h t d(9) - 72 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 24. rx vc-3 poh byte interface 50 pf load parameter symbol min typ max unit rpclk clock period t cyc 51.44 ns rpclk clock duty cycle 40 60 % rpale/rpadd out valid delay from rpclk t d(1) 416ns rpdle/rpdat out valid delay from rpclk t d(2) 416ns rpdat (output) (output) rpadd (output) rpale (output) rpclk (output) t cyc rpdle t d(1) t d(2) poh data address a0 a6 a7 d0 d0 d1 d6 d7 a5 a4 a3 a2 a1 d5 d4 - 73 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 25. tx vc-3 poh byte interface 50 pf load parameter symbol min typ max unit tpclk clock period t cyc 51.44 ns tpclk clock duty cycle 40 60 % tpale/tpadd out valid delay from tpclk t d(1) 416ns tpdle out valid delay from tpclk t d(2) 416ns tpdat setup time before tpclk t s 13 ns tpdat hold time after tpclk t h 0ns tpdat (input) (output) tpadd (output) tpale (output) tpclk (output) t cyc tpdle t d(1) t d(2) poh data address a0 a6 a7 d0 d0 d1 d6 d7 a5 a4 a3 a2 a1 d5 d4 t s t h - 74 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 26. rx low order poh byte interface 50 pf load parameter symbol min typ max unit rpclk1 clock period t cyc 51.44 ns rpclk1 clock duty cycle 40 60 % rpale1/rpadd1 out valid delay from rpclk1 t d(1) 416ns rpdle1/rpdat1 out valid delay from rpclk1 t d(2) 416ns rpdat1 (output) (output) rpadd1 (output) rpale1 (output) rpclk1 (output) t cyc rpdle1 t d(1) t d(2) poh data (8-bits) address (12-bits) d0 d0 d1 d4 d5 a7 a6 a0 a11 a10 a9 a8 d7 d6 - 75 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 27. tx low order poh byte interface 50 pf load parameter symbol min typ max unit tpclk1 clock period t cyc 51.44 ns tpclk1 clock duty cycle 40 60 % tpale1/tpadd1 out valid delay from tpclk1 t d(1) 416ns tpdle1 out valid delay from tpclk1 t d(2) 416ns tpdat1 setup time before tpclk1 t s 13 ns tpdat1 hold time after tpclk1 t h 0.1 ns tpdat1 (input) (output) tpadd1 (output) tpale1 (output) tpclk1 (output) t cyc tpdle1 t d(1) t d(2) poh data (8-bits) address (12-bits) d0 d0 d1 d4 d5 a7 a6 a0 a11 a10 a9 a8 d7 d6 t s t h - 76 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 28. rx vc-3 alarm indication port interface 50 pf load notes: 1. all the output signals are synchronous with the rising edge of internal clock sysclk (rtclk=19.44mhz). according to a configuration bit, the framing pulse and the data can be "generated" on the falling edge or rising edge of raipc or raipc1. 2. the minimum value of t d (4 ns) is maintained because the data and framing pulse are placed on the output when the falling/rising edge of the raipc/raipc1 is placed on the output. the maximum value of t d is also maintained. parameter symbol min typ max unit raipc clock period t cyc 206 ns raipc clock duty cycle 40 60 % raipf/raipd output valid delay from raipc t d 415ns (output) raipf (output) raipc (output) t cyc raipd 1st bit last bit 2nd bit 3rd bit .... .... t d - 77 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 29. tx vc-3 alarm indication port interface 50 pf load notes: 1. all 3 inputs are double synchronized with the rising edge of sysclk (rtclk=19.44mhz). the taipc/taipc1 input clocks are working at sysclk divided by 4. 2. if 2 ethermap-3 plus devices are linked with the alarm indication ports, since the raipf is set to 1 during one raipc period (200 ns), the duration of the framing pulse is close to 200 ns at the input of taipf. parameter symbol min typ max unit taipc clock period t cyc 206 ns taipc clock duty cycle 40 60 % taipf/taipd setup time before taipc t s 60 ns taipf/taipd hold time after taipc t h 60 ns (input) ta i p f (input) ta i p c (input) t cyc ta i p d 1st bit last bit 2nd bit 3rd bit .... .... t s t h - 78 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 30. rx low order alarm indication port interface 50 pf load notes: 1. all the output signals are synchronous with the rising edge of internal clock sysclk (rtclk=19.44mhz). according to a configuration bit, the framing pulse and the data can be "generated" on the falling edge or rising edge of raipc or raipc1. 2. the minimum value of t d (4 ns) is maintained because the data and framing pulse are placed on the output when the falling/rising edge of the raipc/raipc1 is placed on the output. the maximum value of t d is also maintained. parameter symbol min typ max unit raipc1 clock period t cyc 206 ns raipc1 clock duty cycle 40 60 % raipf1/raipd1 output valid delay from raipc1 t d 415ns (output) raipf1 (output) raipc1 (output) t cyc raipd1 1st bit last bit 2nd bit 3rd bit .... .... t d - 79 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 31. tx low order alarm indication port interface 50 pf load notes: 1. all the 3 inputs are double synchronized on the rising edge of sysclk (rtclk=19.44mhz). the taipc/taipc1 input clocks are working at sysclk divided by 4. . 2. if 2 ethermap-3 plus devices are linked with the alarm indication ports, since the raipf is set to 1 during one raipc period (200 ns), the duration of the framing pulse is close to 200 ns at the input of taipf. parameter symbol min typ max unit taipc1 clock period t cyc 206 ns taipc1 clock duty cycle 40 60 % taipf1/taipd1 setup time before taipc1 t s 60 ns taipf1/taipd1 hold time after taipc1 t h 60 ns (input) ta i p f 1 (input) ta i p c 1 (input) t cyc ta i p d 1 1st bit last bit 2nd bit 3rd bit .... .... t s t h - 80 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 32. asynchronous microprocessor interface: intel-type write cycle timing 50 pf load see parameter table on next page. a(15-0) (inputs) t su(1) t h(1) t inactive t delay t su(3) t d(1) t h(4) t h(3) t h(2) sel (input) wr (input) rd (input) d(15-0) (input/output) microprocessor data ready (output) t su(2) t su(4) t d(2) - 81 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers notes: 1. micclk must always be applied to the ethermap-3 plus to run the microprocessor interface. 2. for gmii mode, the minimum micclk clock frequency is 25 mhz. for smii mode, the minimum micclk clock fre- quency is 6.5 mhz. parameter symbol min typ max unit micclk clock period (not shown in diagram) (see note 1) t cyc 20 note 2 ns micclk duty cycle t pwh /t cyc 45 55 % a(15-0) setup time to sel assertion t su(1) 0ns a(15-0) hold time from sel deassertion t h(1) 0ns rd deassertion setup time to sel assertion t su(2) 0ns sel assertion setup time to wr assertion t su(3) 5ns wr and sel assertion to ready valid delay t d(1) 213ns wr or sel deassertion to ready tristate delay t d(2) 217ns sel deassertion (high) time between accesses t inactive 10 ns sel hold time from wr deassertion t h(2) 5ns wr hold time from ready assertion t h(3) 0ns d(15-0) input setup time to wr assertion t su(4) 5ns d(15-0) input hold from wr deassertion t h(4) t cyc + 5 ns ready assertion from wr assertion t delay t cyc 6*t cyc + 1.3 s- - 82 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 33. asynchronous microprocessor interface: intel-type read cycle timing 50 pf load see parameter table on next page. a(15-0) (inputs) t su(1) t h(1) t inactive t delay(1) t su(3) t d(1) t h(3) t h(2) sel (input) rd (input) wr (input) d(15-0) (input/output) ethermap-3 plus data ready (output) t su(2) t d(2) t d(4) t d(3) t d(5) t delay(2) - 83 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers notes: 1. the micclk must always be applied to the ethermap-3 plus to run the microprocessor interface. 2. t r max = 4.70 ns and t f max = 4.76 ns. 3. for gmii mode, the minimum micclk clock frequency is 25 mhz. for smii mode, the minimum micclk clock fre- quency is 6.5 mhz. parameter symbol min typ max unit micclk clock period (not shown in diagram) (see note 1) t cyc 20 note 3 ns micclk duty cycle t pwh /t cyc 45 55 % a(15-0) setup time to sel assertion t su(1) 0ns a(15-0) hold time from sel deassertion t h(1) 0ns wr deassertion setup time to sel assertion t su(2) 0ns sel assertion setup time to rd assertion t su(3) 5ns rd and sel assertion to ready valid delay t d(1) 213ns sel deassertion (high) time between accesses t inactive t cyc ns sel hold time from rd deassertion t h(2) 5ns rd hold time from ready assertion t h(3) 0ns ready assertion from rd and sel assertion t delay t cyc 6*t cyc + 1.3 s- d(15-0) output tristate turned off from rd and sel assertion t d(2) 211ns d(15-0) output valid delay from rd or sel deassertion t d(3) 1ns d(15-0) output tristate delay from rd or sel deassertion t d(4) 314ns rd or sel deassertion to ready tristate delay t d(5) 217ns d(15-0) output rise and fall times t r ,t f 2.49 note 2 ns ready assertion to rd deassertion t delay(2) 2*t cyc ns - 84 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 34. asynchronous microprocessor interface: motorola 68360-type write cycle timing 50 pf load see parameter table on next page. t su(1) t h(1) t inactive t delay t su(2) t h(4) t h(3) t h(2) sel (input) ds (input) rd/wr (input) d(15-0) (input/output) microprocessor data a(15-0) (inputs) t su(4) t d(1)(max) dtack (output) t d(1)(min) t d(3) - 85 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers notes: 1. the micclk must always be applied to the ethermap-3 plus to run the microprocessor interface. 2. for gmii mode, the minimum micclk clock frequency is 25 mhz. for smii mode, the minimum micclk clock fre- quency is 6.5 mhz. parameter symbol min typ max unit micclk clock period (not shown in diagram) (see note 1) t cyc 20 note 2 ns micclk duty cycle t pwh /t cyc 45 55 % a(15-0)/rd/wr setup time to sel assertion t su(1) 0.0 ns a(15-0)/rd/wr hold time from sel deassertion t h(1) 6.0 ns sel assertion setup time to ds assertion t su(2) 5.0 ns sel and ds assertion to dtack valid delay t d(3) 0.0 15 ns sel or ds deassertion to dtack deassertion delay t d(1) 1.0 15 ns sel deassertion (high) time between accesses t inactive t cyc ns sel hold time from ds deassertion t h(2) 3.0 ns ds hold time from dtack assertion t h(3) 0.0 ns d(15-0) input setup time to ds assertion t su(4) 5.0 ns d(15-0) input valid hold from ds deassertion t h(4) t cyc ns dtack assertion from ds assertion t delay t cyc 6*t cyc + 1.3 s- - 86 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 35. asynchronous microprocessor interface: motorola 68360-type read cycle timing 50 pf load see parameter table on next page. a(15-0) (inputs) t su(1) t h(1) t inactive t delay t su(2) t h(3) t h(2) t d(2)(max) sel (input) ds (input) rd/wr (input) d(15-0) (input/output) ethermap-3 plus data dtack (output) t d(4) t d(6) t d(5) t d(2)(min) (inputs) t d(1) - 87 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers notes: 1. the micclk must always be applied to the ethermap-3 plus to run the microprocessor interface. 2. t r max = 4.70 ns and t f max = 4.76 ns. 3. for gmii mode, the minimum micclk clock frequency is 25 mhz. for smii mode, the minimum micclk clock fre- quency is 6.5 mhz. parameter symbol min typ max unit micclk clock period (not shown in diagram) (see note 1) t cyc 20 note 3 ns micclk duty cycle t pwh /t cyc 45 55 % a/rd/wr setup time to sel assertion t su(1) 0.0 ns a/rd/wr hold time from sel deassertion t h(1) 6.0 ns sel assertion setup time to ds assertion t su(2) 5.0 ns sel and ds assertion to dtack valid delay t d(1) 0.0 23 ns sel or ds deassertion to dtack deassertion delay t d(2) 1.0 23 ns sel deassertion (high) time between accesses t inactive t cyc ns sel hold time from ds deassertion t h(2) 3.0 ns ds hold time from dtack assertion t h(3) 0.0 ns dtack assertion from ds assertion t delay t cyc 6*t cyc + 1.3 s- d(15-0) output tristate turned off from sel assertion t d(4) 3.0 17 ns d(15-0) output valid hold from sel deassertion t d(5) 1.0 ns d(15-0) output tristated from sel deassertion t d(6) 3.0 14 ns d(15-0) output rise and fall times t r ,t f 2.49 note 2 ns - 88 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 36. synchronous microprocessor interface: motorola mpc860-type read cycle timing 50 pf load notes: 1. only one wait state is shown (i.e., t delay = 1 micclk cycle), but the ethermap-3 plus can insert more wait states by keeping ta deasserted for additional clock cycles. thus t delay can be extended for a maximum of 30 micclk cycles. the extension of t delay is caused by states of the internal logic and is not programmable by the user. 2. sel can be held low for multiple accesses without being brought high. 3. an extra wait state is inserted to meet setup/hold time of data / ta . see parameter table on next page. a(15-0) t su(1) t h(3) sel (input) ts (input) rd/wr (input) d(15-0) (input/output) ethermap-3 plus data ta (output) (inputs) micclk (input) wait state t su(3) t d(5) t d(7) t h(2) t su(2) t h(1) t su(4) t h(4) t delay t d(1) t cyc t pwh t d(6) t d(4) t d(3) extra wait state - 89 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers notes: 1. the micclk must always be applied to the ethermap-3 plus to run the microprocessor interface. 2. t r max = 4.70 ns and t f max = 4.76 ns. 3. for gmii mode, the minimum micclk clock frequency is 25 mhz. for smii mode, the minimum micclk clock fre- quency is 6.5 mhz. parameter symbol min typ max unit micclk clock period (see note 1) t cyc 20 note 3 ns micclk duty cycle t pwh /t cyc 40 60 % a(15-0) setup time to micclk t su(1) 4ns a(15-0) hold time from micclk t h(1) 1ns sel setup time to micclk t su(2) 4ns sel hold time from micclk t h(2) 1ns ts setup time to micclk t su(3) 4ns ts hold time from micclk t h(3) 1ns rd/wr setup time to micclk t su(4) 4ns rd/wr hold time from micclk t h(4) 3ns d(15-0) output driven from micclk t d(1) 015ns d(15-0) output stable from micclk t d(3) 315ns d(15-0) output tristate from micclk t d(4) 417ns ta output driven low and stable from micclk t d(5) 010ns ta output driven high from micclk t d(6) 310ns ta output tristate from sel t d(7) 417ns ta assertion from ts assertion t delay t cyc 6*t cyc + 1.3 s- d(15-0) output rise and fall times t r ,t f 2.49 note 2 ns - 90 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 37. synchronous microprocessor interface: motorola mpc860-type write cycle timing 50 pf load notes: 1. only one wait state is shown (i.e., t delay = 1 micclk cycle), but the ethermap-3 plus can insert more wait states by keeping ta deasserted for additional clock cycles. thus t delay can be extended for a maximum of 30 micclk cycles. the extension of t delay is caused by states of the internal logic and is not programmable by the user. 2. sel can be held low for multiple accesses without being brought high. see parameter table on next page. a(15-0) t su(1) t h(3) sel (input) ts (input) rd/wr (input) d(15-0) (input/output) microprocessor data ta (output) (inputs) micclk (input) wait state t s(3) t d(1) t d(3) t h(2) t su(2) t h(1) t su(4) t h(4) t delay t cyc t pwh t d(2) t s(5) t h(5) - 91 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers notes: 1. the micclk must always be applied to the ethermap-3 plus to run the microprocessor interface. 2. for gmii mode, the minimum micclk clock frequency is 25 mhz. for smii mode, the minimum micclk clock fre- quency is 6.5 mhz. parameter symbol min typ max unit micclk clock period (see note 1) t cyc 20 note 2 ns micclk duty cycle t pwh /t cyc 40 60 % a(15-0) setup time to micclk t su(1) 4ns a(15-0) hold time from micclk t h(1) 1ns sel setup time to micclk t su(2) 4ns sel hold time from micclk t h(2) 1ns ts setup time to micclk t su(3) 4ns ts hold time from micclk t h(3) 1ns rd/wr setup time to micclk t su(4) 4ns rd/wr hold time from micclk t h(4) 3ns d(15-0) setup time to micclk t su(5) 4ns d(15-0) hold time from micclk t h(5) 1.5 ns ta output driven low and stable from micclk t d(1) 010ns ta output driven high from micclk t d(2) 310ns ta output tristate from sel t d(3) 417ns ta assertion from ts assertion t delay t cyc 6*t cyc + 1.3 s- d(15-0) output rise and fall times t r ,t f 4.8 5.3 ns - 92 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 38. boundary scan timing parameter symbol min max unit tck clock period t cyc 50 ns tck clock duty cycle t pwh /t cyc 40 60 % tms setup time to tck t su(1) 3.0 ns tms hold time after tck t h(1) 15 ns tdi setup time to tck t su(2) 3.0 ns tdi hold time after tck t h(2) 15 ns tdo delay from tck t d 4.0 20 ns trs pulse width t pw 50 ns tms tdi tdo t d(min) tck (input) (input) (input) (output) t h(2) t su(2) t su(1) t h(1) t pwh t cyc trs (input) t pw t d(max) - 93 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers operation sonet/sdh processing general the mapper and demapper blocks provide the sonet/sdh processing of the ethermap-3 plus . the mapper maps and multiplexes (virtual concatenated) payload into a vc-4/sts-3c/vc-3/sts-1 structure on the add telecom bus. conversely the demapper demaps and demultiplexes a vc-4/sts-3c/vc-3/sts-1 structure from the drop telecom bus into (virtual concatenated) payload. figure 39 shows a functional block diagram of the mapper and demapper blocks. vc-4/sts-3c poh monitor tu-3 pointer tracker/retimer vc-3/sts-1/tug-3 timeslot interchange vc-3/sts-1 poh monitor lo pointer tracker low order timeslot interchange low order poh monitor receive/drop telecom bus vc-4/sts-3c poh generator tu-3 pointer generator vc-3/sts-1/tug-3 timeslot interchange vc-3/sts-1 poh generator lo pointer generator low order timeslot interchange low order poh generator transmit/add telecom bus drop telecom bus add telecom bus rx high order poh port rx low order poh port tx low order poh port tx high order poh port to rx virtual concatenation from tx virtual concatenation figure 39. functional block diagram of the mapper/demapper rx low order alarm indication port tx low order alarm indication port rx high order alarm indication port tx high order alarm indication port remote information (rx high order alarm indication port) remote information (rx low order alarm indication port) remote information (rx high order alarm indication port) - 94 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 40 presents a bi-directional functional model according to itu-t g.783 of the functionality made available through the mapper and demapper blocks (also see itu-t g.806 for the terminology used). the telecom bus is represented as server layer to the s3 or s4 high order path layer. . te l e combus combus/s3_a combus/s4_a s3_tt sm_tt s3/sm_a s4/sm_a s4/s3_a s3_c sm_c s3-xv/s3-x_a s4-xv/s4-x_a sm-xv/sm-x_a s4_tt ri ri ri figure 40. functional model of the mapper/demapper - 95 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers bypass modes each of the mapper and demapper blocks has a bypass mode which can be configured per sts-1/vc-3/tug-3 timeslot to obtain the desired sonet/sdh mapping structure. superimposing functional model and block diagram in figure 41 reveals which blocks require bypassing. combus/s3_a combus/s4_a s3_tt sm_tt s3/sm_a s4/sm_a s4/s3_a s3_c s3-xv/s3-x_a s4-xv/s4-x_a sm-xv/sm-x_a s4_tt sm_c combus/s3_a combus/s4_a s3_tt sm_tt s3/sm_a s4/sm_a s4/s3_a s3_c s3-xv/s3-x_a s4-xv/s4-x_a sm-xv/sm-x_a s4_tt sm_c te l e combus combus/s3_a combus/s4_a s3_tt sm_tt s3/sm_a s4/sm_a s4/s3_a s3_c s3-xv/s3-x_a s4-xv/s4-x_a sm-xv/sm-x_a sm_c te l e combus combus/s3_a combus/s4_a s3_tt sm_tt s3/sm_a s4/sm_a s4/s3_a s3_c s3-xv/s3-x_a s4-xv/s4-x_a sm-xv/sm-x_a s4_tt sm_c vc-4/sts-3c poh generator tu-3 pointer generator vc-3/sts-1/ tug-3 tsi vc-3/sts-1 poh generator lo pointer generator lo tsi lo poh generator vc-4/sts-3c poh monitor tu-3 pointer tracker/retimer vc-3/sts-1/ tug-3 tsi vc-3/sts-1 poh monitor lo pointer tr a ck e r lo tsi lo poh monitor transmit/add telecom bus receive/drop telecom bus ri ri ri ri ri ri sts-1/au-3 sts-1/au-3 tug-3 tug-3 figure 41. mapper/demapper bypass modes - 96 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers receive direction: the vc-4/sts-3c poh monitor is bypassed by setting bit 1 (bypass) of address 0x1f680, the tu-3 pointer tracker/retimer can be physically bypassed (the output of the vc-4/sts-3c poh monitor is also distributed as additional port to the receive vc-3/sts-1/tug-3 tsi, i.e., the path from s4_tt to s4-xv/s4-x_a) for an unstructured vc-4/sts-3c signal. for substructured vc-4 or au- 3/sts-1 based signals the tu-3 pointer tracker/retimer supports the following modes per high order time slot by writing the aug1_format and tug3_format bits at address 0x19c80 (0x19c90, 0x19ca0): the receive vc-3/sts-1/tug-3 tsi is bypassed by connecting straight through, the vc-3/sts-1 poh monitor can be bypassed per high order time slot by setting bit 1 (bypass) of address 0x1d900 (0x1d920, 0x1d940), the low order pointer tracker can be bypassed per high order time slot by writing 0x0001 to the bypass register at address 0x1c620 (0x1c622, 0x1c624), the receive low order tsi can be bypassed per high order time slot by writing 0x0001 to the bypass register at address 0x1c600 (0x1c602, 0x1c604), the low order poh monitor can be bypassed per high order time slot by writing 0x0001 to the bypass register at address 0x148e0 (0x148e2, 0x148e4), additionally for a vc-4/sts-3c non-substructured bypass (s4_tt to s4-xv/s4-x_a) the vc-4 has c4 register at address 0x14800 has to be set. transmit direction: the vc-4/sts-3c poh generator is bypassed by setting bit 3 (passpoh) of address 0x1d058, the tu-3 pointer generator supports the following modes per high order time slot by writing the conversion type register at address 0x19ee0 (0x19ee8, 0x19ef0): the transmit vc-3/sts-1/tug-3 tsi is bypassed by connecting straight through, the vc-3/sts-1 poh generator can be bypassed per high order time slot by setting bit 3 (passpoh) of address 0x1f960 (0x1f962, 0x1f964), the low order pointer generator can be bypassed per high order time slot by writing 0x0001 to the bypass register at address 0x1a480 (0x1a482, 0x1a484), the transmit low order tsi can be bypassed per high order time slot by writing 0x0001 to the bypass register at address 0x1a4c0 (0x1a4c2, 0x1a4c4), the low order poh generator can be bypassed per high order time slot by writing 0x0001 to the bypass register at address 0x1a440 (0x1a442, 0x1a444), table 1: tu-3 pointer tracker/retimer modes 0x19c80/90/a0 mode 0x0000 au-3/sts-1 mapping combus/s3_a to s3_c 0x0001 au-4/vc-4/tug-3/tu-3 mapping s4_tt to s4/s3_a 0x0003 au-4/vc-4/tug-3/tug-2 mapping s4_tt to s4/sm_a table 2: tu-3 pointer generator modes 0x19ee0/e8/f0 mode 0x0000 au-3/sts-1 mapping s3_c to combus/s3_a 0x0001 au-4/vc-4/tug-3/tu-3 mapping special case where internally au-3 is generated and converted to tug-3. the au-4 has a fixed pointer, but the tu-3 pointers may adjust to cope with phase differences between the tu-3 and au-3. 0x0002 au-4/vc-4/tug-3/tu-3 mapping s3_c to s4/s3_a 0x0004 au-4/vc-4/tug-3/tug-2 mapping s4/sm_a to s4_tt 0x0005 au-4/vc-4 unstructured mapping s4-xv/s4-x_a to s4_tt - 97 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers transmit high order path termination (vc-3/vc-4/sts-1/sts-3c poh generator) general the ethermap-3 plus optionally provides transmit high order path termination functions for one sts-3c- spe/vc-4s and three sts-1-spe/vc-3s. j1 the transmitted j1 path trace message can be written by the microprocessor for transmission into the up_j1messagebytes ram at address 0x1d080 (0x1fa00, 0x1fa80, 0x1fb00). the ethermap-3 plus device supports 16 or 64 byte long repeating messages, the length can be selected via the j1_length64 register, i.e., bit 0 at address 0x1d040 (0x1f900, 0x1f902, 0x1f904). b3 the b3 is calculated and transmitted for each spe/vc. for test purposes the ethermap-3 plus supports a b3 error mask in the poh ram, at address 0x1d000 (0x1f800, 0x1f810, 0x1f820). when the b3_masking register, bit 1 at address 0x1d040 (0x1f900, 0x1f902, 0x1f904), is set, the calculated b3 is exor ? ed with the b3 error mask before being inserted into the signal. c2 the c2 signal label can be written by the microprocessor for transmission into the c2 position of the poh ram at address 0x1d002 (0x1f802, 0x1f812, 0x1f822). the ethermap-3 plus also has the option to source an unequipped signal by setting the forceuneq register (bit 1 at address 0x1d058 (0x1f960, 0x1f962, 0x1f964)) or a supervisory unequipped spe/vc by setting the forcesupuneq register (bit 2 at address 0x1d058 (0x1f960, 0x1f962, 0x1f964)). g1 the received b3 errors are automatically inserted into the g1 byte as path rei. the ethermap-3 plus has on option to transmit either a single bit path rdi or an enhanced 3-bit path rdi. selection is made via the onebitrdi register (bit 3 at address 0x1d058 (0x1f960, 0x1f962, 0x1f964)). the transmitted g1 bytes can be generated from local alarm conditions or derived from the alarm indication port interface. the selection is made per high order path timeslot on the high order alarm indication port interface via the selectinterface register at address (0x19a80+4(decimal)*timeslot). see the high order alarm indication port interface section for the time slot assignment. when the uni-directional option is active by setting the g1_unidirectional register (bit 2 at address 0x1d058 (0x1f960, 0x1f962, 0x1f964)), all transmitted remote information is set to zero. 0x19a80+4(decimal)*timeslot selectinterface 0 rdi and rei generated from local alarm conditions. 1 rdi and rei derived from high order alarm indication port interface. - 98 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers h4 the h4 byte can be written by the microprocessor into the poh ram, at address 0x1d008 (0x1f808, 0x1f818, 0x1f828), or by the high order poh port interface for transmission, or it can be selected to carry the v1/v2 multiframe in case the spe/vc is substructured into low order vt/tus, or it can be selected to carry the virtual concatenation multiframe and control packets in case high order virtual concatenation is active for this spe/vc. this selection is made via the h4_control register, bits 11-10 at address 0x1d040 (0x1f900, 0x1f902, 0x1f904): f2, f3/z3, k3/z4, and n1/z5 the f2, f3/z3, k3/z4, and n1/z5 bytes can be written by the microprocessor into the poh ram, see table 241, on page 338 , or by the high order poh port interface for transmission. these values are static and are not acted upon by the ethermap-3 plus transmit logic. the source can be selected via the f2_control, f3_control, k3_control and n1_control registers (bits 9, 12, 13 and 14 at address 0x1d040 (0x1f900, 0x1f902, 0x1f904)): a value of 0 selects the poh ram, a value of 1 selects the poh port. receive high order path termination (vc-3/vc-4/sts-1/sts-3c poh monitor) general the ethermap-3 plus optionally provides receive high order path termination functions for one sts-3c- spe/vc-4s and three vc-3/sts-1-spe/vc-3s. the received poh bytes are always forwarded to the receive high order poh port interface and written to the receive high order poh ram at address 0x1f640 (0x1d800, 0x1d820, 0x1d840). j1 both 16 and 64 byte messages can be received. the expected j1 path trace message can be configured at address 0x1f500 (0x1de00, 0x1de80, 0x1df00). the received j1 path trace is compared with the microprocessor written expected j1 path trace. if a mismatch occurs between received and expected j1 path trace, a trace identifier mismatch defect (dtim) is declared. an all-zero path trace is also reported to allow detection of an unequipped signal versus a supervisory unequipped signal. the microprocessor can retrieve the value of the received j1 path trace of one vc-4/sts-3c and of one vc- 3/sts-1 path termination at a time. bit 11 bit 10 h4_control 0 0 insert h4 from the poh ram, e.g. for an unstructured, non-virtual concatenated vc- 4/sts-3c. 0 1 insert h4 from the high order poh port. 1 0 pass the multiframe and control word for a virtual concatenated vc-3/sts-1. 1 1 generate the v1/v2 multiframe for vc-3/vc-4/sts-1 spe substructured into lo vt/tu ? s. - 99 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers the number of trace message multiframes to set or reset the tim defect is configurable via registers j1_nrofframestosettim (bits 6-3 at address 0x1f682 (0x1d902, 0x1d922, 0x1d942)) and j1_nrofframestoresettim (bits 10-7 at address 0x1f682 (0x1d902, 0x1d922 and 0x1d942)). b3 performance monitor counters are provided for the b3 errors and b3 block errors. optionally the burst error degraded signal defect can be detected. the threshold values and interval times are configurable per high order path via registers b3_setthreshold, b3_clearthreshold, b3_setnrofintervals and b3_clearnrofintervals at address 0x1f688-0x1f68c (0x1d908-0x1d90c, 0x1d928-0x1d92c, 0x1d948- 0x1d94c). the signal degrade registers pertain to the detection of the degraded signal defect, assuming a bursty distribution of errors, as in 6.2.3.1.2/g.806. above registers correspond to the degthr and degm settings referred to by 6.2.3.1.2/g.806. the ethermap-3 plus does not detect "excessive error" (excessive error assumes a poisson distribution of errors, as in 6.2.3.1.1/g.806). the detection algorithms assuming bursty distribution uses the one second block error counts for performance monitoring. the one second clock onesec (see page 43), is required. the degraded signal defect (ddeg) is declared if b3_setnrofintervals consecutive bad intervals (interval is the one second period used for performance monitoring) are detected. an interval is declared bad if the number of errored blocks in that interval > degraded threshold (b3_setthreshold). the degraded signal defect is cleared if b3_clearnrofintervals consecutive good intervals are detected. an interval is declared good if the number of errored blocks in that interval < b3_clearthreshold. the parameters b3_setnrofintervals and b3_clearnrofintervals are provisionable in the range 2 to 10. the degthr parameters b3_setthreshold and b3_clearthreshold are to be provisioned as a number of errored blocks in the range of 0 < degthr < number of blocks in the interval, i.e., 8000. address register description 0x1f400 (0x1db00) accepted 64 byte trace message 0x1f742 (0x1dc42), bit 0 j1_report_enable enable reporting of the accepted j1 trace message for the j1_report_channel. 0x1f742 (0x1dc42), bit 2-1 j1_report_channel select the vc-4/sts-3c spe (vc-3/sts-1 spe) chan- nel for which the j1 accepted trace message is retrieved. 0x1f760 (0x1dc50), bit 0 j1_stable_1 a constantly repeating single j1 byte has been detected. 0x1f760 (0x1dc50), bit 1 j1_stable_16 a 16-byte j1 trace message has been detected. 0x1f760 (0x1dc50), bit 2 j1_stable_64 a 64-byte j1 trace message has been detected. - 100 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers c2 unequipped detection (duneq) and vc ais detection (dais) is performed on the incoming c2 byte. the expected c2 signal label can be written by the microprocessor at address 0x1f750 (0x1dcb0, 0x1dcb2, 0x1dcb4). if a mismatch occurs between the received c2 and the expected c2, a payload mismatch defect (dplm) is declared. the accepted c2 value is written to the on-chip ram for retrieval by the microprocessor at address 0x1f738, (0x1dc60, 0x1dc64, 0x1dc68). g1 a performance monitoring counter is provided for the path rei. the g1 byte is monitored for the presence of single bit or enhanced path rdi. h4 the h4 byte is written to the on-chip ram for retrieval by the microprocessor. it can be optionally monitored for the v1/v2 multiframe in case the spe/vc is substructured into low order vt/tus, or the virtual concatenation multiframe in case high order virtual concatenation is active for this spe/vc. the selection is made per high order path via the h4_multiframetype register (bits 1-0 at address 0x1f690 (0x1d910, 0x1d930, 0x1d950)). f2, f3/z3, k3/z4, and n1/z5 the f2, f3/z3, k3/z4, and n1/z5 are written to the on-chip high order poh ram for retrieval by the microprocessor. high order poh port interface all received high order poh bytes of all vc-3/sts-1 and vc-4/sts-3c are output on the receive high order poh port interface. the transmit high order poh port interface allows inserting most high order poh byte into the vc-3/sts-1 and vc-4/sts-3c poh. j1 and c2 cannot be selected from the transmit ho poh port interface, while the b3 bip-8 is used as error mask on the calculated bip-8 for test purposes. each interface consists of clock, data, data enable, address and address enable lines. h4_multiframetype 00 disable monitoring of h4 for vc-4/sts-3c spe. 01 monitor the v1/v2 multiframe for a vc-3/vc-4/sts-1 spe substructured into low order vt/tus. 10 monitor the virtual concatenation multiframe. 11 disable monitoring of h4 for vc-3/sts-1 spe. - 101 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers the address is a 8-bit word with following format: high order alarm indication port interface the high order alarm indication port interface transports the remote information (ri) from the vc-3/sts-1 and vc-4/sts-3c poh sink/monitor to the poh source/generator. the remote information consists of the rei and (enhanced) rdi values to insert by the poh generator. the high order poh monitor blocks multicast the remote information of all vc-3/sts-1 and vc-4/sts-3c channels to the high order poh generator blocks and the receive high order alarm indication port interface. the high order poh generator blocks can select per vc-3/sts-1 and vc-4/sts-3c channel if the remote information is taken from the transmit high order alarm indication port interface or the internal remote information provided by the high order poh monitor blocks. each interface consists of a clock, data and start of frame line. a start of frame pulse coincides with the first bit of the high order alarm indication port data frame. each high order alarm indication port data frame consists of 16 timeslots of 32 bits per timeslot: a7-a6 a5-a4 a3 a2 a1 a0 00 (reserved) channel number 00 = vc-3/sts-1 #1 01 = vc-3/sts-1 #2 10 = vc-3/sts-1 #3 11 = vc-4/sts-3c 0000 j1 0001 b3 0010 c2 0011 g1 0100 f2 0101 h4 0110f3/z3 0111k3/z4 1000n1/z5 frame x x+1 timeslot 0 1 ... 15 ... bit number 31 30 ... 1 0 31 30 ... 1 0 ... 31 30 ... 1 0 ... - 102 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers the first 12 time slots are assigned to vc-3/sts-1 remote information, the last 4 time slots to vc-4/sts-3c remote information: each 32-bit timeslot has a field for the rei and rdi. a valid flag indicates if the value in a field is valid and needs to be processed. invalid values are ignored. au-4 and au-3 pointer generation the generation of the au-4 and au-4 pointer depends upon the timing mode selected for the telecom bus interface (this mode is controlled by lead abust and register ctbadd). drop bus timing mode in drop bus timing mode the au-4 (or au-3) pointer bytes follow the drop dc1j1v1 pulses. add bus timing mode 1 in add bus timing mode 1 (alias "add slave mode") the au-4 (or au-3) pointer bytes follow the pulses on input signal ac1j1v1. the ac1j1v1 pulses (generated by external circuitry like the transwitch phast-3n) must correspond to a fixed pointer value (in other words, the distance between c1 pulse and j1 pulse must be fixed). any fixed value is acceptable. note that the ethermap-3 plus does not insert the h1 h2 byte value on the ad leads. it must be inserted by the external circuitry (like the phast-3n). timeslot assigned to 0 vc-3/sts-1 #1 1 vc-3/sts-1 #2 2 vc-3/sts-1 #3 3..11 reserved for vc-3/sts-1 12 vc-4/sts-3c #1 13..15 reserved for vc-4/sts-3c bit number name description 31 rei-valid rei value in bits 30..27 is valid. 30..27 rei rei value 26 reserved 25 rdi-valid rdi values in bits 24..22 are valid 24 rdi-s enhanced rdi server failure, contributes to single bit rdi 23 rdi-c enhanced rdi connectivity failure, contributes to single bit rdi 22 rdi-p enhanced rdi path failure 21..4 reserved 3..0 crc-4 crc-4 over bits 31..4 - 103 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers add bus timing mode 2 in add bus timing mode 2 (alias "add master mode") the au-4 (or au-3) pointer bytes are fixed at 0. note that the ethermap-3 plus does not insert the h1 h2 byte value on the ad leads. it must be inserted by external circuitry (like the phast-3n). tu-3 pointer generation in all the timing modes, the tu-3 pointer has a fixed value of 595. also, the ethermap-3 plus inserts the tu-3 byte value on the ad leads. tu-3 pointer tracking the incoming negative and positive tu-3 pointer adjustments are counted for performance monitoring. the lop and pointer ais defects are detected. vc-3/sts-1/tug-3 timeslot interchange in each direction the vc-3/sts-1/tug-3 timeslots can be interchanged. each tsi output vc-3/sts-1/tug-3 timeslot can be configured to connect to any tsi input timeslot (sourceslot) or to send an unequipped (forceuneq) or ais (forceais) signal. vt/tu pointer tracking the incoming negative and positive pointer adjustments are counted for performance monitoring. the lop and pointer ais defects are detected. the v1, v2, and v4 bytes are written to the on-chip ram for retrieval by the microprocessor (v1 ram at 0x1cf00, v2 ram at 0x1c000, v4 ram at 0x1c200). vt/tu pointer generation the vt1.5/tu-11 pointer has a fixed value selectable between 0 and 78. the vc-12/tu-12 pointer has a fixed value selectable between 0 and 105. the pointer value of 0 is selected via registers pointervaluezero, bit 0 at address 0x13d00+channel, and pointerzerovalue, bit 1 at address 0x1a800+4(decimal)*channel. for each channel both registers need to correspond. the v4 byte for each low order timeslot can be written by the microprocessor at address 0x1a000+channel. low order timeslot interchange in each direction the low order timeslots can be interchanged. each low order tsi output timeslot can be configured to connect to any tsi input timeslot within the same high order container. this means it is not possible to connect timeslots between au-3/sts-1 ? s. unequipped or ais signals need to be generated via the low order poh generator. cross connects are made by writing the appropriate value into the mapram_data cross connect map. this array of 84 elements is indexed by the output channel number, its value represents the input channel number to be connected to this output channel. the cross connect map consists of two banks of 84 elements. the cross connect hardware reads the information from the active bank, while the software can only write to the inactive bank. when a new configuration is written to the inactive bank, both banks can be swapped. - 104 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers software can select which of the banks is visible for reading. transmit low order path termination (low order poh generator) general the ethermap-3 plus provides transmit low order path termination functions for up to 84 vt1.5-spe/vc-11s or 63 vt2-spe/vc-12s. the low order poh generators are numbered according to the klm numbering: channel = (k-1)*28+(l-1)*4+(m-1) j2 the j2 path trace can be written by the microprocessor for transmission as a 16 byte long repeating message in the transmit low order poh ram at address 0x1b000+16(decimal)*channel. this 16 byte frame is identical to the 16 byte frame of the j0. the msb of byte 1 should be set to 1 and is the trace identifier frame alignment signal. bip-2 the v5 bip-2 is calculated and transmitted for each vt/vc. for test purposes the ethermap-3 plus supports a bip-2 error mask in the transmit low order poh ram, at address 0x1b000. when the bip2_error register, bit 0 at address 0x1a800+4(decimal)*channel, is set, the calculated bip-2 is exor ? ed with the bip-2 error mask before being inserted into the v5 byte. rx tsi tx tsi description usedefaultmapping when set, the cross connect map is disabled: each klm output timeslot is connected to the corresponding klm input timeslot. 0x1c672, bit 1 0x1a400, bit 1 mapram_data cross connect map. disabled if usedefault- mapping is set. 0x1c400 0x1a600 active_mapram_bank_id 0x1c672, bit 2 uppermapramvalid 0x1a400, bit 2 selects the active mapram bank: hardware reads from the active bank, software writes to the inactive bank. bank_id_mapram 0x1c674, bit 0 readuppermaprambank 0x1a400, bit 3 selects the mapram bank visible for reading by software. channel assigned to low order #klm 0 vt1.5/vt2/vc-11/vc-12 #111 1 vt1.5/vt2/vc-11/vc-12 #112 2 vt1.5/vt2/vc-11/vc-12 #113 3 vt1.5/vc-11 #114 4 vt1.5/vt2/vc-11/vc-12 #121 ... ... 82 vt1.5/vt2/vc-11/vc-12 #373 83 vt1.5/vc-11 #374 - 105 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers signal label both the v5 signal label (in the transmit low order poh ram at address 0x1b000) and the k4/z7 extended signal label (ext_signallabel register at address 0x1a802+4(decimal)*channel) can be written by the microprocessor for transmission. the v5 signal label must be set to ? 101 ? to activate the generation of the k4/z7 bit 1 mfas and extended signal label. the ethermap-3 plus also has the option to source an unequipped signal or a supervisory unequipped vt/vc through the senduneq and uneqselect registers at address 0x1a800+4(decimal)*channel. rei/rdi the received v5 bip-2 errors are automatically inserted into the v5 path rei. the ethermap-3 plus has on option to transmit either a single bit v5 path rdi or an enhanced 4-bit v5/k4/z7 path rdi. to enable the 4-bit enhanced path rdi, the low order poh generation, per vt/vc needs to be configured to 3-bit rdi mode. the transmitted rei/rdi can be generated from local alarm conditions or derived from the alarm indication port interface. when the uni-directional option is active, all transmitted remote information is set to zero. k4/z7 bit 2 the k4/z7 bit 2 can be written by the microprocessor or by the high order poh port interface for transmission, or it can be selected to carry the virtual concatenation multiframe and control packets in case low order virtual concatenation is active for this vt/vc. in the latter case, the extended signal label in k4/z7 bit 1 has to be activated to generate the mfas word (see signal label above). the source for the k4/z7 bit 2 can be selected per low order channel through register lo_vc_source, bits 7-6 at address 0x1a804+4(decimal)*channel. v5 rfi the v5 rfi bit can be written by the microprocessor for transmission. this value is static and is not acted upon by the ethermap-3 plus transmit logic. n2/z6 the n2/z6 byte can be written by the microprocessor or by the low order poh port interface for transmission. this value is static and is not acted upon by the ethermap-3 plus transmit logic. senduneq bit 3 uneqselect bit 4 description 0 x source an equipped vt/vc. 1 0 source an unequipped vt/vc. 1 1 source a supervisory unequipped vt/vc bit 7 bit 6 lo_vc_source 0 0 insert k4/z7 bit 2 from the poh ram. 0 1 insert k4/z7 bit 2 from the high order poh port. 10reserved 1 1 pass the multiframe and control word for a virtual concatenated vt1.5-spe/vt2-spe/vc- 11/vc-12 - 106 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers receive low order path termination (low order poh monitor) general the ethermap-3 plus provides receive low order path termination functions for up to 84 vt1.5-spes/vc-11s or 63 vt2-spes/vc-12s. like the low order poh generators, the low order poh monitors are numbered according to the klm numbering: channel = (k-1)*28+(l-1)*4+(m-1) the received poh bytes are always forwarded to the receive low order poh port interface and written to the receive low order poh ram at address 0x17800+4(decimal)*channel. j2 the ethermap-3 plus supports 16 byte j2 trace messages. the received j2 path trace message can be compared with a microprocessor written expected j2 path trace at address 0x16000+16(decimal)*channel. if a mismatch occurs between received and expected j2 path trace, a trace identifier mismatch defect (dtim) is declared. an all-zero path trace is also reported to allow detection of an unequipped signal versus a supervisory unequipped signal. the microprocessor can retrieve the value of the received j2 path trace of one low order path termination at a time. the number of trace message multiframes to set or reset the tim defect is configurable via registers j2_nrofframestosettim (bits 3-0 at address 0x14802) and j2_nrofframestoresettim (bits 7-4 at address 0x14802). bip-2 performance monitor counters are provided for the v5 bip-2 errors and v5 bip-2 block errors. optionally the burst error degraded signal defect can be detected. the threshold values and interval times are configurable per low order path via registers bip2_deg_setthreshold, bip2_deg_clearthreshold, bip2_deg_setnrofintervals and bip2_deg_clearnrofintervals at address 0x17c04-0x17c06 (+ 4*channel). the signal degrade registers pertain to the detection of the degraded signal defect, assuming a bursty distribution of errors, as in 6.2.3.1.2/g.806. above registers correspond to the degthr and degm settings referred to by 6.2.3.1.2/g.806. the ethermap-3 plus does not detect "excessive error" (excessive error assumes a poisson distribution of errors, as in 6.2.3.1.1/g.806). the detection algorithms assuming bursty distribution uses the one second block error counts for performance monitoring. the one second clock onesec (see page 43), is required. address register description 0x14980 accepted 16 byte trace message 0x14800, bit 8 j2_report_enable enable reporting of the accepted j2 trace message for the j2_report_channel. 0x14802, bit 15-9 j2_report_channel select the vt/vc channel for which the j2 accepted trace message is retrieved. 0x148c0, bit 0 j2_stable_1 a constantly repeating single j2 byte has been detected. 0x148c0, bit 1 j2_stable_16 a 16-byte j2 trace message has been detected. - 107 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers the degraded signal defect (ddeg) is declared if bip2_deg_setnrofintervals consecutive bad intervals (interval is the one second period used for performance monitoring) are detected. an interval is declared bad if the number of errored blocks in that interval > degraded threshold (bip2_deg_setthreshold). the degraded signal defect is cleared if bip2_deg_clearnrofintervals consecutive good intervals are detected. an interval is declared good if the number of errored blocks in that interval < bip2_deg_clearthreshold. the parameters bip2_deg_setnrofintervals and bip2_deg_clearnrofintervals are provisionable in the range 2 to 10. the degthr parameters bip2_deg_setthreshold and bip2_deg_clearthreshold are to be provisioned as a number of errored blocks in the range of 0 < degthr < number of blocks in the interval, i.e., 2000. signal label unequipped detection (duneq) and vc ais detection (dais) is performed on the incoming v5 signal label. the expected v5 signal label and the expected k4/z7 extended signal label can be written by the microprocessor. if a mismatch occurs between the received and the expected (extended) signal label, a payload mismatch defect (dplm) is declared. the accepted v5 signal label and k4/z7 extended signal label values are written to the on-chip ram for retrieval by the microprocessor. the number of (multi-)frames to accept a tsl or extended tsl value is configurable via registers tsl_nrofintervals (bits 10-7 at address 0x14800) and etsl_nrofintervals (bits 14-11 at address 0x14800). rei/rdi/rfi a performance monitoring counter is provided for the path rei. the v5/k4/z7 bytes are monitored for the presence of single bit or enhanced path rdi. the v5 byte is monitored for the presence of rfi k4/z7 bit 2 the k4/z7 bit 2 can be optionally monitored for the virtual concatenation multiframe in case lower order virtual concatenation is active for this spe/vc. n2/z6 the n2/z6 byte is written to the on-chip ram for retrieval by the microprocessor. address register description 0x14000+4(decimal)*channel tsl_accepted accepted v5 trail signal label. 0x14002+4(decimal)*channel etsl_accepted accepted k4/z7 extended trail signal label. 0x14400+4(decimal)*channel tsl_expected expected v5 trail signal label. 0x14402+4(decimal)*channel etsl_expected expected k4/z7 extended trail signal label. - 108 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers low order and high order path monitor alarm registers this paragraph gives explanation of the different alarm registers available for the low order and high order poh monitors. (lodmp_pohmonitor, t_vci_rx_vcx_poh), as well as the performance/fault monitoring feature of ethermap-3 plus . also, this explanation completes tables 137 to 151 and tables 188 to 199 . 1. channel defects (channel_defects_record): each bit in this array indicates in real time an alarm detected in the received poh referring to itu g.783, g. 806, these alarms are the detected defects: duneq, dtim, dttizero. none of these defects are inhibited by another one. this type of record allows the user to monitor the real time alarms, disregarding the alarm inhibitions. 2. defect correlations unlatched (channel_defect_correlations_unlatched): for these alarms, defect inhibitions are taken into account. a specific alarm is asserted only if higher order alarm are not present, this is expressed in itu g.783 and g.806, in equations like this one: cuneq = duneq and (not ci_ssf) and dttizero and dtim ctim = dtim and (not ci_ssf) and (not (duneq and dttizero)) the inhibitions of one alarm by another can also be configured. the configuration record to do this for the lodmp_pohmonitor is lodmp_pohmonitor_defect_correlations_config. the configuration is common for all the lo channels. example. when uneq_ssf_inhibit_disable = true then the expression for cuneq becomes: cuneq = duneq and dttizero and dtim 3. defect correlations latched (channel_defect_correlations_latchforint): these are the same as 2. above, but latched. these registers are read only and clear when read. a latched bit can be cleared by writing a one (1) to that bit; writing a zero (0) has no effect. 4. mask (channel_defect_correlations_mask): each bit in this array is associated with a latched alarm; each bit will prevent its corresponding alarm from generating an interrupt. 5. defect correlations latched for pm, fm (channel_defect_correlations_latchforpmfm) these are the same as 3. above, but latched for pm and fm. these registers are read only and are cleared on each one second boundary (not cleared on read). they can also be cleared by writing a zero (0) to each bit; writing a one (1) has no effect. 6. performance monitoring (pm) (channel_defect_correlations_pm): this is a latched alarm indicating that an alarm has occurred over the immediately preceding 1 second interval. only cleared on each one second boundary. 7. fault monitoring (fm) (channel_defect_correlations_fm): this is a latched alarm indicating that the unlatched alarm was continuously asserted, without any alarm events taking place, over the full duration of the immediately preceding 1 second interval. only cleared on each one second boundary. - 109 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers additional explanation about 6 and 7 (use of the onesec clock): the one second clock defines one second time intervals to serve as a time reference for the pm/fm scheme. purpose of performance and fault monitoring (pm and fm): an unlatched alarm may have associated with it a corresponding pm/fm feature, that allows a system to monitor the long term evolution of the particular alarm, in a convenient manner. as an example, a system may wish to monitor if a defect occurred over only a single unit time interval, or, if the defect persisted over several unit time intervals with respect to a certain particular alarm, or a group of alarms. the unit time interval may be 1 second, or any other, as laid down by applicable standards (if any), or as required to implement a specified performance and fault monitoring system. 8. defect correlations configuration (channel_defect_correlations_config of type): this configures the way the defects are inhibited in point 2: e.g., the inhibition expression cdeg <- ddeg and (not dtim) and (not ci_ssf) can have each contribution disabled separately. the channel_defect_correlations_config registers are called - 110 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers low order poh port interface all received low order poh bytes of all 63/84 timeslots are output on the receive low order poh port interface. the transmit low order poh port interface allows inserting most low order poh fields into the low order poh. the v5 bip-2 field is used as error mask on the calculated bip-2 for test purposes. per low order channel and per poh field the low order poh port interface can be selected as the source of that field. if a poh byte transports multiple fields, each field can be selected independently. each interface consists of clock, data, data enable, address and address enable lines. the address is a 12-bit word with following format: the low order time slots are numbered according to the klm numbering: timeslot = (k-1)*28+(l-1)*4+(m-1) address bits register description 0x1a804+4(decimal)*channel 1-0 rei_source set to ? 01 ? to insert the rei (v5 bit 3) field from the poh port 3-2 rdi_source set to ? 01 ? to insert the rdi (v5 bit 8 and k4/z7 bits 5-7) field from the poh port 5-4 ext_tsl_source set to ? 01 ? to insert the extended tsl field (k4/z7 bit 1) from the poh port 7-6 lo_vc_source set to ? 01 ? to insert the low order virtual concatenation control word field (k4/z7 bit 2) from the poh port 9-8 aps_source set to ? 01 ? to insert the aps field (k4/z7 bits 3-4) from the poh port 11-10 dl_source set to ? 01 ? to insert the data link field (k4/z7 bit 8) from the poh port 0x1a806+4(decimal)*channel 1-0 j2_source set to ? 01 ? to insert the j2 byte from the poh port 3-2 n2_source set to ? 01 ? to insert the n2/z6 byte from the poh port a11-a9 a8-a2 a1 a0 000 (reserved) timeslot number (range 0..83) 00 v5 01 j2 10n2/z6 11k4/z7 timeslot assigned to low order #klm 0 vt1.5/vt2/vc-11/vc-12 #111 1 vt1.5/vt2/vc-11/vc-12 #112 2 vt1.5/vt2/vc-11/vc-12 #113 3 vt1.5/vc-11 #114 4 vt1.5/vt2/vc-11/vc-12 #121 ... ... 82 vt1.5/vt2/vc-11/vc-12 #373 83 vt1.5/vc-11 #374 - 111 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers low order alarm indication port interface the low order alarm indication port interface transports the remote information (ri) from the low order poh sink/monitor to the poh source/generator. the remote information consists of the rei and (enhanced) rdi values to insert by the poh generator. the low order poh monitor blocks multicast the remote information of all low order channels to the low order poh generator blocks and the receive low order alarm indication port interface. the low order poh generator blocks can select per low order channel if the remote information is taken from the transmit low order alarm indication port interface or the internal remote information provided by the low order poh monitor blocks. each interface consists of a clock, data and start of frame line. a start of frame pulse coincides with the first bit of the low order alarm indication port data frame. each low order alarm indication port data frame consists of 84 timeslots of 16 bits per timeslot: the low order time slots are numbered according to the klm numbering: timeslot = (k-1)*28+(l-1)*4+(m-1) each 16-bit timeslot has a field for the rei and rdi. a valid flag indicates if the value in a field is valid and needs to be processed. invalid values are ignored. frame x x+1 timeslot 0 1 ... 83 ... bit number 15 14 ... 1 0 15 14 ... 1 0 ... 15 14 ... 1 0 ... timeslot assigned to low order #klm 0 vt1.5/vt2/vc-11/vc-12 #111 1 vt1.5/vt2/vc-11/vc-12 #112 2 vt1.5/vt2/vc-11/vc-12 #113 3 vt1.5/vc-11 #114 4 vt1.5/vt2/vc-11/vc-12 #121 ... ... 82 vt1.5/vt2/vc-11/vc-12 #373 83 vt1.5/vc-11 #374 bit number name description 15 rei-valid rei value in bit 14 is valid. 14 rei rei value 13 rdi-valid rdi values in bits 12..10 are valid 12 rdi-s enhanced rdi server failure, contributes to single bit rdi 11 rdi-c enhanced rdi connectivity failure, contributes to single bit rdi 10 rdi-p enhanced rdi path failure 9..4 reserved 3..0 crc-4 crc-4 over bits 15..4 - 112 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers sonet/sdh protection switching recovery time a typical, ethermap-3 plus standards-compliant adm in unidirectional path switched ring (upsr) mode sends a tributary payload in both directions around the ring and receives from one of the two paths. if errors or a failure occur on the chosen receive path, the adm switches over to the other path to resume communication. the sonet/sdh required restoration time of each ho or lo path from the detection of a failure is 50 milliseconds or less. the detection time requirement varies depending on the line rate and the bit error rate. sonet/sdh paths are assumed to be restored when the poh bytes and pointers have no detected errors (e.g., lop or ais). h4 and k4 multiframe alignment and sequence numbers are not included. upsr switching times are typically shorter due to the fact that the switch decisions are made only at the receiving adm(s). for blsr, adm to adm communication via the k1/k2 bytes is required to perform the switch. ta b l e 3 below lists the functions and the times required in presenting a new signal to one or more paths used to carry an ethernet payload in the ethermap-3 plus . table 3: sonet/sdh protection switching recovery time the ethermap-3 plus adds very little delay to ho paths in vcat mode and will achieve the desired 50 millisecond switchover times in upsr applications where differential path delays are small. lo vcat applications will experience more unavailability time during a switchover, but no more than the standards dictate. the main reason for additional delays is that both detection and restoration may only be observable via the k4 bytes in each lo path, for example, a single lo path with a vcat group carried by a high order path experiencing a signal degrade. only a new k4 multiframe sequence would be presented to the ethermap-3 plus. shorter unavailability times are possible with vcat and lcas, but the target adms must support unprotected or non-preemptable unprotected traffic (nut) and the end customers must accept reduced bandwidth during failures. mode total delay see note: ho wo/vcat sonet/sdh + 0.5 msec. 1 lo wo/vcat sonet/sdh + 2.0 msec. 1 ho w/vcat sonet/sdh + pda + 12 msec. 1,2 lo w/vcat sonet/sdh + pda + 72 msec. 1,2,3 notes: 1. sonet/sdh = basic sonet/sdh line and individual paths restoration time after a protection switch (i.e., which does not include the individual paths differential delay compensation time within a virtual concatenation group). 2. pda = maximum path difference. 3. the time listed assumes that the new path is initiated as the result of a selection made on-chip (e.g., changing to an idle lo path or a microprocessor triggered reset of a path). if the path is switched external to the device and the new path only exhibits possibly an ndf and new k4 (e.g., due to a signal degrade condition), the standards require a k4 detection of the failure which can add up to 70 msec or more to the listed value. - 113 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers virtual concatenation and lcas the ethermap-3 plus device takes a contiguous piece of ethernet bandwidth and breaks it up into a number of individual spe/vc which travel independently through the sonet/sdh network and are reassembled at their destination back into the contiguous piece of ethernet bandwidth. the ethermap-3 plus also performs the converse, by taking the spe/vc that it has received from a sending device and reassembling it back into a contiguous piece of ethernet bandwidth. two tremendous advantages are immediately obvious: 1) since the ethernet traffic is traveling through the network in a standard size spe/vc only the equipment at the end points needs to be changed. 2) granularity of bandwidth used can be variable and in increments of the spe/vc that is used. this is useful for the transport of payloads, such as ethernet, which do not efficiently fit into one of the standard spe/vc. the ethermap-3 plus device also supports lcas (link capacity adjustment scheme). this is a mechanism where the allocated bandwidth for an ethernet link can be dynamically reconfigured without causing any hits on to the existing traffic flow. the sections below describe in greater detail how the ethermap-3 plus performs virtual concatenation. low order virtual concatenation without lcas ethernet traffic is transported in low order vt1.5-xv-spe/vc-11-xv or vt2-xv-spe/vc-12-xv virtual concatenation groups as follows: figure 42. vt1.5-xv-spe structure v5 j2 1 1 26 vc-11/vt1.5 spe #x 1 1 4 x x x 25 v5 j2 n2 k4 1 4 1 c-11-xc/vt1.5-xc spe vc-11/vt1.5 spe #1 500 s 500 s vc-11-xv/ payload capacity x x 34 c-12-xc/vt2-xc spe payload capacity vc-12/vt2 spe #x vc-12/vt2 spe #1 vt1.5-xv spe vc-12-xv/ vt2-xv spe 35 - 114 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers the payload capacity consists of ethernet traffic which has been encapsulated in one of four ways: gfp, laps, lapf or ppp. more will be said about these encapsulation methods in following sections. in sdh mode ethernet traffic can also be transported in vc-3-xv as shown in figure 49 . note, a vc-3 is considered high order if carried in an au-3, and low order if carried in a tug-3; in this case the vc-3s are mapped to a tug-3 as shown in figure 44 . also note that the ethermap-3 plus has the capability to map the vc-3s to either a tug-3 or au-3. once the ethermap-3 plus has broken up the ethernet payload into vt2-spe/vc-12 or vt1.5-spe/vc-11 they are then multiplexed into their respective sdh or sonet frame structures as shown below. figure 43. lo sdh multiplexing structure 1 supported by the ethermap-3 plus figure 44. lo sdh multiplexing structure 3 supported by the ethermap-3 plus figure 45. lo sdh multiplexing structure 2 supported by the ethermap-3 plus tug-3 tug-2 tu-12 vt2 sts-3c spe vc-4 vt2 spe vc-12 x3 x3 x7 vt group sonet sdh multiplexing aligning pointer processing mapping vt2 payload c-12 aug-1 au-4 sts-3c x1 sts-3 tug-3 tu-3 sts-3c spe vc-4 vc-3 sts-1 payload c-3 x3 x1 sonet sdh multiplexing aligning pointer processing mapping au-4 sts-3c x1 aug-1 sts-3 tug-2 tu-12 vt2 vt2 spe vc-12 vt2 payload c-12 x7 x3 x7 vt group sts-1 spe vc-3 sonet sdh multiplexing aligning pointer processing mapping x3 au-3 sts-1 aug-1 sts-3 - 115 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 46. lo sdh multiplexing structure 4 supported by the ethermap-3 plus figure 47. lo sonet multiplexing structure supported by the ethermap-3 plus low order virtual concatenation with lcas when using low order virtual concatenation in sonet/sdh mode, every low order virtual concatenation group (vcg) can be independently optionally configured to operate in lcas mode. note, low order virtual concatenation can be used without lcas, but lcas requires virtual concatenation. the low order virtual concatenation lcas control packet definition and format is specified in the itu-t g.707/y.1322 standard. the lcas protocol is specified in the itu-t g.7042/y.1305 standard. the lcas control packet is resident in the k4/z7 [bit 2] poh byte. during initialization/normal operation, the ethermap-3 plus device provides support for management and re- allocation of member resources between lcas and non-lcas modes for use by multiple low order vcgs. in addition, general add and remove operations are supported using single high level messages. tug-3 tug-2 sts-3c spe vc-4 x4 x3 x7 vt group sonet sdh multiplexing aligning pointer processing mapping au-4 sts-3c x1 aug-1 sts-3 vt1.5 spe vc-11 vt1.5 payload c-11 tu-11 vt1.5 tug-2 au-3 sts-1 vt1.5 spe vc-11 vt1.5 payload c-11 x3 x7 x4 vt group sts-1 spe vc-3 tu-11 vt1.5 sonet sdh multiplexing aligning pointer processing mapping aug-1 sts-3 - 116 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers in the transmit direction, for every member of a low order vcg operating in lcas mode, the ethermap-3 plus device provides for individual source side lcas hardware based state machines as per the itu-t g.7042/y.1305. the following additional functions are also supported: prbs generation for the group identification (gid) bit field. crc-3 generation. lcas sequence indicator (sq) field generation. lcas control (ctrl) field generation. inter-member messages during add/remove operations. for each transmit low order vcg in lcas mode, selection of a high/low order member, in the receive direc- tion, that is carrying the member status (mst) and re-sequence acknowledge (rs-ack) information. termination of mst and rs-ack information from respective sink side lcas state machine. configurable low order per-member and per-vcg time-out counters for detection of failure during add and remove operations. alarm generation to indicate lcas source side state machine status. in the receive direction, for every member of a low order vcg operating in lcas mode, the ethermap-3 plus device provides for individual sink side lcas hardware based state machines as per the itu-t g.7042/y.1305. the following additional functions are also supported: group identification (gid) field mismatch detection. crc-3 check. lcas sequence indicator (sq) field processing. lcas control (ctrl) field processing. generation of mst and rs-ack status information. detection and processing of trail signal fail (tsf) conditions. for each receive low order vcg in lcas mode, selection of a transmit side high/low order vcg that is used to transport the member status (mst) and re-sequence acknowledge (rs-ack) information. alarm generation to indicate lcas sink side state machine status. high order virtual concatenation without lcas in sonet mode ethernet traffic is transported in sts-1-xv-spe or in a sts-3c-spe. the sts-1-xv-spe structure is shown in the figure below. the sts-1-xv-spe payload capacity or the sts-3c-spe data consists of ethernet traffic which has been encapsulated in one of four ways: gfp, laps, lapf or ppp. - 117 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 48. high order sts-1-xv-spe/vc-3-xv structure j1 b3 1 1 87 1 1 9 x x x 84 1 c-3-xc/sts-1-xc spe 125 s 125 s vc-3-xv/ 125 s sts-1-xv spe payload capacity vc-3/sts-1 spe #x j1 b3 c2 g1 1 9 n1 k3 f2 f3 h4 vc-3/sts-1 spe #1 30 59 fixed stuff - 118 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers in sdh mode ethernet traffic is transported in vc-3-xv or in vc-4. just like for the sts-1-xv-spe payload capacity the payload capacity for the vc-3-xv and vc-4 consists of ethernet traffic which has been encapsulated in one of four ways: gfp, laps, lapf or ppp. the vc-3-xv structure is shown below. note, a vc-3 is considered high order as long as it is not carried in a tug-3. figure 49. low order vc-3-xv structure once the ethermap-3 plus has broken up the ethernet payload into vc-3 or sts-1-spe they are then multiplexed into their respective sdh or sonet frame structures as shown below. notice that for the vc-3 structure that no stuff columns exist. however, when inserted into the au-3, stuff columns are added so that the vc-3 ends up resembling an sts-1-spe. j1 b3 1 1 85 vc-3 #x 1 1 9 x x x 84 j1 b3 c2 g1 1 9 1 c-3-xc vc-3 #1 125 s 125 s vc-3-xv n1 k3 f2 f3 h4 125 s payload capacity - 119 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 50. ho sonet/sdh multiplexing structure supported by the ethermap-3 plus high order virtual concatenation with lcas when using high order virtual concatenation in sonet/sdh mode, every high order virtual concatenation group (vcg) can be independently optionally configured to operate in lcas mode. note, high order virtual concatenation can be used without lcas, but lcas requires virtual concatenation. the high order virtual concatenation lcas control packet definition and format is specified in the itu-t g.707/y.1322 standard. the lcas protocol is specified in the itu-t g.7042/y.1305 standard. the lcas control packet is resident in the h4 poh byte. during initialization/normal operation, the ethermap-3 plus device provides support for management and re- allocation of member resources between lcas and non-lcas modes for use by multiple high order vcgs. in addition, general add and remove operations are supported using single high level messages. in the transmit direction, for every member of a high order vcg operating in lcas mode, the ethermap-3 plus device provides for individual source side lcas hardware based state machines as per the itu-t g.7042/y.1305. the following additional functions are also supported: prbs generation for the group identification (gid) bit field. crc-8 generation. lcas sequence indicator (sq) field generation. lcas control (ctrl) field generation. inter-member messages during add/remove operations. for each transmit high order vcg in lcas mode, selection of a high/low order member, in the receive direction, that is carrying the member status (mst) and re-sequence acknowledge (rs-ack) information. termination of mst and rs-ack information from respective sink side lcas state machine. configurable high order per-member and per-vcg time-out counters for detection of failure during add and remove operations. alarm generation to indicate lcas source side state machine status. in the receive direction, for every member of a high order vcg operating in lcas mode, the ethermap-3 plus device provides for individual sink side lcas hardware based state machines as per the itu-t g.7042/y.1305. the following additional functions are also supported: group identification (gid) field mismatch detection. crc-8 check. au-3 sts-1 sts-1 payload c-3 sts-1 spe vc-3 sonet sdh multiplexing aligning pointer processing mapping x3 aug-1 sts-3 - 120 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers lcas sequence indicator (sq) field processing. lcas control (ctrl) field processing. generation of mst and rs-ack status information. detection and processing of trail signal fail (tsf) conditions. for each receive high order vcg in lcas mode, selection of a transmit side high/low order vcg that is used to transport the member status (mst) and re-sequence acknowledge (rs-ack) information. alarm generation to indicate lcas sink side state machine status. configuration for virtual concatenation and lcas general the virtual concatenation of the 8 ethernet lines within 8 vcgs can be performed with the ethermap-3 plus . for both transmit and receive, it is possible to configure the design in low order, high order, mixed high order/low order, with lcas or without lcas, on a per vcg basis. the following paragraphs explain how to configure the virtual tributaries and how to extract status information from the device. note: a coherency is necessary between the configuration of the virtual concatenation part of the design and the mapper configuration (for example: high order virtual concatenation with high order mapping). this applies also to any unused sonet/sdh container. low order configurations use the - 121 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers it is important to note that depending on add/drop timing mode, some mappings restrictions will apply. in drop timing mode, because of unalignment of sts-1/tug-3, following mappings become impossible: sts-3 / sts-1 spe, sts-1-xv where x > 1 sts-3 / sts-1 / vt1.5 spe, vt1.5-xv where vt1.5s are spread over several sts-1s sts-3 / sts-1 / vt2 spe, vt2-xv where vt-2s are spread over several sts-1s stm-1 / aug-1 / au-4 / vc-4 / tug-3 / tug-2 / tu-11 / vc-11, vc-11-xv where vc-11s are spread over several tug-3s stm-1 / aug-1 / au-3 / vc-3, vc-3-xv where x > 1 stm-1 / aug-1 / au-3 / vc-3 / tug-2 / tu-11 / vc-11, vc-11-xv where vc-11s are spread over several au-3s stm-1 / aug-1 / au-3 / vc-3 / tug-2 / tu-12 / vc-12, vc-12-xv where vc-12s are spread over several au-3s configuring transmit vcat (ethernet to sonet/sdh) the transmit side configuration/status is controlled by the following registers: csntsdh which indicates the sonet or sdh configuration. a single register is used for all the vcgs in transmit and receive direction. default value is 0 (=sonet). configuration of the 3 high order virtual tributaries: cthovc4(6) indicates if there is no virtual concatenation with mapping on vc-4/sts-3c (when this bit is set to 1) or if the virtual concatenation exists (default value = 0) cthovc3_1(5:4) indicates if the sts-1#1 is configured in low order (vt1.5/vt2 or vc-11/vc-12 (tug-3)) with the value 00 (default), configured in low order in vc-12 (au-3) in sdh only with the value 01 and in high order with the value 11. cthovc3_2(3:2) indicates if the sts-1#2 is configured in low order (vt1.5/vt2 or vc-11/vc-12 (tug-3)) with the value 00 (default), configured in low order in vc-12 (au-3) in sdh only with the value 01 and in high order with the value 11. cthovc3_3(1:0) indicates if the sts-1#3 is configured in low order (vt1.5/vt2 or vc-11/vc-12 (tug-3)) with the value 00 (default), configured in low order in vc-12 (au-3) in sdh only with the value 01 and in high order with the value 11. configuration of each vcg (lcas/non-lcas, itu/ansi, non standard itu/ansi): ctmst_vt(9:3) is used only in lcas mode to select the tributary which carries mst and rs_ack. made by concatenation of au3 # (bits 9-8), tug2 # (bits 7-5) and tu1 # (bits 4-3). default value is 0. ctlcas(2) is used to indicate the configuration of the vcg (lcas or non lcas). default value is 0 means non lcas. cthovcg(1:0) indicate if the vcg is used in low order itu/ansi (00, default value), in low order non standard itu/ansi (01 value) or in high order itu/ansi (11 value). ctvc4mac(7:0): choice of the mac which will be mapped into vc-4/sts-3c. ex: 00000100 means that the mac #2 is mapped into vc-4/sts-3c. 00000001 means that the mac#0 is mapped into vc-4/sts-3c. configuration of each low order virtual tributary: ctlosq (10:5)_klm: sequence indicator of the virtual tributary. default is 0x3f. ctlovcg (4:2)_klm: number of assigned vcg. default is 0. ctlopool (1:0)_klm: assignation to global/non-lcas/lcas_idle/lcas_active pool. status of each low order virtual tributary: stlosq (14:9)_klm: current sequence indicator of the virtual tributary. default is 0x3f. stloctrl (8:5)_klm: command/state field in lcas/non lcas. default value is 0 (non lcas). 0001 means add, 0010 means norm, 0011 means eos, 0101 means idle and 1111 means dnu in lcas mode. - 122 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers stlovcg (4:2)_klm: number of assigned vcg. default is 0. stlopool (1:0)_klm: assignation to global/non-lcas/lcas_idle/lcas_active pool. configuration of each sts-1/vc-3 used in high order virtual concatenation: cthopool_[1..3] (1:0): assignation to global/non-lcas/lcas_idle/lcas_active pool. cthovcg_[1..3] (4:2): number of assigned vcg. default is 0. cthosq[1..3] (12:5): sequence indicator value of each sts-1/vc-3 in case of high order virtual concatenation. status of each sts-1/vc-3 used in high order virtual concatenation: sthopool_[1..3] (1:0): assignation to global/non-lcas/lcas_idle/lcas_active pool. sthovcg_[1..3] (4:2): number of assigned vcg. default is 0. sthoctrl_[1..3] (8:5): command/state field in lcas/non lcas. default value is 0 (non lcas). 0001 means add, 0010 means norm, 0011 means eos, 0101 means idle and 1111 means dnu in lcas mode. sthosq_[1..3](7:0): configuration status of sequence indicator value of each sts-1/vc-3 in case of high order virtual concatenation. configuring receive vcat (sonet/sdh to ethernet) the receive side configuration/status is controlled by the following registers: csntsdh which indicates the sonet or sdh configuration. common with transmit virtual concatenation. configuration of the 3 high order virtual tributaries: crhovc4(6) indicates if there is no virtual concatenation i.e., with mapping on vc-4/sts-3c (when this bit is set to 1) or if the virtual concatenation exists (default value = 0) crhovc3_1(5:4) indicates if the sts-1#1 is configured in low order (vt1.5/vt2 or vc-11/vc- 12 (tug-3)) with the value 00 (default), configured in low order in vc-12 (au-3) in sdh only with the value 01 and in high order with the value 11. crhovc3_2(3:2) indicates if the sts-1#2 is configured in low order (vt1.5/vt2 or vc-11/vc- 12 (tug-3)) with the value 00 (default), configured in low order in vc-12 (au-3) in sdh only with the value 01 and in high order with the value 11. crhovc3_3(1:0) indicates if the sts-1#3 is configured in low order (vt1.5/vt2 or vc-11/vc- 12 (tug-3)) with the value 00 (default), configured in low order in vc-12 (au-3) in sdh only with the value 01 and in high order with the value 11. configuration of each vcg (lcas/non-lcas, itu/ansi, non standard itu/ansi): tx_vcg_x(5:3) is used only in lcas mode to select the transmit vcg which carries mst and rs_ack generated by lcas sink process. default value is 0 crlcas_x(2) is used to indicate the configuration of the vcg (lcas or non lcas). default value is 0 means non lcas. crvcg_x(1:0) indicate if the vcg is used in low order itu/ansi (00, default value), in low order non standard itu/ansi (01 value) or in high order itu/ansi (11 value). crvc4mac(7:0): choice of the mac which is mapped into vc-4/sts-3c. ex: 00000100 means that the mac #2 is mapped into vc-4/sts-3c. 00000001 means that the mac#0 is mapped into vc- 4/sts-3c. configuration of each low order virtual tributary: crlofmstfail(11)_klm: forces mst to fail condition when set to 1 otherwise normal generation of mst. crlosq (10:5)_klm: expected sequence indicator of the virtual tributary. default is 0x3f. crlovcg (4:2)_klm: number of assigned vcg. default is 0. crlopool (1:0)_klm: assignation global/non-lcas/lcas_idle/lcas_active pool. - 123 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers status of each low order virtual tributary: srlosq(14:9)_klm: extracted sequence indicator of the virtual tributary. default is 0x3f. srloctrl (8:5)_klm]: extracted command/state field in lcas/non lcas. default value is 0 (non lcas). 0001 means add, 0010 means norm, 0011 means eos, 0101 means idle and 1111 means dnu in lcas mode. srlovcg (4:2)_klm: number of assigned vcg. default is 0. srlopool (1:0)_klm: assignation to global/non-lcas/lcas_idle/lcas_active pool. frame count of each low order virtual tributary: srlomfi_x(4:0)_klm: extracted mfi value. srlofc_x (9:5)_klm: extracted frame count value. configuration of each sts-1/vc-3 used in high order virtual concatenation: crhopool_[1..3] (1:0): assignation to global/non-lcas/lcas_idle/lcas_active pool. crhovcg_[1..3] (4:2): number of assigned vcg. default is 0. crhosq_[1..3] (10:5): expected sequence indicator of the virtual tributary. default is 0xff. crhofmstfail(11)_[1..3][1..7][1..4]: forcing mst to fail condition when set to 1 otherwise normal generation of mst. status of each sts-1/vc-3 used in high order virtual concatenation: srhopool_[1..3] (1:0): assignation to global/non-lcas/lcas_idle/lcas_active pool. srhovcg_[1..3] (4:2): number of assigned vcg. default is 0. srhoctrl_[1..3] (8:5): extracted command/state field in lcas/non lcas. default value is 0 (non lcas). 0001 means add, 0010 means norm, 0011 means eos, 0101 means idle and 1111 means dnu in lcas mode. frame count status of each sts-1/vc-3 used in high order virtual concatenation: srhomfi1_x(3:0)_[1..3]: extracted mfi1 value. srhomfi2_x (11:4)_[1..3]: extracted mfi2 value. srhosq_[1..3](7:0): status of the extracted sequence indicator value of each sts-1/vc-3 in case of high order virtual concatenation. lcas-specific configuration - transmit ctlok4vcen_klm: enables the transmission of the k4 bit 2 when set to 1 for each low order virtual tributary (default = 0). ctlocrcerr_klm: initialization of the shift register for the crc calculation for each low order virtual tributary. a zero initializes the register to 0 for normal operation. a one initializes the register to 1 and causes crc errors to be generated. cthoh4vcen_[1..3]: enables the transmission of the h4 byte when set to 1 for each high order virtual tributary (default = 0). cthocrcerr_[1..3]: initialization of the shift register for the crc calculation in high order only for the sts-1/vc-3. a zero initializes the register to 0 for normal operation. a one initializes the register to 1 and causes crc errors to be generated. ctlolcprd1_klm(9:0): terminal count of timeout counter (unit = ms) when adding the member on low order. use for detection of mst_ok after an add command. ctholcprd1_[1..3](9:0): terminal count of timeout counter (unit = ms) when adding the member in high order. use for detection of mst_ok after an add command. ctlcprd2_[1..8](9:0): terminal count of timeout counter (unit = ms) when adding the member in the vcg. use for detection of rs_ack after an add command. ctlcprd3_[1..8](9:0): terminal count of timeout counter (unit = ms) when removing the member in the vcg. use for detection of rs_ack after a remove command. - 124 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers assigning unused vcgs (when at least one vcg is lcas) for mst extraction by the source: unused vcgs cannot point to the same member used for extraction by the used vcg(s). for example in a low order case, if vt/vc #111 is used for extraction, then the extraction controls for the remaining 7 vcgs must be changed, since they default to pointing to vt/vc #111. the following is an example of how to configure the other vcg's if only vcg0 is used for extraction. 0x1ec88 0300 - vcg1 (mac 1) -> unused, no mst/rs_ack extraction 0x1ec8a 0300 - vcg2 (mac 2) -> unused, no mst/rs_ack extraction 0x1ec8c 0300 - vcg3 (mac 3) -> unused, no mst/rs_ack extraction 0x1ec8e 0300 - vcg4 (mac 4) -> unused, no mst/rs_ack extraction 0x1ec90 0300 - vcg5 (mac 5) -> unused, no mst/rs_ack extraction 0x1ec92 0300 - vcg6 (mac 6) -> unused, no mst/rs_ack extraction 0x1ec94 0300 - vcg7 (mac 7) -> unused, no mst/rs_ack extraction the value 0x0300 represents an invalid member number since it points to au3/sts1 #4, that is not a valid tributary index. for mst generation by the sink: unused vcgs cannot point to the same vcg used for mst generation by the used vcg(s). for example, if vcg0 is used for generation, then the generation controls for the remaining 7 vcgs must be changed, since they default to pointing to vcg0. the following is an example of how to configure the other vcg's if only vcg0 is used for generation. 0x1f00a 0008 - mst and rs_ack inserted into tx vcg1 for receive vcg1 0x1f00c 0010 - mst and rs_ack inserted into tx vcg2 for receive vcg2 0x1f00e 0018 - mst and rs_ack inserted into tx vcg3 for receive vcg3 0x1f010 0020 - mst and rs_ack inserted into tx vcg4 for receive vcg4 0x1f012 0028 - mst and rs_ack inserted into tx vcg5 for receive vcg5 0x1f014 0030 - mst and rs_ack inserted into tx vcg6 for receive vcg6 0x1f016 0038 - mst and rs_ack inserted into tx vcg7 for receive vcg7 the values shown point to the same vcg number as the received vcg number. dynamic mapping and virtual concatenation changes vcg tributary assignments (adding and removing members) the following procedures must be followed when adding or removing containers to/from an active vcg. for non-lcas re-assignment, the source/sink, add/remove procedures can be followed in any order. for reassignment involving lcas vcgs, the lcas protocol must be respected and will limit the order in which events occur. multiple tributary reassignment is described in each procedure. single tributary reassignment is performed using the same steps. for initial configuration, the add procedures can be followed. the procedures below refer to tx and rx mac reset. these functions are accomplished by setting both the reset tx/rx function bit (bit 0/1) and the reset tx/rx mac control bit (bit 2/3) in configuration register 0x00002. please note that all mac registers must be accessed as 16-bit register pairs, even when only a 16- bit register access is needed. registers 0x00000 and 0x00002 are a pair. for writes, the 16 msbs (address bit 0 is high) must be written first. for reads, the 16 lsbs (address bit 0 is low) must be read first. note: z = h (high order) or l (low order) - 125 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers case 1: re-assign multiple vc-11/vc-12 or vc-3/tug-3 from vcgx to vcgy, non-lcas mode: below are listed four stand-alone procedures that can be executed in any order. when moving a tributary between vcgs, the order below will minimize resynchronization time. remove procedure - transmit tx channel x reset on (rx macx reset first, then vcgx reset) change ctzopool to global for all containers to be removed from vcgx change ctzosq to resequence the remaining members of vcgx delay if needed (members must remain in global pool for a minimum of 16 ms lo (2 ms ho) before moving to non-lcas pool) tx channel x reset off (vcgx reset first, then rx macx reset) remove procedure - receive rx channel x reset on (vcgx reset first, then tx macx reset) change crzopool to global for all containers to be removed from vcgx change crzosq to resequence the remaining members of vcgx rx channel x reset off (tx macx reset first, then vcgx reset) add procedure - receive rx channel y reset on (vcgy reset first, then tx macy reset) change crzovcg to vcgy for all containers to be added into vcgy change crzopool to non-lcas for all containers to be added into vcgy rx channel y reset off (tx macy reset first, then vcgy reset) add procedure - transmit tx channel y reset on (rx macy reset first, then vcgy reset) change ctzovcg to vcgy for all containers to be added into vcgy change ctzopool to non-lcas for all containers to be added into vcgy tx channel y reset off (vcgy reset first, then rx macy reset) case 2: re-assign multiple vc-11/vc-12 or vc-3/tug-3 from vcgx to vcgy, lcas mode: in lcas mode, a remove or add procedure involves steps at both the sink and the source. when moving a tributary between vcgs, the tributary must be removed first and then added. remove procedure step 1 - remove at the source for first tributary: change ctzopool to lcas idle (wait for alarm rem or prd3) change ctzopool to global change cthoh4vcen_[1..3] or ctlok4vcen_klm to disable then move on to the next tributary delay if needed (members must remain in global pool for a minimum of 16 ms lo (2 ms ho) before moving to lcas idle pool) step 2 - remove at the sink for first tributary: change crzopool to lcas idle (wait for arlcasrem) change crzopool to global then move on to the next tributary - 126 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers add procedure step 1 - add at the sink for first tributary: change crzovcg to vcgy change crzopool to lcas idle change crzopool to lcas active read arlcasadded then move on to the next tributary step 2 - add at the source for first tributary: change ctzovcg to vcgy change cthoh4vcen_[1..3] or ctlok4vcen_klm to enable change ctzopool to lcas idle delay if needed (members must remain in idle pool for a minimum of 16 ms lo (2 ms ho) before moving to lcas active pool) change ctzopool to lcas active (check prd1, prd2, atlcasadded) then move on to the next tributary step 3 - (optional) verify at the sink read arlcasadded alarm (allows the add procedure to be verified at the sink end, and also clears the alarm for its next use.) case 3: re-assign multiple vc-11/vc-12 or vc-3/tug-3 from vcgx (lcas) to vcgy (non-lcas): use the case 2 remove procedure and the case 1 add procedure, completing the removes before per- forming any adds. alternatively, the lcas remove and non-lcas add can be completed at the source before any operations are done at the sink. case 4: re-assign multiple vc-11/vc-12 or vc-3/tug-3 from vcgx (non-lcas) to vcgy (lcas): use the case 1 remove procedure (rx and tx in any order), then follow the case 2 add procedure. changing vcg encapsulation/decapsulation mode the procedures for changing encapsulation mode are covered in the encapsulation/decapsulation section beginning on page 139 . changing vcg sonet/sdh structure this section deals with changing the fundamental sonet/sdh structure of a vcg. when changing a vcg from high-order mode to low-order mode (or vice-versa), or when changing to/from sts-3c/vc-4 mode, the following procedures must be followed. the vcg tributary reassignment procedure defined above is referenced by this procedure and should be maintained except where noted below. for non-lcas reconfiguration, the transmitter and receiver reconfiguration procedures below can be followed in either order. for reconfiguration involving lcas vcgs, the lcas protocol must be respected and will limit the order in which events occur. as such, for any reconfiguration involving addition of lcas vcgs in which only non-lcas vcgs are removed, the receiver reconfiguration procedure below is performed first. for any reconfiguration in which lcas vcgs are removed and are either added or not added, the transmitter reconfiguration below is performed first. however, when lcas vcgs are added, no member can be added to the lcas active pool at the transmitter until after the receiver reconfiguration procedure is completed. - 127 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers transmitter reconfiguration changing high-order/low-order assignment (ho->lo or lo->ho) 1) empty the changing vcgs by moving their containers to the global pool. this is done by following the applicable tributary assignment procedure (non-lcas or lcas) starting on page page 124 . for non-lcas, the soft resets of the tx vcgs and rx macs being added are not released. 2) if not done in step 1, apply soft reset to any tx vcg and rx mac to be used in the new configuration 3) freeze all vcgs that are to be used (ctfcrstx in ta b l e 6 5 on page 271 ) 4) reconfigure the mapper for the new sonet/sdh structure 5) reconfigure the vcgs (ctvcg_x, ctlcas_x, ctmst_vt_x in ta b l e 6 5 on page 271 ) 6) reconfigure the sts-1/vc-3s (cthovc3_n in ta b l e 6 5 on page 270 ) 7) allocate containers to the vcgs using the applicable tributary assignment procedure (non-lcas or lcas) starting on page 124 . for lcas vcgs, first release the tx vcg and rx mac resets. 8) release the ctfcrst bits for the changed vcgs note: for the following configurations, step 4 above is performed after step 6: lll => llh; lhl => lhh; llh => lhh; lll => hlh; hll => hlh; lll => llh; hll =>llh; lhl => llh, where l = low order and h = high order and, for example, hll => llh indicates that sts1#1/vc3#1 is changing from high order to low order and sts1#3/vc3#3 is chang- ing from low order to high order. changing from sts-3c/vc-4 1) apply soft reset to the tx vcg and rx mac that is assigned to the sts-3c/vc-4 2) freeze all vcgs to be configured (ctfcrstx in ta b l e 6 5 on page 271 ) 3) reconfigure the mapper block for the new sonet/sdh structure 4) reconfigure the vcgs (ctvcg_x, ctlcas_x, ctmst_vt_x in ta b l e 6 5 on page 271 ) 5) reconfigure the sts-1/vc-3s (cthovc3_n in ta b l e 6 5 on page 270 ) 6) configure for non sts-3c/vc-4 mode (cthovc4 in ta b l e 6 5 on page 270 ) 7) remove sts-3c/vc-4 ethernet port mapping (ctvc4mac in table 65 on page 270 ) 8) allocate containers to the vcgs using the applicable tributary assignment procedure (non-lcas or lcas) starting on page 124 . for lcas vcgs, first release the tx vcg and rx mac resets. 9) release the ctfcrst bits for the newly configured vcgs 10) if not released during step 8, release the soft reset of the tx vcg and rx mac that was formerly assigned to the sts-3c/vc-4 changing to sts-3c/vc-4 1) empty all vcgs by moving their containers to the global pool. this is done by following the applicable tributary assignment procedure (non-lcas or lcas) starting on page 124 . for non- lcas, the rx mac soft reset is not releasedfor the ethernet port that will be mapped to the sts- 3c/vc-4. 2) if not done in step 1, apply rx mac soft reset to the ethernet port that will be mapped to the sts-3c/vc-4 3) apply tx soft reset to all of the emptied vcgs and the vcg that will be mapped to the sts-3c/vc-4. 4) freeze all emptied vcgs (ctfcrst in ta b l e 6 5 on page 271 ) 5) reconfigure the mapper block for the new sonet/sdh structure 6) add the sts-3c/vc-4 ethernet port mapping (ctvc4mac in table 65 on page 270 ) 7) configure for sts-3c/vc-4 mode (cthovc4 in ta b l e 6 5 on page 270 ) 8) release the ctfcrst bits of the emptied vcgs and the new sts-3c/vc-4 vcg 9) release the rx mac soft reset of the ethernet port that is now mapped to the sts-3c/vc-4 10) release tx soft reset of all emptied vcgs and the new sts-3c/vc-4 vcg - 128 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers receiver reconfiguration changing high-order/low-order assignment (ho->lo or lo->ho) 1) empty the changing vcgs by moving their containers to the global pool. this is done by following the applicable tributary assignment procedure (non-lcas or lcas) starting on page 124 . for non-lcas, the soft reset of the rx vcg and tx mac being added are not released. 2) if not done in step 1, apply soft reset to any rx vcg and tx mac to be used in the new configuration 2) reconfigure the vcgs (crvcg_x, crlcas_x, tx_vcg_x in ta b l e 7 6 on page 284 ) 3) reconfigure the sts-1/vc-3s (crhovc3_n in table 76 on page 283 ) 4) reconfigure the demapper block - when reconfiguring from high to low order, there must be at least 1 ms of delay between enable of the lo pointer processor (0x1c620/2/4->0x0000) and enable of the lo poh monitor (0x148e0/2/4->0x0000) 5) allocate containers to the vcgs using the applicable tributary assignment procedure (non-lcas or lcas) starting on page 124 . for lcas vcgs, first release the rx vcg and tx mac resets. changing from sts-3c/vc-4 1) stop data flow from the demapper (set addresses 0x148e0, 0x148e2 and 0x148e4 to 0x0) 2) apply soft reset to all rx vcgs 3) apply tx mac soft reset to all eight macs 4) configure the 3 sts-1/vc-3s (crhovc3_n in table 76 on page 283 ). do not exit sts-3c/vc-4 mode. 5) release rx soft reset of all eight vcgs 6) configure for non sts-3c/vc-4 mode (crhovc4 in table 76 on page 283 ) 7) remove the sts-3c/vc-4 ethernet port mapping (crvc4mac in ta b l e 7 6 on page 284 ) 8) apply rx soft reset to all eight vcgs 9) reconfigure the vcgs (crvcg_x, crlcas_x, tx_vcg_x in ta b l e 7 6 on page 284 ) 10) reconfigure the demapper block for the new sonet/sdh structure 11) for ho sts-1/vc-3s only: allow data flow from the demapper (set addresses 0x148e0, 0x148e2 and 0x148e4 to 0x1) 12) allocate containers to the vcgs using the applicable tributary assignment procedure (non-lcas or lcas) starting on page 124 . for lcas vcgs, first release the rx vcg and tx mac soft resets. 13) release tx mac soft reset of all macs not released in step 12 14) release rx soft reset of all vcgs not released in step 12 changing to sts-3c/vc4 1) empty all vcgs by moving their containers to the global pool. this is done by following the applicable tributary assignment procedure (non-lcas or lcas) starting on page 124 . for non- lcas only, the tx mac soft reset is not released for the ethernet port that will be mapped to the sts-3c/vc-4. 2) if not done in step 1, apply tx mac soft reset to the ethernet port that will be mapped to the sts-3c/vc-4 3) apply rx soft reset to all eight vcgs 4) release rx soft reset of all eight vcgs 5) add the sts-3c/vc-4 ethernet port mapping (crvc4mac in ta b l e 7 6 on page 284 ) 6) configure for sts-3c/vc-4 mode (crhovc4 in table 76 on page 283 ) 7) reconfigure the demapper block for the new sonet/sdh structure 8) apply rx soft reset to all eight vcgs 9) release the tx mac soft reset of the ethernet port now mapped to the sts-3c/vc-4 10) release the rx soft reset of all eight vcgs - 129 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers differential delay compensation the ethermap-3 plus performs differential delay compensation for the containers included in a given virtual concatenation group. this supports the scenario where the virtually concatenated containers travel different paths in the sonet/sdh network and therefore are received by the ethermap-3 plus with a time offset. the mutliframe indicator field (mfi) is used for differential delay compensation. mfi is located in the h4 byte (for high order virtual concatenation) or in the k4/z7 byte (for low order virtual concatenation). for each virtual concatenation group (vcg_x, x = 0 - 7), two registers are provided. see below. maximum differential delay allowed register rmaxdelvcg_x is used to configure the maximum differential delay value allowed amongst the members of a virtual concatenation group (vcg_x). the maximum value that can be configured for both low order virtual concatenation (lo vcat) and high order virtual concatenation (ho vcat) is 48 ms. low order in lo vcat, only bits (9-7) of rmaxdelvcg_x are used. the value is configured in steps of 16 ms. table 4 shows the values allowed: table 4: configuration of rmaxdelvcg_x in low order vc high order in ho vcat, bits (9-0) of rmaxdelvcg_x are used. the value is configured in steps of 125 s. table 5 shows the values allowed: table 5: configuration of rmaxdelvcg_x in high order vc configuration of rmaxdelvcg_x multiple of 16 ms resulting maximum delay allowed 0x0000 0 x 16 ms 0 ms 0x0080 1 x 16 ms 16 ms 0x0100 2 x 16 ms 32 ms 0x0180 3 x 16 ms 48 ms configuration of rmaxdelvcg_x multiple of 125 s resulting maximum delay allowed 0x0000 0 x 125 s 0 ms 0x0001 1 x 125 s 125 s .... ... .... 0x0180 384 x 125 s48 ms - 130 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers maximum differential delay detected register rdifdelvcg_x reports the maximum differential delay detected among the members of a given virtual concatenation group (vcg_x). the maximum delay that can be detected is 128 ms. low order in lo vcat, bits (3-0) of rdifdelvcg_x represent the maximum differential delay detected among the low order members of a vcg_x. the register has a granularity of 16 ms: a value of 0001 hex represents a delay of 16 ms. the maximum allowed value is 8, corresponding to 128 ms. if the delay is higher than 128 ms, then bit (11) of rdifdelvcg_x is set, indicating ethermap-3 plus is not able to compute such a differential delay, and further, bits (3-0) of rdifdelvcg_x contain invalid information. furthermore, in lo vcat, when the reported differential delay is found to be greater than that configured in the rmaxdelvcg_x register, an alarm, aloloa_x, is generated per vcg_x. high order in ho vcat, bits (10-0) of rdifdelvcg_x represents the maximum differential delay detected among the members of a vcg_x. the register has a granularity of 125 s: a value of 0001 hex represents a delay of 125 s. the maximum allowed value is 1024, corresponding to 128 ms. if the delay is higher than 128 ms, bit (11) of rdifdelvcg_x is set, indicating ethermap-3 plus is not able to compute such a differential delay, and further, bits (10-0) of rdifdelvcg_x contain invalid information. furthermore, in ho vcat, when the reported differential delay is found to be greater than that configured in the rmaxdelvcg_x register, an alarm, aholoa_x, is generated per vcg_x. in both cases (lo vcat and ho vcat), ethermap-3 plus can compute a differential delay up to 128 ms, but it can only compensate a maximum differential delay of 48 ms. - 131 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ethernet support smii and gmii interfaces the ethermap-3 plus supports two types of ethernet line interfaces: smii or gmii. the gmii ethernet line interface is used only when the ethermap-3 plus ethernet line side is configured for 1000 mbps operation. the smii ethernet line interface is used only when the ethermap-3 plus ethernet line side is configured for 10/100 mbps operation. an external signal lead, gmii/smii , provides for selection between either a single gmii ethernet line interface or up to eight independent smii ethernet line interfaces. note, that the gmii ethernet line interface uses the same leads as the smii ethernet line interface and thus these two ethernet line interfaces cannot be used simultaneously. when using the gmii interface, an external signal lead, phy/mac , selects the clock source for the output signal, gtx_clk. this allows for flexible interconnections between ethermap-3 plus and other common components such as ethernet phy or switch devices. figure 51 shows these various interconnection options. ethermap-3 plus supports up to eight independent smii interfaces. all eight smii interfaces use a common global clock and common global sync signal (smii_gclk). an external signal lead, sync_dir, controls the direction of the sync signal on the smii_gsync signal lead. the external lead phy/mac allows the 8 ethernet lines of ethermap-3 plus to be connected to a phy or to a mac. when phy/mac is equal to 1, ethermap-3 plus is connected to a phy and then is ready to accept status information from the phy. when phy/mac is equal to 0, ethermap-3 plus is considered to be connected to a mac and then the 8 ethernet interface need to be configured. ethermap-3 plus supports half duplex and full duplex for 10/100 mbps and only full duplex for 1000 mbps. in addition to the gmii/smii ethernet line interfaces, the ethermap-3 plus also provides support of control and status to and from external phys using a two-wire mii management interface (mdc, mdio) as per ieee 802.3u. this interface can be used with both gmii/smii interfaces. - 132 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 51. ethermap-3 plus to phy or switch interconnection using gmii interface gtx_clk txd(7-0) tx_clk rx_clk rxd(7-0) gtx_clk txd tx_clk rx_clk rxd n/c ethermap-3 plus phy gtx_clk txd(7-0) tx_clk rx_clk rxd(7-0) rx_clk rxd tx_clk txd ethermap-3 plus switch gtx_clk txd(7-0) tx_clk rx_clk rxd(7-0) rx_clk rxd tx_clk txd ethermap-3 plus switch n/c ethermap-3 plus to phy interconnection using gmii interface (i.e., mac-to-phy) gmii/smii =high phy/mac =high gmii/smii =high phy/mac =low ethermap-3 plus to switch interconnection using gmii interface (i.e., mac-to-mac) ethermap-3 plus to switch interconnection using gmii interface (i.e., mac-to-mac) gmii/smii =high phy/mac =high tx_clk is used for gtx_clk tx_clk is used for gtx_clk rx_clk is used for gtx_clk note: in gmii mode, the difference between mac-to-phy and mac-to-mac configuration is given by the different wiring, as can be seen comparing the upper and the lower two configurations in this diagram. 8 8 8 8 8 8 - 133 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ethernet mac blocks the ethermap-3 plus contains eight ethernet macs. each of these macs can support a 10/100/1000 mbit/s operation. however, when ethermap-3 plus is configured for gigabit mode, only the first mac is used for 1000 mbit/s operation. the remaining macs are disabled. when ethermap-3 plus is configured for 10/100 mbit/s mode, all eight macs are enabled and each can be independently configured for 10 or 100 mbit/s operation. the selection between 10/100 or 1000 mbit/s mode is done using the external signal lead gmii/smii and further internal registers to select between 10 or 100 mbit/s mode only. in addition, if the attached phy device auto-negotiates between 10 and 100 mbps, this information is passed to the mac over the smii interface and overrides any internal register setting. link status is available in registers shown in table 16 . in the transmit direction (i.e., towards the ethernet line side), each mac can be configured to apply or not to apply padding and to append or not to append a valid fcs field to the ethernet frames. ethermap-3 plus supports both half duplex mode (csma/cd) and full duplex mode for 10/100 mbit/s and full duplex mode for 1000 mbit/s. pause flow control frame generation is fully configurable and supported (as per ieee 802.3x). following each ethernet frame transmission or abortion, ethermap-3 plus updates the appropriate transmit side rmon statistic counters. the general configuration of the macs is described in tables 18 - 22 (including selection between full or half duplex operation). furthermore table 21 specifies half duplex configuration such as: configuration of collision window, number of maximum transmission attempts following a collision before abortion, abort or transmit of an excessively deferred packet, use of alternate binary exponential back-off rule or to immediately re-transmit a packet following a collision during back pressure, use of 802.3 standard tenth collision or programmable alternate binary exponential back-off truncation. in the receive direction (i.e., from the ethernet line side), each mac scans the preamble looking for the start frame delimiter (sfd). the preamble and sfd are stripped and the remaining ethernet frame is passed on for further processing. in addition, each mac provides the capability to filter ethernet frames that have less than a configured inter-frame gap; to detect broadcast or multicast destination addresses; to check length field against the actual length of the data field portion of the ethernet frame and to check or not the fcs field of the ethernet frame. ethermap-3 plus supports both half duplex mode (csma/cd) and full duplex mode for 10/100 mbit/s and only full duplex mode for 1000 mbit/s. this means that the pause flow control frame detection is fully configurable and supported (as per ieee 802.3x). following each ethernet frame reception, the appropriate receive side rmon statistic counters are updated. tables 24 - 29 are used for configuration and control of the mii management interface. using the control bits of table 24 , the mdc (mii management clock) is derived from the micclk clock by applying a divide factor between 4 and 28. it is also possible to suppress or not the preamble information. to perform a write access, the following steps are followed: configure ? register address ? field (with 0x0 for control register of the phy) of table 26 , configure ? phy address ? field of table 26 , write a data value into the ? mii mgmt control ? field of table 27 , similarly, to perform a read access, the following steps are followed: configure ? register address ? field (with 0x1 for control register of the phy) of table 26 , configure ? read cycle ? field of table 25 , read a data value from the ? mii mgmt status ? field of table 28 . - 134 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ethernet frame size ethernet frames received which are shorter than the ethernet standard of 64 bytes are counted as undersize or fragments (see table 14, on page 202 ) but are still passed through the mac block if the fcs is correct. the maximum ethernet frame size that is passed through the mac is configurable using the maximum frame length register (0x00010, table 22 on page 213 ). this 16-bit register can be configured for up to 64k frame lengths, but extremely large frames are not guaranteed to pass through the device. the actual maximum frame size supported depends on traffic conditions, but the following statements hold true: when using any number of smii interfaces, the device can support the full sonet line rate with frames sizes up to 9600 bytes. when using the gmii interface, the device can transmit frames up to 1650 bytes in length at the full sonet line rate while receiving a continuous stream of 64 byte frames. larger frames on the receive path will allow larger ethernet frames to be transmitted. if the same frame size is used in both directions, the device can support the full sonet line rate with frames up to 3000 bytes. for both the smii and gmii interfaces, slower sonet line rates can support larger ethernet frame sizes. ethernet half duplex in half-duplex mode of operation, two or more ethernet devices are connected to a common transmission medium and when one ethernet device transmits, the others listen. in the case where two ethernet devices transmit at once, a ? collision ? is said to have occurred. a ? jam sequence ? is transmitted by the transmitting ethernet device indicating the occurrence of a collision. the contention is resolved by each of the ethernet devices responsible for the collision, backing off, and attempting to re-transmit after a time period. this method is called carrier sense multiple access/collision detection (csma/cd). the ethermap-3 plus media access controller (mac) implements the 802.3 compliant csma/cd algorithm. for a complete definition of this algorithm please refer to the ieee 802.3 specification. following is an outline based on the ethermap-3 plus mac. note: carrier sense and collision detection status is indicated by the phy device to the ethermap-3 plus via the smii interface. please refer to the serial media independent interface (smii) specification for further details. carrier sense to begin transmission of an ethernet frame, the ethermap-3 plus media access controller (mac) uses three different configuration registers. after the transmission of an ethernet frame, the back-to-back inter packet gap (ipg) is enforced. after an ethernet frame is received, the non-back-to-back ipg (ipg2) is used. additionally, during the time defined by the ipgr1 configuration register, the mac monitors the carrier sense status. this carrier sense window is known as ipg1. if carrier is detected during this window, the mac does not attempt to transmit. if the carrier becomes active after the ipg1 window, transmission is begun after the proper ipg has elapsed, forcing a collision and subsequent backoff. the carrier sense window is typically configured using a two-thirds/one-third ratio, meaning that the carrier is monitored during the first two-thirds of the ipg, and is ignored during the remaining one-third. since it is not possible for the ethernet output to backpressure traffic arriving from sonet/sdh, it may be necessary to configure the ethermap-3 plus to more aggressively occupy the ethernet media by reducing the size of the ipg1 window. collision detection in the event the ethermap-3 plus mac detects a collision when the device is transmitting an ethernet frame, the mac outputs the 32-bit jam sequence. the jam sequence is made up of several bits of the crc, inverted to guarantee an invalid crc upon reception of the frame. the mac then backs off transmission of the frame (retry) based on the ? truncated binary exponential backoff ? (beb) algorithm. following this backoff time, the frame is retried. the ? no backoff ? configuration bit, when enabled, retransmits the frame without a backoff, following a collision. this option needs to be enabled with caution. - 135 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers alternate beb truncation the backoff time following a collision is a controlled randomization process called ? truncated binary exponential backoff ? . it is defined as an integer multiple of the slot times. the number of slot times to delay before the n th retransmission attempt is chosen as a uniformly distributed random integer r in the range: 0 r 2 k where k = min(n,10). so, after the first collision, the mac will backoff either 0 or 1 slot times. after the fifth collision, the mac will backoff between 0 and 32 slot times. after the tenth collision, the maximum number of slot times to backoff is 1024. by setting the ? alternate beb enable ? bit, the truncation point can be changed from min(n,10) to min(n,m) where m is set in the ? alternate beb truncation ? register. excessive collisions upon collision, the mac attempts re-transmission of the frame. as specified in the ieee 802.3 specification, a frame has excessive collisions if 15 re-transmission attempts have occurred. the number of retransmission attempts for excessive collisions is configurable. in the event a frame has been excessively deferred, the frame is discarded and will not be transmitted. it is possible to configure the ethermap-3 plus not to discard an excessively deferred frame. half-duplex flow control there is no ieee 802.3 compliant backpressure mechanism for half duplex. the common industry implementation is the ? raise carrier ? method. the ethermap-3 plus mac uses the configurable ? raise carrier ? method for flow control in half-duplex mode. in the event the ethermap-3 plus mac needs to backpressure the transmission medium, it raises carrier by transmitting the preamble. other devices on the transmission medium defer to the carrier. if a collision occurs due to the raised carrier, the congestion is resolved using the standardized collision-detect, backoff method. the duration of a raised carrier is kept below 3.3 ms in 10 mbps mode and 33 ms in 100 mbps mode so that the anti-jabber limitation in the phy device is not exceeded. to avoid an excessive deferral condition at the sender, a maximum of 16 of these raised carriers bursts will be sent, after which a transmit packet must go out before the carrier can be raised again. the host can not initiate flow control when the raise carrier method is being used. - 136 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers flow control operation overview because there could be a mismatch of data rates between an ethernet port and its corresponding sonet/sdh link (i.e., transporting 100 mbit/s using a single vc-3), ethermap-3 plus has the ability to backpressure the ethernet traffic. depending on the mode of operation of the ethernet port (i.e., full duplex or half duplex), the ethermap-3 plus provides support for the following types of flow control mechanisms: full duplex mode (for 10/100/1000 mbit/s): when configured for full duplex mode, the pause frame (as per ieee 802.3) is used a flow control mechanism. half duplex mode (for 10/100 mbit/s): when configured for half duplex mode, the csma/cd algorithm is used as a backpressure flow control mechanism. the backpressure scheme uses the ? raise carrier ? method. table 21 provides further details on specific configuration options. full duplex flow control definitions the ethermap-3 plus uses several structures to implement full duplex flow control. first, each mac channel has a separate ? txfifo ? that is used to buffer ethernet frames and perform rate adaptation between the ethernet and sonet/sdh data rates. each txfifo has a configurable high watermark and a configurable low watermark. associated with the watermarks are the high pause time value and low pause time value. these values get inserted into outgoing pause frames in the pause_time field and create the concept of a high pause frame and low pause frame which carry the high pause time value and low pause time value, respectively. in typical xon/xoff implementations the high pause frame carries a fairly large or maximum time value and the low pause frame simply carries a time value of zero. finally, there is an internal sample timer that determines when the txfifo depth is sampled. when a high pause frame is queued for transmission, the sample timer is loaded with the high pause time value and is decremented until it reaches a configurable terminal value, at which point it has expired. flow control algorithm a high pause frame is sent when any of the following are true: the txfifo depth is rising and the high watermark is crossed and the sample timer is not decrementing the sample timer expires and the txfifo depth is above the high watermark a low pause frame is sent when any of the following are true: the txfifo depth is falling and the low watermark is crossed and the sample timer is not decrementing the sample timer expires and the txfifo depth is below the low watermark txfifo overflow if the attached ethernet client does not properly respond to pause frames, then an overflow of the txfifo is the likely result (indicated by the atxfifo alarm, ta b l e 9 9 on page 299 ). if the fifo does overflow, further writes to the fifo are prevented and incoming ethernet traffic is discarded while observing frame boundaries (no partial frames are written into the fifo). fifo reads continue to take place allowing the fifo level to recede. once the fifo depth falls to the high watermark, writes are again allowed. during all of this, the flow control algorithm remains in effect, so if the sample timer expires while the fifo depth is above the high watermark, or if the fifo depth rises and crosses the high watermark, additional outgoing pause frames will be sent. external pause frames in addition to generating pause frames for flow control purposes, it is also possible for the ethermap-3 plus to receive pause frames from either the ethernet input interface, or from the sonet/sdh line interface. - 137 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers in the ethernet-to-sonet direction, several options exist for managing pause frames. if the arriving pause frame is detected and acted upon, then the corresponding tx mac stops transmission for the amount of time indicated in the pause_time field. this behavior is configured by setting the receive flow control enable bit described in table 18 on page 210 . whether or not the received pause frame is used to stop outgoing ethernet traffic, the pause frame can be optionally encapsulated into the sonet/sdh stream. this is controlled using the ctfcmode bits described in table 86 on page 295 . in the sonet-to-ethernet direction, pause frames are never used to stop traffic. they can either be passed through to the ethernet output or discarded, depending on the setting of the crfcmode bit described in table 48 on page 236 . in any event, all pause frames received from sonet/sdh are counted (per ethernet port) using the rpcrpausex counter. configuring full duplex flow control the following registers are used to configure full duplex flow control: the allowed ranges for the high/low watermarks depend on the sdram configuration (sdram_cfg bit) and the selection of gmii/smii mode, as shown in the table below. table 6: allowed range for high/low watermark registers notes: 1. in the watermark registers, one step of 1 hex corresponds to four bytes in the fifo. for example, if you lower the watermark by a hex value of "1", the fifo threshold will be lowered by four bytes. 2. for the high watermark, the maximum allowed value corresponds to the whole allocated fifo space minus one 32 bit word (4 bytes). for example, in the last line of table above, 3 ffff corresponds to 1,048,572 bytes, which is the whole allocated txfifo space (1* 1024*1024 bytes) minus one 32 bit word (4 bytes). concept register location enable transmit flow control enable ta b l e 1 8 receive flow control enable txfifo high watermark rhwtmk_msb_x ta b l e 9 8 rhwtmk_lsb_x txfifo low watermark rlwtmk_msb_x rlwtmk_lsb_x high pause time value rhwpt_x ta b l e 3 0 low pause time value rlwpt_x sample timer terminal value rhipse_x e-to-s pause frame filtering ctfcmode ta b l e 8 6 s-to-e pause frame filtering crfcmode ta b l e 4 8 mode sdram size memory allocated to each fifo minimum value for rlwtmk_msb_x, rlwtmk_lsb_x maximum value for rhwtmk_msb_x, rhwtmk_lsb_x smii 8mb 32 kb 0000 0020 0000 1fff 16mb 64 kb 0000 0020 0000 3fff 32mb 128 kb 0000 0020 0000 7fff gmii 8mb 256 kb 0000 0020 0000 ffff 16mb 512 kb 0000 0020 0001 ffff 32mb 1 mb 0000 0020 0003 ffff - 138 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers changing configurations when changing flow control parameters from their default values, the following procedures should be followed: from a hardware reset: 1. configure the flow control parameters ( table 30 and ta b l e 9 8 ). 2. de-assert the mac soft reset (see ta b l e 1 8 - reset tx, reset rx). 3. enable the transmit and receive mac blocks (see ta b l e 1 8 - transmit enable and receive enable). from an already configured device: 1. disable the transmit and receive mac blocks. 2. assert the mac soft reset. 3. configure the flow control parameters ( table 30 and ta b l e 9 8 ). 4. de-assert the mac soft reset. 5. enable the transmit and receive mac blocks. - 139 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers encapsulation/decapsulation when the ethernet line side is configured for smii interface, the ethermap-3 plus device provides support for up to eight independent 10/100 mbit/s ethernet mac blocks. each 10/100 mbit/s ethernet mac block is further allocated to a dedicated protocol encapsulation/decapsulation block (up to eight independent blocks) for servicing its bi-directional ethernet frame traffic. when the ethernet line side is configured for gmii interface, the ethermap-3 plus device provides support for a single 1000 mbit/s ethernet mac block (shared with the first 10/100 mbit/s ethernet mac block). the 1000 mbit/s ethernet mac block is allocated to a dedicated protocol encapsulation/decapsulation block (the first block is shared between 10/100 mbit/s and 1000 mbit/s) for servicing its bi-directional ethernet frame traffic. each protocol encapsulation/decapsulation block can be independently configured to use one of the following protocols for transport of ethernet mac frames over a sonet/sdh link: generic framing procedure (gfp), link access procedure - sdh (laps), link access procedure frame mode (lapf) and point-to-point protocol (ppp) with bridging control protocol (bcp). by default, the protocol encapsulation blocks are configured for laps and the protocol decapsulation blocks are configured for byte-synchronous hdlc (i.e., laps mode). encapsulation configuration and status registers are described in tables 35-47 . decapsulation registers are described in tables 48-61 . setting the encapsulation mode the mode of encapsulation is configurable according to the ctencapx register. the mode of decapsulation is configurable according to the crdecapx register. when the mode of decapsulation is configured to byte-synchronous hdlc, the crhdlcx register must be used to select between laps or ppp (with bcp) type. ctencapx, bit 1 ctencapx, bit 0 encapsulation modes 0 0 laps (default). 01lapf. 10gfp. 1 1 ppp (with bcp). crdecapx, bit 1 crecapx, bit 0 decapsulation modes 0 0 byte-synchronous hdlc (default). 01lapf. 10gfp. 1 1 disabled (i.e., no decapsulation is used and block is not used). crhdlcx, bit 3 byte-synchronous hdlc decapsulation mode 0 laps (default). 1 ppp (with bcp). - 140 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers changing the encapsulation mode since encapsulation mode is chosen separately for each vcg, it is possible to change the encapsulation for a particular vcg without affecting traffic on vcgs that are not changing, provided the procedure described below is followed. during the time the encapsulation is changing, payload traffic for that vcg will be interrupted, so it is appropriate to send ais on all tributaries associated with the changing vcg. high order ais can be forced by setting bit 0 of address 0x1f960, 0x1f962, or 0x1f964 according to the high order tributary desired. this will insert vc ais. set the pointer bytes to all 1s. set bit 0 of address 0x19ee6, 0x19eee, or 0x19ef6 depending upon which high order tributary that is to have ais inserted into it. to insert ais into a low order tributary, bit 2 of address 0x1a800+channel#x8 can be set. as with the vcg reconfiguration procedures, the procedures below refer to tx and rx mac reset. see the reassignment procedures beginning on page 124 for the details of tx and rx mac reset. all modes except gfp linear mode: changing encapsulation (transmit path) send ais on all tribs in the vcg tx channel x reset on (rx macx reset first, then vcgx reset) change encapsulation mode of the vcg tx channel x reset off (vcgx reset first, then rx macx reset) remove ais condition across the entire vcg changing decapsulation (receive path) rx channel x reset on (vcgx reset first, then tx macx reset) change decapsulation mode of the vcg rx channel x reset off (tx macx reset first, then vcgx reset) gfp linear mode: in linear mode, multiple mac channels are assigned to a single vcg, so all macs that make up a vcg will need to be held in reset during the change. changing encapsulation (transmit path) send ais on all tribs in the vcg tx channel x reset on (rx macx reset for all macs involved in the vcg, then vcgx reset) change encapsulation mode of the vcg tx channel x reset off (vcgx reset first, then rx macx reset for all macs involved) remove ais condition across the entire vcg changing decapsulation (receive path) rx channel x reset on (vcgx reset first, then tx macx reset for all macs involved in the vcg) change decapsulation mode of the vcg rx channel x reset off (tx macx reset for all macs involved, then vcgx reset) - 141 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers gfp generic framing procedure (gfp) is protocol for mapping packet data into an octet-synchronous transport such as sonet/sdh. unlike hdlc-based protocols, gfp does not use any special characters for frame delineation. instead, it uses a cell delineation protocol, such as used by atm, to encapsulate variable length packets. a fixed amount of overhead is required by the gfp encapsulation that is independent of the contents of the packet. the gfp protocol is specified in the itu-t g.7041/y.1303 standard. figure 52 shows the format of a gfp frame with a ethernet mac frame payload (denoted by the shaded area) relationship. figure 52. format of gfp frame with an ethernet mac frame payload as shown in figure 52 , the gfp overhead can consist of two headers: a core header, which consists of a two byte payload length indicator (pli) field and a two byte core header error control (chec) field. the core header is used for frame delineation. a payload header, which consists of a type header and an extension header (optional). the type header consists of a two byte type field and a two byte type header error control (thec) field. the type header is used to indicate the format and content of the payload information field. the ethermap-3 plus device supports frame based mapping for ethernet mac frames only. the extension header used for managing logical links, classes of service and source/destination addresses. two forms of extension headers are supported: null extension header and linear extension header. for null extension header support, no additional extension header bytes are required (as per itu-t g.7041/y.1303). for linear extension header support, four bytes are required in addition to the type header. these consist of a one byte channel id (cid) field, a one byte spare (reserved) field and a two byte extension header error control (ehec) field. as shown in figure 52 , the gfp payload information field is used to carry a complete ethernet mac frame. further, an optional a payload fcs field (4 bytes) may be inserted after the gfp payload information field. the optional payload fcs field contains a 32-bit crc sequence that protects the contents of the gfp payload information field only. ethernet mac frame g fp frame o ctets 2 pli field 2 chec field ctets 2 type field 7 p reamble 2 thec field 1 start of frame delimiter 0-60 extension header 6 destination address (da) 6 source address (sa) 2 length/type gfp mac client data payload information field pad 4 frame check sequence (fcs) bits 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 - 142 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers in the transmit direction (ethernet-to-sonet/sdh), for each encapsulation block configured for gfp, the following functions are supported: encapsulate ethernet mac frame within a gfp frame. each ethernet mac frame is encapsulated with a core header, a payload header and an optional payload fcs field. for the core header, the pli and the chec fields are generated. for the type header within payload header, the pti, pfi, exi, upi and thec fields are generated and configurable. for the extension header (when in linear frame mode) within payload header, the cid, spare and ehec fields are generated and configurable. gfp core header scrambling can be enabled/disabled using the ctcscrx register. gfp client data and client management frame formats are supported. gfp idle frame generation and insertion is supported. cptix(2-0) gfp payload type identifier field configuration 0x0 - 0x7 contents of the pti field for gfp client data frames only. (default = 0x0) cpfix bit 3 gfp payload fcs indicator control 0 the pfi bit within the gfp payload header is set to zero (0). gfp payload fcs field is not inserted. (default) 1 the pfi bit within the gfp payload header is set to one (1). gfp payload fcs field is inserted. cexix(3-0) gfp extension header identifier field configuration 0x0 - 0xf contents of the exi field with in the gfp payload header. (default = 0x0) cupix(7-0) gfp user payload identifier field configuration 0x00 - 0xff contents of the upi field for gfp client data frames only. (default = 0x01) csparex (7-0) gfp spare field configuration 0x00 - 0xff contents of the spare field within the gfp extension header when using gfp linear frame structure. (default = 0x00) cfecidx (7-0) gfp channel id (cid) field configuration 0x00 - 0xff contents of the cid field within the gfp extension header when using gfp linear frame structure. (default = 0x00) ctcscrx bit 3 gfp core header scrambling control 0 enable scrambling of gfp core header only. (default) 1 disable scrambling of gfp core header only. - 143 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers self-synchronous scrambler (x 43 +1 polynomial) for the payload header, payload information field and payload fcs field (optional) can be enabled/disabled according using the ctpscrdx register. furthermore, the scrambler can be initialized to a default state using the ctscrinitx register. 32-bit crc sequence generation for the payload fcs field (optional), over all octets of the gfp payload information field only, is supported. gfp frame multiplexing (when in linear frame mode, cexix=1) from multiple ethernet ports using a configurable scheduling algorithm is supported. for further details, please see the following section ? gfp linear frame mode operation ? on page 150 . detection and handling of errored ethernet mac frames on gfp ingress is supported. an alarm, atetherrx, is generated when an errored ethernet mac frame is detected and discarded for the transmit direction. generation of gfp client signal fail (csf) indication is supported using the ctgfptxcsfx register. the ctgfptxcsfx allows to enter into the csf mode (when set to 1). in that mode, every 100 ms, a csf indication is transmitted to the line. the atgfpcsfx alarm indicates the activation of this mode. to exit from this mode, the ctgfptxcsfx must be cleared. ability to insert errors in chec, thec and ehec fields for testing is configurable respectively using the ctchecerrx, ctthecerrx and ctehecerrx registers (self-clearing type, i.e., error is inserted only in a single frame). furthermore, the chec generator can be initialized to a default state using the cthecinitialx register. ctpscrdx bit 7 gfp payload area scrambling control 0 enable scrambling of gfp payload area only. (default) 1 disable scrambling of gfp payload area only. ctscrinitx bit 0 gfp payload scrambler initialization control 0 scrambler is initialized with an all zeros state. (default) 1 scrambler is initialized with an all ones state. ctgfptxcsfx bit 4 gfp csf frame transmit control 0 disable gfp csf frame transmit mode. (default) 1 enable gfp csf frame transmit mode. beginning at the next gfp frame, a csf indication is transmit every 100 ms period (i.e., no gfp client data frames can be transmitted). gfp idle frames are transmitted in the interim. ctchecerrx bit 0 gfp chec error insertion 0 disable chec error insertion. (default) 1 enable chec error insertion. error is inserted by inverting the calculated chec field before transmission. - 144 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers for each gfp frame byte that is input to the chec/thec/ehec generator, the bit-order within the byte can be swapped/reversed using the cthecswapinx register. for each gfp chec/thec/ehec byte from the chec/thec/ehec generator, the bit-order within the chec/thec/ehec byte can be swapped/reversed using the cthecswapoutx register before transmission to sonet/sdh. this does not affect the chec/thec/ehec calculation result but rather the transmission bit- order of each fcs byte into sonet/sdh. ability to force abort generation is configurable using the ctabtgx register. ctthecerrx bit 1 gfp thec error insertion 0 disable thec error insertion. (default) 1 enable thec error insertion. error is inserted by inverting the calculated thec field before transmission. ctehecerrx bit 2 gfp ehec error insertion 0 disable ehec error insertion. (default) 1 enable ehec error insertion. error is inserted by inverting the calculated ehec field before transmission. cthecinitialx bit 0 gfp chec generator initialization control 0 chec generator is initialized with an all zeros state. (default) 1 chec generator is initialized with an all ones state. cthecswapinx bit 0 gfp chec/thec/ehec input swap control 0 for each gfp frame byte at the input of the chec/thec/ehec generator, the bit-order is preserved (i.e., not swapped/reversed). (default). 1 for each gfp frame byte at the input of the chec/thec/ehec generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa). cthecswapoutx bit 0 gfp chec/thec/ehec output swap control 0 for each gfp chec/thec/ehec byte that are output from the chec/thec/ehec generator, the bit-order is preserved (i.e., not swapped/reversed) before being transmit to sonet/sdh. (default). 1 for each gfp chec/thec/ehec byte that are output from the chec/thec/ehec generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa) before being trans- mit to sonet/sdh. - 145 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers detection of fifo overflow/underflow conditions and size (maximum) of gfp payload information field via alarm and interrupt generation. the detection of fifo overflow/underflow is observable according to the atgfpfmerrx alarm. the limit of the gfp payload information size is programmable using the register rtmaxflx. the default value is 0x600. an alarm, atgfpmaxerx, is generated when the size of the gfp payload information exceeds the value configured in rtmaxflx register. ability to insert gfp client management/control frames by the host is supported. a 64-byte buffer (using 64 rtctl_x(8-0) registers) per mac is provided to store a single gfp client management/control frame from the host. the msb bit (bit 8), when set to ? 1 ? , of each byte is a valid bit to indicate that the current byte (bits 7-0) is part of the gfp client management/control frame. the host must write a valid formatted (including overhead bytes) gfp client management/control frame into the buffer such that only additional processing steps performed are: core header scrambling and payload area scrambling (note: if payload fcs is required then this is provided by the host). the stctlbx status register (which can be accessed by the host) is provided to indicate the empty/full state of the buffer. a reset of the buffer can be generated using the ctctlbrstx register. this reset will cause the buffer to discard its contents and clear the stctlbx status register (stctlbx=0). below is an example of how the host can use this buffer: step 1: if the buffer is empty, stctlbx=0 and the host is allowed to write a gfp client management/control frame. step 2: once the gfp client management/control frame has been written. the host must set the stctlbx status register (stctlbx=1) to indicate that the gfp client management/control frame is ready for transmission. step 3: during the next gfp inter-frame window (i.e., after completion of the gfp frame currently being transmitted), the stored gfp client management/control frame is inserted into the datapath for transmission to sonet/sdh. step 4: once the gfp client management/control frame has been transmitted, the stctlbx status register is cleared (stctlbx=0) by the ethermap-3 plus and an alarm, atctlx, is generated. the alarm can be used to provide an indication of the next available gfp client management/control frame transmission. ctmaxflx (15-0) gfp payload information field size 0x0001 - 0x0640 indicates maximum number of octets in the gfp payload information field that is transmitted. (default = 0x0640). when cpfix=1, for a gfp payload length that exceeds the configured value in the ctmaxflx register, the payload fcs is inverted before transmission to sonet/sdh. this will ensure that the terminating end discards the gfp frame. when cpfix=0, for a gfp payload length that exceeds the configured value in the ctmaxflx register, the current gfp payload is padded with 0xff octets up to the configured length. stctlbx bit 0 gfp client management/control frame buffer status indication 0 buffer is empty and is able to receive a new gfp client management/control frame. (default) 1 buffer is full and is not able to receive a new gfp client management/control frame. - 146 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ability to filter mapping of select gfp frames for transmission to sonet/sdh is provided using ctgfppdux register. transmission of all gfp client management/control frames (i.e., control frames received from the host) are not affected by this register. the ctoffx register can be used to filter mapping of all types of gfp frames (i.e., including gfp client management/control frames) for transmission to sonet/sdh. maintains transmit statistics counters. two types of counters are provided: the total number of gfp frame payloads transmitted (rpctgfpframex register) and the total number of gfp frame payload octets transmitted (rpctgfpbytex register). these are also described in table 43 . in the receive direction (sonet/sdh-to-ethernet), for each decapsulation block configured for gfp, the follow- ing functions are supported: decapsulate to extract the ethernet mac frame from within a gfp frame after frame delineation and sync is achieved. robustness of gfp frame delineation acquisition using four virtual framers is configurable using the crdeltax register. processing of null or linear header types is configurable using the crgfphdrx register. ctctlbrstx bit 0 gfp client management/control frame buffer reset control 0 buffer is not in reset state. (default) 1 buffer is in reset state. ctgfppdux bit 9 selective gfp frame mapping filter control 0 gfp frames are allowed to pass for mapping into sonet/sdh. (default) 1 gfp frames are not allowed (i.e., frames are discarded) to pass for map- ping into sonet/sdh. ctoffx bit 6 generic gfp frame mapping filter control 0 all types of gfp frames (i.e., including gfp client management/control frames) are allowed to pass for mapping into sonet/sdh. (default)) 1 all types of gfp frames (i.e., including gfp client management/control frames) are not allowed (i.e., frames are discarded) to pass for mapping into sonet/sdh. only gfp idle frames are mapped into sonet/sdh. crdeltax (2-0) gfp re-synchronization control 0x0 - 0x7 indicates values of delta to be used in the gfp delineation process. (default = 0x1) crgfphdrx bit 10 gfp header type processing control 0 only gfp null header type is processed. gfp frames received with other types of headers are discarded. (default) 1 only gfp linear header type is processed. gfp frames received with other types of headers are discarded. - 147 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers core header descrambling can be enabled/disabled using the crcdscrx register. single-bit error detection and correction in the core header, type header and extension header is configurable. multiple-bit error detection in the core header, type header and extension header is supported and these frames are discarded. gfp client data and client management frame formats are supported. gfp idle frame detection and discard is supported. self-synchronous descrambler (x 43 +1 polynomial) for the payload header, payload information field and payload fcs field (optional) can be enabled/disabled using the crpscrdx register. crcdscrx bit 0 gfp core header de-scrambling control 0 enable de-scrambling of gfp core header only. (default) 1 disable de-scrambling of gfp core header only. crcordisx bit 1 gfp core header single-bit error correction control 0 for gfp core header, enable single-bit error correction and all received gfp frames detected with single-bit errors are corrected and passed. (default) 1 for gfp core header, disable single-bit error correction and all received gfp frames detected with single-bit errors are discarded. crthecsx bit 2 gfp type header single-bit error correction control 0 for gfp type header, enable single-bit error correction and all received gfp frames detected with single-bit errors are corrected and passed. (default) 1 for gfp type header, disable single-bit error correction and all received gfp frames detected with single-bit errors are discarded. crehecsx bit 3 gfp extension header single-bit error correction control 0 for gfp extension header, enable single-bit error correction and all received gfp frames detected with single-bit errors are corrected and passed. (default) 1 for gfp extension header, disable single-bit error correction and all received gfp frames detected with single-bit errors are discarded. crpscrdx bit 4 gfp payload area de-scrambling control 0 enable de-scrambling of gfp payload area only. (default) 1 disable de-scrambling of gfp payload area only. - 148 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 32-bit crc sequence generation and checking for the payload fcs field (optional), over all octets of the gfp payload information field only, is supported. an option is provided to pass or discard gfp frames with a fcs error using the crgfpfcserx register. gfp frame demultiplexing (when in linear frame mode) to multiple ethernet ports based on configurable cid fields is supported. for further details, please see the following section ? gfp linear frame mode operation ? on page 150 . detection of gfp client signal fail (csf) indication is supported. detection of size (maximum) of gfp payload information field via alarm and interrupt generation. the max- imum size of the received gfp frame payload information field (in octets) can be configured using the rrmaxflx register. an alarm, argfpmaxerx, is generated when the size of the received gfp frame pay- load information field (in octets) exceeds the value configured in rrmaxflx register. gfp host insertion/extraction of management/control frames ability to filter and extract gfp client management/control frames by the host is supported. a 64-byte buffer (using 64 rrlmix_ (8-0) registers) per mac is provided to store a single gfp client manage- ment/control frame for the host extraction. lmi is an acronym for local management interface. the msb bit (bit 8), when set to ? 1 ? , of each byte is a valid bit to indicate that the current byte (bits 7-0) is part of the gfp client management/control frame. this applies up to the first byte where msb = 0 (bit 8); all other bytes after and including the byte with msb = 0 are not a part of the received frame. the host is provided with a gfp client management/control frame such that only the following processing have been performed: gfp frame delineation, core header descrambling and payload area descrambling. the srctlbx status register (which can be accessed by the host) is provided to indicate the empty/full state of the buffer. a reset of the buffer can be generated using the crctlbrstx register. this reset will clear the srctlbx status register (srctlbx=0) and enable a new management/control frame to be received. the rrgfpcpx register is used to configure the payload header type field value to be checked in order to extract the gfp client man- agement/control frame and the rrctlmaska1x register is used as a bit level mask that is applied to the crgfpcpx register. below is an example of how the host can use this buffer: step 1: if the buffer is empty, srctlbx=0 and the host is not allowed to read for a new gfp client management/control frame. step 2: once the gfp client management/control frame has been received, the srctlbx status register is set (srctlbx=1) by the ethermap-3 plus and an alarm, arctlrxx, is generated to indicate that the present gfp client management/control frame is ready for extraction by the host. no further gfp client management/control frames may be written into the buffer (i.e., are discarded silently) until the srctlbx status register is cleared. if the received gfp client management/control frame is bigger than the buffer size, an alarm, arctlberrx, is generated and the buffer must be cleared/reset by the host. crgfpfcserx bit 9 gfp fcs check handling 0 received gfp frames detected with a payload fcs error (when fcs is present) are discarded. (default) 1 received gfp frames detected with a payload fcs error (when fcs is present) are not discarded. crmaxflx (15-0) gfp payload information field size 0x0001 - 0x0640 indicates maximum number of octets in a received gfp frame payload information field not including the payload header and fcs bytes. (default = 0x0640) - 149 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers step 3: once the gfp client management/control frame has been extracted, the srctlbx status register is cleared (srctlbx=0) by the host. this is to indicate that a follow-on received gfp client management/control frame may be written into the buffer. ability to filter decapsulation of select gfp frames that are received from sonet/sdh is provided using crgfppdux register. reception of all gfp client management/control frames (i.e., control frames des- tined for extraction by host) are not affected by this register. maintains receive statistics counters. all gfp receive side statistic counters are described in table 60 . srctlbx bit 0 gfp client management/control frame buffer status indication 0 buffer is empty and no new gfp client management/control frame has been received/stored. (default) 1 buffer is full with a new gfp client management/control frame received. crctlbrstx bit 0 gfp client management/control frame buffer reset control 0 buffer is not in reset state. (default) 1 buffer is in reset state. rrgfpcpx(15-0) gfp client management/control frame payload header type field contents 0x0000 - 0xffff indicates contents of the gfp client management/control frame payload header type field that is checked against a received control frame for extraction to the host. this is used in conjunction with the rrctlmaska1 mask register. (default = 0x8000) the structure of this register is as follows: pti field value = bits (15-13), pfi field value = bit 12, exi field value = bits (11-8) and upi field value = bits (7-0). rrctlmaska1x(15-0) gfp client management/control frame payload header type field contents mask 0x0000 - 0xffff mask value that is applied to the rrgfpcpx register contents to aid in the fil- tering process. when the mask bit is set (i.e., to a 1), the corresponding bit of the rrgfpcpx register is used for filtering. (default = 0xffff) crgfppdux bit 11 selective gfp frame decapsulation filter control 0 all gfp frame types received frames from sonet/sdh are allowed to be decapsulated. 1 only gfp csf and gfp client management/control frames matching the rrgfpcpx register are allowed to be decapsulated. (default) - 150 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers gfp linear frame mode operation this mode allows support for scenarios where traffic from multiple independent mac ports can be transported within a single vcg on sonet/sdh. the use of this mode requires configuration for linear frame extension header (which is added to the transported gfp frame) and of the cid tables (which configure the ethermap-3 plus for this operation). note that, for each vcg operating in gfp linear frame mode, the extension header field (exi) within the gfp payload header must be configured using the cexi register for the transmit side. on the receive side, the crgfphdrx register must be configured to allow for correct processing of gfp linear frames. transmit side linear extension header the following registers are used for configuration inputs for the transmit side linear extension header bytes. these bytes are written in during system configuration, and are updated only in a static manner by host processor. spare field: for each mac port, the csparex register is used to configure the insertion value of the spare field within the linear frame extension header. channel id field (cid): for each mac port, the cfecidx register is used to configure the value of the cid field. this field will be common to all the frames transmitted from that mac port; thus the contents of the cfecidx register will represent the originating mac port id, when the frame is received by the far-end mac port. transmit side cid configuration tables when a vcg operates in gfp linear mode, several mac ports may be configured to multiplexed in it. for any vcg, the cidtablex_0, cidtablex_1, cidtablex_2, cidtablex_3, cidtablex_4, cidtablex_5, cidtablex_6, cidtablex_7 registers will allow configuration of specific mac ports that will multiplexed in that vcg. these registers are only modified in a static manner by the host upon initialization of the gfp link. note that the 8 mac ports need not be all involved in the frame multiplexing process: for example, only a subset of the ? n ? ethernet ports may be multiplexed in a given vcg. the operation of the cidtablex registers can be represented with a example scheduling matrix, shown in table 7 . this matrix is used to configure/control the multiplexing process for all the participating mac ports configured for gfp linear frame mode. table 7 shows an example configuration of the scheduling matrix. the vcg are represented along the vertical axis; on horizontal axis, the matrix represents the mac ports that a vcg will service. table 7: scheduling matrix vcg013122311 vcg1747747nn vcg2nnnnnnnn vcg3nnnnnnnn vcg4nnnnnnnn vcg5nnnnnnnn vcg6nnnnnnnn vcg755500505 - 151 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers scheduling matrix explanation: 1) the above matrix can be interpreted as follows: transport path vcg0 (represented on the top row), will first transmit one frame from mac1, then one frame from mac3, then one frame from mac1, then one frame from mac2, then one frame from mac2, then one frame from mac3, then one frame from mac1, then one frame from mac1 etc. this cycle is continuously repeated. for transport path vcg 1, the mac ports are serviced in this order: 7, 4, 7, 7, 4, 7, 4, 7, 7, 4, etc. for transport path vcg 2, there are no participating mac ports. for transport path vcg 3, there are no participating mac ports. for transport path vcg 4, there are no participating mac ports. for transport path vcg 5, there are no participating mac ports. for transport path vcg 6, there are no participating mac ports. for transport path vcg 7, the mac ports are serviced in this order: 5, 5, 5, 0, 0, 5, 0, 5, etc. 2) for each vcg row, each entry identifies the mac port (configured for gfp linear frame) to be serviced. also, each entry represents only one complete ethernet frame to be accepted each time into the multiplexing process. 3) ? n ? represents a null value. the entries are read/serviced from left to right and wrap around to beginning of the cycle after servicing the last entry (i.e., entry number 7). a null value is used to terminate the servicing sequence order back to the first entry in the row (i.e., entry number 1). on initialization/power-up, all entries in the matrix are configured to a null value. 4) a null value cannot exist in the middle of the servicing sequence order (i.e., for example to be used to skip a service cycle). it is only allowed at the end of the servicing sequence order (see 2 above). 5) a mac port is not used across/in multiple vcgs. however, within a single vcg, an ethernet port is allowed multiple entries. 6) only mac ports configured for gfp linear frame mode are allowed to participate in the scheduling matrix multiplexing process. 7) ethernet port 3 is participating in the vcg 0 multiplexing process, this means that vcg 3 is only allowed to use other ethernet ports if they are configured for gfp linear frame mode. no laps, lapf or gfp null encapsulated ethernet frames are allowed in vcg 3. 8) when operating in gfp linear frame mode, the core header scrambling is performed by each of the separate mac blocks before the gfp linear frame is sent to the scheduling matrix for multiplexing. 9) when operating in gfp linear frame mode, the payload scrambling is only performed after the gfp linear frames have been multiplexed (as per the scheduling matrix) for each vcg separately. 10) table 8 shows how the matrix is mapped in the ethermap-3 plus register memory map. table 8: scheduling matrix mapped in the ethermap-3 plus register map x = 0 cidtablex_0 cidtablex_1 cidtablex_2 cidtablex_3 cidtablex_4 cidtablex_5 cidtablex_6 cidtablex_7 x = 1 cidtablex_0 cidtablex_1 cidtablex_2 cidtablex_3 cidtablex_4 cidtablex_5 cidtablex_6 cidtablex_7 x = 2 cidtablex_0 cidtablex_1 cidtablex_2 cidtablex_3 cidtablex_4 cidtablex_5 cidtablex_6 cidtablex_7 x = 3 cidtablex_0 cidtablex_1 cidtablex_2 cidtablex_3 cidtablex_4 cidtablex_5 cidtablex_6 cidtablex_7 - 152 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers each register cidtablex_n comprises of four bits: the most significant bit, cidtablex_n [3], indicates "entry active" (when set to '1') or "entry not active" (when set to '0'). the remaining least significant bits, cidtablex_n [2-0], indicate the select mac port. receive side linear extension header the crgfphdrx register is used to configure the type of gfp payload header (i.e., null or linear) processing for the gfp receive side. for the receive direction, the clecidx register is used to assign/configure a unique local-end cid number to each receive side mac port. this is used for processing a match condition between the local-end cid number and the cid field of the received gfp linear frame. receive side cid configuration tables for every vcg, operating in gfp linear frame mode, being received from sonet/sdh side, there is a receive cid table using crgfpcidxi (where x = 0 - 7 gfp decapsulation blocks and i = 0 - 7 entries of the receive cid table) registers. each table can be configured with up to eight cid values, corresponding to a maximum of eight ethernet ports. this enables a filtering function to be made on the received gfp frames by comparing their cid field values with the table of expected cid values. example: if vcg0 receives a frame, the cid field is compared against all the cid values listed in crgfpcid01, crgfpcid02, crgfpcid03, crgfpcid04, crgfpcid05, crgfpcid06 and crgfpcid07 registers. after this check, one of the following will happen: i) if cid value of the received frame matches any of cid values in the list, the frame is passed through, the ethernet frame is decapsulated and forwarded to the local receive ethernet port with the matching local-end cid number. ii) for all received gfp linear frames with matching cid values, when a far end receive csf indication is detected for a select cid value, an alarm, argfpfecsfcidxi (where x = 0 - 7 vcg decapsulation blocks; i = 0 - 7 entries of the receive cid table), is generated for that cid value. iii) when a match is not detected with the received gfp linear frame, the gfp frame is discarded and an alarm is generated. an alarm, argfpciderrx (where x = 0 - 7), is generated when the received gfp linear frame contains an unsupported cid value (i.e., a mismatch condition against the local end cid numbers). note that the order of the cid in the receive cid table is not important and that a cid number entry can only exist in once in the receive cid table for one given vcg (i.e., cannot have the same cid number entry exist in multiple tables). this check is performed by the software driver. x = 4 cidtablex_0 cidtablex_1 cidtablex_2 cidtablex_3 cidtablex_4 cidtablex_5 cidtablex_6 cidtablex_7 x = 5 cidtablex_0 cidtablex_1 cidtablex_2 cidtablex_3 cidtablex_4 cidtablex_5 cidtablex_6 cidtablex_7 x = 6 cidtablex_0 cidtablex_1 cidtablex_2 cidtablex_3 cidtablex_4 cidtablex_5 cidtablex_6 cidtablex_7 x = 7 cidtablex_0 cidtablex_1 cidtablex_2 cidtablex_3 cidtablex_4 cidtablex_5 cidtablex_6 cidtablex_7 clecidx (7-0) gfp local-end cid value configuration 0x00-0xff indicates a unique local-end cid number assigned to a local receive ethernet port. (default = 0x00) - 153 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers laps laps is a hdlc-like framing structure to encapsulate ieee 802.3 ethernet mac frame to provide a point-to- point full duplex simultaneous bidirectional operation. the laps protocol is specified in the following standards: itu-t x.85/y.1321 and itu-t x.86. figure 53 shows the format of a laps frame with a ethernet mac frame payload (denoted by the shaded area). figure 53. format of laps frame with an ethernet mac frame payload in the transmit direction (ethernet-to-sonet/sdh), for each encapsulation block configured for laps, the following functions are supported: encapsulate ethernet mac frame within a laps frame. each ethernet mac frame is encapsulated with a start flag (0x7e), address, control and sapi fields, a 32-bit fcs field, and a closing flag (0x7e). field insertions except the start flag can be disabled through configuration. when field insertion is enabled, the contents of the address, control and sapi fields are configurable. the management of the address and control field is performed according to the ctacselx register. msb flag (0x7e) lsb 1 octet msb address (0x04) lsb 1 octet msb control (0x03) lsb 1 octet msb first octet of sapi (0xfe) lsb 1 octet msb second octet of sapi (0x01) lsb 1 octet destination address (da) 6 octets source address (sa) 6 octets length / type 2 octets mac client data 46 - 1500 octets pa d fcs of mac 4 octets fcs of laps 4 octets msb flag (0x7e) lsb 1 octet msb bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb ctacselx bit 2 ctacselx bit 1 laps address and control field insertion management 0 0 address and control field contents set to all zeros. - 154 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers the management of the sapi field is controlled by the ctsapix register. shared flag (start and closing) generation is configurable. idle flag generation and insertion is supported. the ctflagx register allows to configure the minimum number of flags to be inserted between two consecutive laps frames. self-synchronous scrambler (x 43 +1 polynomial) can be enabled or disabled. the ctscrdx register allows to enable/disable scrambling of laps frame. furthermore, the scrambler can be initialized to a default state using the ctscrinitx register. 32-bit fcs generation over all bits of the address, control, sapi, payload information field (shaded area as shown in figure 53 ) not including any flags and abort sequences, is configurable using the ctfcsx register. furthermore, the fcs generator can be initialized to a default state using the ctfcsinitiallx register. 0 1 address and control field contents contain fixed default values (i.e., address=0x04, control=0x03). (default). 10reserved. 1 1 address and control field contents are taken from the rtacfdx register. ctsapix bit 3 laps sapi field insertion management 0 sapi field contents are taken from the rtsapfdx register. 1 sapi field contents set to all zeros. ctflagx bit 0 laps flag insertion 0 a single flag are inserted between sequential laps frames (i.e., a shared flag). 1 minimum of two flags are inserted between two consecutive laps frames. (default). ctscrdx bit 2 laps scrambling control 0 enable scrambling of laps frame. (default) 1 disable scrambling of laps frame. ctscrinitx bit 0 laps scrambler initialization control 0 scrambler is initialized with an all zeros state. (default) 1 scrambler is initialized with an all ones state. ctfcsx bit 3 laps fcs generation/calculation mode 0 32-bit fcs calculation is disabled and all four fcs field octets are not inserted. 1 32-bit fcs calculation is enabled and all four fcs field octets are inserted. (default) ctacselx bit 2 ctacselx bit 1 laps address and control field insertion management - 155 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers for each laps fcs byte from the fcs generator, the bit-order within the fcs byte can be swapped/reversed using the ctfcsswapoutx register before transmission to sonet/sdh. this does not affect the fcs calculation result but rather the transmission bit-order of each fcs byte into sonet/sdh. for each laps frame byte that is output from the fcs generator, the bit-order within the byte can be swapped/reversed using the ctfcsswapoutx register before it is transmitted to sonet/sdh. transparency processing (octet stuffing for flags and control escape) is supported. byte stuffing occurs between start and closing flags. stuffing replaces each byte within a laps frame that matches the flag or control escape code bytes with a two-byte sequence. ability to insert fcs errors for testing is configurable using a self-clearing ctfcsex register (i.e., error is inserted only in a single frame). ability to force abort generation is configurable. the ctabtgx register allows to force (ctabtgx=1) the abortion of the current encapsulated frame by sending 0x7d and 0x7e bytes. ctfcsinitiallx bit 0 laps fcs generator initialization control 0 fcs generator is initialized with an all zeros state. 1 fcs generator is initialized with an all ones state. (default) ctfcsswapinx bit 0 laps fcs input swap control 0 for each laps frame byte at the input of the fcs generator, the bit-order within is preserved (i.e., not swapped/reversed). in this case, the least significant bit of each byte is input first into the fcs generator. (default). 1 for each laps frame byte at the input of the fcs generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa). in this case, the most significant bit of each byte is input first into the fcs generator. ctfcsswapoutx bit 0 laps fcs output swap control 0 for each laps fcs byte output from the fcs generator, the bit-order within is pre- served (i.e., not swapped/reversed) before being transmit to sonet/sdh. (default). 1 for each laps fcs byte output from the fcs generator, the bit-order is not pre- served (i.e., is swapped/reversed, msb becomes lsb and vice-versa) before being transmit to sonet/sdh. ctfcsex bit 4 laps fcs error insertion 0 the 32-bit fcs is transmitted without any error insertion. (default) 1 the 32-bit fcs is errored (i.e., inverted) before transmission. ctabtgx bit 5 laps transmit abort generation 0 no abort generated. (default) 1 current frame under transmission is aborted by 0x7d followed by 0x7e. - 156 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers detection of fifo overflow/underflow conditions and size (maximum) of laps payload information field via alarm and interrupt generation. the detection of fifo overflow/underflow is observable according to the atlpferrx alarm. the limit of the laps payload information size (in octets) is programmable using the rtmaxflx(15-0) register. an alarm, atmaxerx, is generated when the size of the laps payload information field exceeds the value configured in rtmaxflx register. ability to insert laps control frames by the host is supported. a 64-byte buffer (using 64 rtctl_x(8-0) registers) per mac is provided to store a single laps control frame from the host. the msb bit (bit 8), when set to ? 1 ? , of each byte is a valid bit to indicate that the current byte (bits 7-0) is part of the laps control frame. the host must write a valid formatted (including overhead bytes) laps control frame into the buffer such that only additional processing steps performed are: fcs calculation, byte stuffing, addition of flags and scrambling. the stctlbx status register (which can be accessed by the host) is provided to indicate the empty/full state of the buffer. a reset of the buffer can be generated using the ctctlbrstx register. this reset will cause the buffer to discard its contents and clear the stctlbx status register (stctlbx=0). below is an example of how the host can use this buffer: step 1: if the buffer is empty, stctlbx=0 and the host is allowed to write a laps control frame. step 2: once the laps control frame has been written. the host must set the stctlbx status register (stctlbx=1) to indicate that the laps control frame is ready for transmission. step 3: during the next laps inter-frame window (i.e., after the closing flag of the preceding laps frame and before the opening flag of the following laps frame), the stored laps control frame is inserted into the datapath for transmission to sonet/sdh. step 4: once the laps control frame has been transmitted, the stctlbx status register is cleared (stctlbx=0) by the ethermap-3 plus and an alarm, atctlx, is generated. the alarm can be used to provide an indication of the next available laps control frame transmission. ability to filter mapping of laps frames for transmission to sonet/sdh is provided using ctlppdux register. transmission of all laps control frames (i.e., control frames received from the host) are not affected by this register. the ctoffx register can be used to filter mapping of all types of laps frames (i.e., including laps control frames) for transmission to sonet/sdh. rtmaxflx (15-0) laps payload information field size 0x0000 - 0x0640 indicates maximum number of octets in the laps payload information field that is transmitted. (default = 0x0640) stctlbx bit 0 laps control frame buffer status indication 0 buffer is empty and is able to receive a new laps control frame. (default) 1 buffer is full and is not able to receive a new laps control frame. ctctlbrstx bit 0 laps control frame buffer reset control 0 buffer is not in reset state. (default) 1 buffer is in reset state. - 157 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers maintains transmit statistics counters. two types of counters are provided: the total number of laps frame payloads transmitted (rpctlapsframex register) and the total number of laps frame payload octets transmitted (rpctlapsbytex register) to sonet/sdh. these are also described in table 43 . in the receive direction (sonet/sdh-to-ethernet), for each decapsulation block configured for laps, the following functions are supported: decapsulate to extract the ethernet mac frame from within a laps frame. field extraction and checking, except the start and closing flags, can be disabled through configuration. when field extraction and checking is enabled, the contents of the address, control and sapi fields of a received laps frame are validated against configurable stored values. further, an option to discard frames with a mismatch of one of the fields, is configurable. the cracselx(1:0) register allows to configure the type of check to be performed on the address and control field contents. ctlppdux bit 4 laps frame mapping filter control 0 laps frames are allowed to pass for mapping into sonet/sdh. (default) 1 laps frames are not allowed (i.e., frames are discarded) to pass for mapping into sonet/sdh. ctoffx bit 6 generic laps frame mapping filter control 0 all types of laps frames (i.e., including laps control frames) are allowed to pass for mapping into sonet/sdh. (default) 1 all types of laps frames (i.e., including laps control frames) are not allowed (i.e., frames are discarded) to pass for mapping into sonet/sdh. only flags (i.e., 0x7e octets) are mapped into sonet/sdh. cracselx bit 4 cracselx bit 3 laps address and control field contents check control 0 0 address and control field contents check is disabled. assume address and control fields are present. 0 1 address and control field contents checked against fixed values (i.e., address=0x04, control=0x03). (default). 1 0 reserved. 1 1 address and control field contents checked against the contents of rracfdx register. - 158 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers the crsapix register allows to configure the type of check to be performed on the sapi field contents. the crmmaex register allows to configure handling of laps frame with mismatched address or control or sapi field contents. an alarm, arlpsfmmx, is generated when a mismatch is detected on the address or control or sapi field contents of the received laps frame. shared flag (start and closing) detection is configurable. idle flag detection and discard is supported. the crflagx register allows to configure the type of flag detection between consecutive laps frames. self-synchronous de-scrambler (x 43 +1 polynomial) can be enabled or disabled according to the crscrdx register. 32-bit fcs generation and checking over all bits of the address, control, sapi, payload information field (shaded area as shown in figure 53 ) not including any flags and abort sequences, is configurable. the crfcs register allows to configure enable/disable laps fcs checking. further, an option is provided to process or discard laps frames with a fcs error according to the crlpfcserx register. an alarm, arlpsfcser, is generated when a laps frame is received with fcs error. crsapix bit 5 laps sapi field contents check control 0 sapi field contents check is disabled. 1 sapi field contents checked against the contents of rrsapfdx register. (default) crmmaex bit 6 laps field contents mismatch management 0 laps frame with mismatched address or control or sapi field contents is discarded. (default) 1 laps frame with mismatched address or control or sapi field contents is not dis- carded crflagx bit 1 laps flag detection control 0 at least two flags to be detected between laps frames. (default). 1 at least a single flag to be detected between laps frames (i.e., a shared flag). crscrdx bit 0 laps descrambling control 0 enable descrambling of laps frame. (default) 1 disable descrambling of laps frame. crfcsx bit 2 laps fcs check 0 32-bit fcs check is disabled and assume all four fcs field octets are not present. 1 32-bit fcs check is enabled. (default) - 159 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers for each received laps frame byte that is input to the fcs generator for checking, the bit-order within the byte can be swapped/reversed using the crfcsswapinx register. transparency processing (octet de-stuffing for flags and control escape) is supported. byte de-stuffing occurs between start and closing flags. ability to detect an abort indication via alarm and interrupt generation. to force an abort of the current frame, the crlpabtgx register needs to set to 1. an alarm, arlpsabtdx, is generated when an abort indication is detected (i.e., receive 0x7d followed by 0x7e) on the receive side. processing of invalid laps frames as per itu-t x.86. detection of size (minimum and maximum) of laps payload information field via alarm and interrupt gener- ation. the minimum size of the received laps frame (in octets) can be configured using the rrlpminflx register (i.e., the number of octets between the opening and closing flags). an alarm, arlpsshterx, is generated when the size of received laps frame is less than six octets and this frame is aborted. an alarm, arlpsminerx, is generated when the size of the received laps frame is greater than six octets but less than the value configured in rrlpminflx register. the maximum size of the received laps frame payload information field (in octets) can be configured using the rrmaxflx register. an alarm, arlpsmaxerx, is generated when the size of the received laps frame payload information field (in octets) exceeds the value configured in rrmaxflx register. crlpfcserx bit 8 laps fcs check handling (used when fcs check is enabled as per crfcsx register) 0 received laps frames with fcs error are discarded. (default) 1 received laps frames with fcs error are not discarded. crfcsswapinx bit 0 laps fcs input swap control 0 for each received laps frame byte at the input of the fcs generator, the bit-order is preserved (i.e., not swapped/reversed). (default). 1 for each received laps frame byte at the input of the fcs generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa). crlpabtgx bit 7 laps abort generation 0 no frame aborted. (default) 1 current frame under receive is aborted. rrlpminflx(7-0) laps frame size 0x06 - 0xff indicates minimum number of octets present in a received laps frame between opening and closing flags. (default = 0x06) rrmaxflx(15-0) laps frame payload information field size 0x0001 - 0x0640 indicates maximum number of octets in a received laps frame payload information field. (default = 0x0640) - 160 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ability to filter and extract laps control frames by the host is supported. a 64-byte buffer (using 64 rrlmix_ (8-0) registers) per mac is provided to store a single laps control frame for the host extraction. the msb bit (bit 8), when set to ? 1 ? , of each byte is a valid bit to indicate that the current byte (bits 7-0) is part of the laps control frame. this applies up to the first byte where msb = 0 (bit 8); all other bytes after and includ- ing the byte with msb = 0 are not a part of the received frame. the host is provided with a laps control frame such that only the following processing have been performed: fcs check, byte de-stuffing and removal of flags. the srctlbx status register (which can be accessed by the host) is provided to indicate the empty/full state of the buffer. a reset of the buffer can be generated using the crctlbrstx register. this reset will clear the srctlbx status register (srctlbx=0) and enable a new management/control frame to be received. the rrlpcpx register is used to configure the sapi value to be checked in order to extract the laps control frame and the rrctlmaska1x register is used as a bit level mask that is applied to the crlpcpx register. below is an example of how the host can use this buffer: step 1: if the buffer is empty, srctlbx=0 and the host is not allowed to read for a new laps control frame. step 2: once the laps control frame has been received, the srctlbx status register is set (srctlbx=1) by the ethermap-3 plus and an alarm, arctlrxx, is generated to indicate that the present laps control frame is ready for extraction by the host. no further laps control frames may be written into the buffer (i.e., are discarded silently) until the srctlbx status register is cleared. if the received laps control frame is bigger than the buffer size, an alarm, arctlberrx, is generated and the buffer must be cleared/reset by the host. step 3: once the laps control frame has been extracted, the srctlbx status register is cleared (srctlbx=0) by the host. this is to indicate that a follow-on received laps control frame may be written into the buffer. srctlbx bit 0 laps control frame buffer status indication 0 buffer is empty and no new laps control frame has been received/stored. (default) 1 buffer is full with a new laps control frame received. crctlbrstx bit 0 laps control frame buffer reset control 0 buffer is not in reset state. (default) 1 buffer is in reset state. rrlpcpx(15-0) laps control frame sapi field contents 0x0000 - 0xffff indicates contents of the laps control frame sapi field that is checked against a received control frame for extraction to the host. this is used in conjunction with the rrctlmaska1 mask register. (default = 0x0000) rrctlmaska1x(15-0) laps control frame sapi field contents mask 0x0000 - 0xffff mask value that is applied to the rrplcpx register contents to aid in the filtering process. when the mask bit is set (i.e., to a 1), the corresponding bit of the rrplcpx register is used for filtering. (default = 0xffff) - 161 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ability to filter decapsulation of select laps frames (i.e., frames with sapi field contents equal to rrsapfdx register) that are received from sonet/sdh is provided using crlppdux register. reception of all laps control frames (i.e., control frames destined for extraction by host) are not affected by this register. maintains receive statistics counters. all laps receive side statistic counters are described in ta b l e 6 0 . crlppdux bit 9 selective laps frame decapsulation filter control 0 received frames from sonet/sdh, with sapi field contents equal to rrsapfdx register, are allowed to be decapsulated. 1 received frames from sonet/sdh, with sapi field contents equal to rrsapfdx register, are not allowed (i.e., frames are discarded) to be decapsulated. (default) - 162 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers lapf lapf is a hdlc-like framing structure to encapsulate ieee 802.3 ethernet mac frame to provide a point-to- point full duplex simultaneous bidirectional operation. the lapf protocol is specified in the itu-t q.922 standard. use of lapf for transport of ethernet mac frames is specified in rfc2427. the ethermap-3 plus device only supports lapf bridged frame format. figure 54 shows the format of a lapf bridged frame with a ethernet mac frame payload (denoted by the shaded area). figure 54. format of lapf bridged frame with an ethernet mac frame payload in the transmit direction (ethernet-to-sonet/sdh), for each encapsulation block configured for lapf, the following functions are supported: encapsulate ethernet mac frame within a lapf frame. each ethernet mac frame is encapsulated with a start flag (0x7e), dlci, c/r, ea, fecn, becn, de, control, pad, nlpid, oui and pid fields, a 16-bit fcs field, and a closing flag (0x7e). field insertions except the start flag can be disabled through configuration according to the ctlfacnopselx register. the insertion of the pad field is also con- figurable using the ctlfpadx register. when other field insertion is enabled, the contents of dlci, c/r, ea, fecn, becn, de, control, pad, nlpid, oui and pid fields are configurable according to the registers described into the ta b l e 3 7 . bit 8bit 7bit 6bit 5bit 4bit 3bit 2bit 1 flag (0x7e) octet 011111101 upper dlci c/r ea (0x00) 2 lower dlci fecn becn de ea (0x01) 3 control (0x03) 4 pa d ( 0 x 0 0 ) 5 nlpid (0x80) 6 oui (0x00) 7 oui (0x80) 8 oui (0xc2) 9 pid (0x00) 10 pid (0x07) 11 first octet of mac destination address 12 mac frame last octet of mac frame before lan fcs n-3 lapf frame check sequence (fcs) - first octet n-2 lapf frame check sequence (fcs) - second octet n-1 flag (0x7e) 01111110n - 163 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers shared flag (start and closing) generation is configurable according to the ctflagx register. idle flag generation and insertion is supported. the ctflagx register allows to configure the minimum number of flags to be inserted between two consecutive lapf frames 16-bit fcs generation over all bits of dlci, c/r, ea, fecn, becn, de, control, pad, nlpid, oui, pid and payload information fields (shaded area as shown in figure 54 ) not including any flags and abort sequences, is configurable using the ctfcsx register. furthermore, the fcs generator can be initialized to a default state using the ctfcsinitiallx register. ctlfacnopselx bit 3 lapf address, control, nlpid, oui and pid field insertion management 0 lapf overhead field content insertion is enabled. (default) address field contents taken from rtdlcix, ctcrx, ctfecnx, ctbecnx and ctdex registers. control field contents taken from rtlfcntlx register. nlpid field contents taken from rtnlpidx register. oui field contents taken from rtouix register. pid field contents taken from rtpidx register. 1 address, control, nlpid, oui and pid field contents insertion is disabled. these fields are all set to zero. ctlfpadx bit 4 lapf pad field insertion management 0 pad field insertion is enabled and the field contents are taken from the rtpadn register. (default) 1 pad field insertion is disabled (i.e., no pad field is present in the lapf frame). ctfcsx bit 3 lapf fcs generation/calculation mode 0 16-bit fcs calculation is disabled and all fcs field octets are not inserted. 1 16-bit fcs calculation is enabled and all fcs field octets are inserted. (default) ctfcsinitiallx bit 0 lapf fcs generator initialization control 0 fcs generator is initialized with an all zeros state. 1 fcs generator is initialized with an all ones state. (default) - 164 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers for each lapf frame byte that is input to the fcs generator, the bit-order within the byte can be swapped/reversed using the ctfcsswapinx register. for each lapf fcs byte from the fcs generator, the bit-order within the fcs byte can be swapped/reversed using the ctfcsswapoutx register before transmission to sonet/sdh. this does not affect the fcs calcu- lation result but rather the transmission bit-order of each fcs byte into sonet/sdh. ability to insert lapf lmi control frames by the host is supported. a 64-byte buffer (using 64 rtctl_x(8-0) registers) per mac is provided to store a single lapf lmi control frame from the host. the msb bit (bit 8), when set to ? 1 ? , of each byte is a valid bit to indicate that the current byte (bits 7-0) is part of the lapf lmi control frame. the host must write a valid formatted (including overhead bytes) lapf lmi control frame into the buffer such that only additional processing steps performed are: fcs calculation, bit stuffing and addi- tion of flags. the stctlbx status register (which can be accessed by the host) is provided to indicate the empty/full state of the buffer. a reset of the buffer can be generated using the ctctlbrstx register. this reset will cause the buffer to discard its contents and clear the stctlbx status register (stctlbx=0). below is an example of how the host can use this buffer: step 1: if the buffer is empty, stctlbx=0 and the host is allowed to write a lapf lmi control frame. step 2: once the lapf lmi control frame has been written. the host must set the stctlbx status register (stctlbx=1) to indicate that the lapf lmi control frame is ready for transmission. step 3: during the next lapf inter-frame window (i.e., after the closing flag of the preceding lapf frame and before the opening flag of the following lapf frame), the stored lapf lmi control frame is inserted into the datapath for transmission to sonet/sdh. step 4: once the lapf lmi control frame has been transmitted, the stctlbx status register is cleared (stctlbx=0) by the ethermap-3 plus and an alarm, atctlx, is generated. the alarm can be used to provide an indication of the next available lapf lmi control frame transmission. ctfcsswapinx bit 0 lapf fcs input swap control 0 for each lapf frame byte at the input of the fcs generator, the bit-order within is preserved (i.e., not swapped/reversed). in this case, the least significant bit of each byte is input first into the fcs generator. (default). 1 for each lapf frame byte at the input of the fcs generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa). in this case, the most significant bit of each byte is input first into the fcs generator. ctfcsswapoutx bit 0 lapf fcs output swap control 0 for each lapf fcs byte output from the fcs generator, the bit-order within is preserved (i.e., not swapped/reversed) before being transmit to sonet/sdh. (default). 1 for each lapf fcs byte output from the fcs generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa) before being transmit to sonet/sdh. - 165 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ability to filter mapping of lapf frames for transmission to sonet/sdh is provided using ctlfpdux register. transmission of all lapf lmi control frames (i.e., control frames received from the host) are not affected by this register. the ctoffx register can be used to filter mapping of all types of lapf frames (i.e., including lapf lmi control frames) for transmission to sonet/sdh. transparency processing (bit-stuffing for flags and control escape) is supported. bit stuffing occurs between start and closing flags. ability to insert fcs errors for testing is configurable using a self-clearing ctfcsex register (i.e., error is inserted only in a single frame). stctlbx bit 0 lapf lmi control frame buffer status indication 0 buffer is empty and is able to receive a new lapf lmi control frame. (default) 1 buffer is full and is not able to receive a new lapf lmi control frame. ctctlbrstx bit 0 lapf lmi control frame buffer reset control 0 buffer is not in reset state. (default) 1 buffer is in reset state. ctlfpdux bit 6 lapf frame mapping filter control 0 lapf frames are allowed to pass for mapping into sonet/sdh. (default) 1 lapf frames are not allowed (i.e., frames are discarded) to pass for map- ping into sonet/sdh. ctoffx bit 6 generic lapf frame mapping filter control 0 all types of lapf frames (i.e., including lapf lmi control frames) are allowed to pass for mapping into sonet/sdh. (default) 1 all types of lapf frames (i.e., including lapf lmi control frames) are not allowed (i.e., frames are discarded) to pass for mapping into sonet/sdh. only flags (i.e., 0x7e octets) are mapped into sonet/sdh. ctfcsex bit 4 lapf fcs error insertion 0 the 16-bit fcs is transmitted without any error insertion. (default) 1 the 16-bit fcs is errored (i.e., inverted) before transmission. - 166 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers detection of fifo overflow/underflow conditions and size (maximum) of lapf payload information field via alarm and interrupt generation. the detection of fifo overflow/underflow is observable according to the atlfferrx alarm. the limit of the lapf payload information size (in octets) is programmable using the rtmaxflx(15-0) register. an alarm, atlfmaxerx, is generated when the size of the lapf payload information field exceeds the value configured in rtmaxflx register. maintains transmit statistics counters. two types of counters are provided: the total number of lapf frame payloads transmitted (rpctlapfframex register) and the total number of lapf frame payload octets transmitted (rpctlapfbytex register) to sonet/sdh. these are also described in ta b l e 4 3 . in the receive direction (sonet/sdh-to-ethernet), for each decapsulation block configured for lapf, the following functions are supported: decapsulate to extract the ethernet mac frame from within a lapf frame. field extraction and checking, except the start and closing flags, can be disabled through configuration. when field extraction and checking is enabled, the contents of dlci, c/r, ea, fecn, becn, de, control, pad, nlpid, oui and pid fields of a received lapf frame are validated against configurable stored values. the crlfacnopselx register allows to configure the type of check to performed on the address and control and nlpid and oui and pid field contents. the crlfpadx register allows to configure the type of check to performed on the pad field contents. rtmaxflx(15-0) lapf payload information field size 0x0001 - 0x0640 indicates maximum number of octets in the lapf payload information field that is transmitted. (default = 0x0640) crlfacnopselx bit 1 lapf address, control, nlpid, oui and pid field insertion management 0 lapf overhead field content checking is enabled. (default) address field contents are checked against rrlfadrx register. control field contents are checked against rrlfcntlx register. nlpid field contents are checked against rrnlpidx register. oui field contents are checked against rrouix register. pid field contents are checked against rrpidx register. register rrpidx is configured to indicate whether the ethernet frame fcs is present or not. when rrpidx=0x0001, the ethernet frame fcs is present and this ethernet frame is transmitted onto the ethernet line. when rrpidx=0x0007, the ethernet frame fcs is not present and a new ethernet fcs (4-bytes) is generated and appended by the mac before the frame is transmitted onto the ethernet line. 1 address, control, nlpid, oui and pid field contents checking is disabled. crlfpadx bit 3 lapf pad field insertion management 0 lapf pad field contents checking is enabled for only one pad field in the received lapf frame. (default). the pad field contents are checked against rrpadx register. 1 lapf pad field contents checking is disabled. assume no pad field is present in the received lapf frame. - 167 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers the crlfmmaex register allows to configure handling of lapf frames with mismatched address or control or pad or nlpid or oui or pid field contents. an alarm, arlfmmx, is generated when a mismatch is detected on the address or control or pad or nlpid or oui or pid field contents of the received lapf frame. shared flag (start and closing) detection is configurable. idle flag detection and discard is supported. the crlfflagx register allows to configure the type of flag detection between consecutive lapf frames. 16-bit fcs generation and checking over all bits of dlci, c/r, ea, fecn, becn, de, control, pad, nlpid, oui, pid and payload information fields (shaded area as shown in figure 54 ) not including any flags and abort sequences, is configurable using the crlffcsx register. further, an option is provided to process or discard lapf frames with a fcs error using the crlffcserx register. an alarm, arlffc- serx, is generated when a lapf frame is received with fcs error. for each received lapf frame byte that is input to the fcs generator for checking, the bit-order within the byte can be swapped/reversed using the crfcsswapinx register. crlfmmaex bit 5 lapf field contents mismatch management 0 lapf frame with mismatched address or control or pad or nlpid or oui or pid field contents are discarded. (default) 1 laps frame with mismatched address or control or pad or nlpid or oui or pid field contents are not discarded crlfflagx bit 0 lapf flag detection 0 at least two flags to be detected between lapf frames. (default). 1 at least a single flag to be detected between lapf frames (i.e., a shared flag). crlffcsx bit 6 lapf fcs check 0 16-bit fcs check is disabled and assume all two fcs field octets are not present. 1 16-bit fcs check is enabled. (default) crlffcserx bit 7 lapf fcs check handling (used when fcs check is enabled as per crlffcsx register) 0 received lapf frames with fcs error are discarded. (default) 1 received lapf frames with fcs error are not discarded. crfcsswapinx bit 0 lapf fcs input swap control 0 for each received lapf frame byte at the input of the fcs generator, the bit-order is preserved (i.e., not swapped/reversed). (default). 1 for each received lapf frame byte at the input of the fcs generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa). - 168 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers transparency processing (bit de-stuffing for flags and control escape) is supported. bit de-stuffing occurs between start and closing flags. ability to filter and extract lapf lmi frames by the host is supported. a 64-byte buffer (using 64 rrlmix_(8- 0) registers) per mac is provided to store a single lapf lmi buffer for the host extraction. the msb bit (bit 8), when set to ? 1 ? , of each byte is a valid bit to indicate that the current byte (bits 7-0) is part of the lapf lmi frame. this applies up to the first byte where msb = 0 (bit 8); all other bytes after and including the byte with msb = 0 are not a part of the received frame. the host is provided with a lapf lmi frame such that only the following processing have been performed: fcs check, bit de-stuffing and removal of flags. the srctlbx status register (which can be accessed by the host) is provided to indicate the empty/full state of the buffer. a reset of the buffer can be generated using the crctlbrstx register. this reset will clear the srctlbx status register (srctlbx=0) and enable a new management/control frame to be received. the crlmidlcix register allows to determine the dlci field value to be checked in order to extract the lapf lmi frame. below is an example of how the host can use this buffer: step 1: if the lmi buffer is empty, srctlbx=0 and the host is not allowed to read for a new lapf lmi frame. step 2: once the lapf lmi frame has been received, the srctlbx status register is set (srctlbx=1) by the ethermap-3 plus and an alarm, arctlrxx, is generated to indicate that the present lapf lmi frame is ready for extraction by the host. no further lapf lmi frames may be written into the buffer (i.e., are discarded silently) until the srctlbx status register is cleared. if the received lapf lmi frame is bigger than the buffer size, an alarm, arctlberrx, is generated and the buffer must be cleared/reset by the host. step 3: once the lapf lmi frame has been extracted, the srctlbx status register is cleared (srctlbx=0) by the host. this is to indicate that a follow-on received lapf lmi frame may be written into the buffer. ability to detect an abort indication via arlfabtdx alarm and interrupt generation. processing of invalid lapf frames as per itu-t q.922. detection of size (minimum and maximum) of lapf payload information field via alarm and interrupt generation. the minimum size of the received lapf frame (in octets) can be configured using the rrlfminflx register (i.e., the number of octets between the address field and closing flag). an alarm, arlffserx, is generated when the size of received lapf frame is less than three octets (between address field and closing flag) and this frame is aborted. an alarm, arlfminerx, is generated when the size of the received lapf frame is greater than three octets but less than the value configured in srctlbx bit 0 lapf lmi frame buffer status indication 0 buffer is empty and no new lapf lmi frame has been received/stored. (default) 1 buffer is full with a new lapf lmi frame received. crctlbrstx bit 0 lapf lmi frame buffer reset control 0 buffer is not in reset state. (default) 1 buffer is in reset state. crlmidlcix bit 2 lapf lmi dlci field value selection 0 lapf lmi frames with dlci=0 are filtered for extraction by the host. (default) 1 lapf lmi frames with dlci=1023 are filtered for extraction by the host. - 169 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers rrlfminflx register. the maximum size of the received lapf frame payload information field (in octets) can be configured using the rrmaxflx register. an alarm, arlfmaxerx, is generated when the size of the received lapf frame payload information field (in octets) exceeds the value configured in rrmaxflx register. provide an indication on the status of the lapf link for the receive side. the slnkstsx status register is used by the host to determine the state of the lapf link. after power-up/reset, the lapf link is set to a ? down ? state. while the link is in a ? down ? state, only lapf flags and lmi frames are allowed to be received, furthermore, while in a ? down ? state, when either 64 consecutive lapf flags or a single valid lapf frame are received, the link state is set to an ? up ? state. an alarm, alnkstsupx, is generated to indicate a change of lapf link to an ? up ? state. while the link is in ? up ? state, when 256 consecutive ? 1 ? s are received, the link state is set to a ? down ? state. an alarm, alnkstsdwnx, is generated to indicate a change of lapf link to a ? down ? state. note in case of ais on the telecom bus side, the slnkstsx status information is only updated in vc-4 mode. in all other virtual concatenation modes, ais is filtered earlier in the sonet to ethernet direction. ability to filter decapsulation of lapf frames that are received from sonet/sdh is provided using crlfpdux register. reception of all lapf lmi frames (i.e., control frames destined for extraction by host) are not affected by this register. maintains receive statistics counters. all lapf receive side statistic counters are described in table 60 . rrlfminflx(7-0) lapf frame size 0x03 - 0xff indicates minimum number of octets present in a received lapf frame between address field and closing flag. (default = 0x06) rrmaxflx(15-0) lapf frame payload information field size 0x0001 - 0x0640 indicates maximum number of octets in a received lapf frame payload information field. (default = 0x0640) crlfpdux bit 7 selective lapf frame decapsulation filter control 0 all lapf frame types received frames from sonet/sdh are allowed to be decapsulated. 1 only lapf lmi frames matching the crlmidlcix register are allowed to be decapsulated. (default) - 170 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ppp (with bcp and lcp support) the point-to-point protocol (ppp) is a hdlc-like framing structure and provides a standard method for transporting multi-protocol datagrams over point-to-point links. ppp can be used to encapsulate ieee 802.3 ethernet mac frame to provide a point-to-point full duplex simultaneous bidirectional operation. the ppp bridging control protocol (bcp) is specified in the following standards: rfc 1661, rfc 1662, rfc 2878, rfc 2615 and rfc 3518. figure 55 shows the format of a ppp frame with an ethernet mac frame payload (denoted by the shaded area). figure 55. format of ppp frame with an ethernet mac frame payload in the transmit direction (ethernet-to-sonet/sdh), for each encapsulation block configured for ppp, the following functions are supported: encapsulate ethernet mac frame within a ppp frame. each ethernet mac frame is encapsulated with a start flag (0x7e), address, control, ppp protocol, ppp bcp flags, ppp bcp pad and ppp bcp mac type fields, a 16/32-bit ppp fcs field, and a closing flag (0x7e). field insertions except the start flag can be disabled via configuration. when field insertion is enabled, the contents of the address, control, ppp protocol and ppp bcp mac type fields are configurable. the management of the address and control field is performed according to the ctppacselx register. msb flag (0x7e) lsb 1 octet msb address (0xff) lsb 1 octet msb control (0x03) lsb 1 octet msb first octet of ppp protocol (0x00) lsb 1 octet msb second octet of ppp protocol (0x31) lsb 1 octet msb f 0 z b ppp bcp pads lsb 1 octet msb ppp bcp mac type (0x01) lsb 1 octet destination address (da) 6 octets source address (sa) 6 octets length / type 2 octets mac client data 46 - 1500 octets pa d fcs of mac 4 octets fcs of ppp (16/32 bits) 2 or 4 octets msb flag (0x7e) lsb 1 octet msb bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb - 171 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers the management of the ppp protocol field is controlled by the ctpppix register. the management of the ppp bcp flag fields (i.e., f, 0, z, b fields) is performed according to the following registers: ctbcpflgfx, ctbcpflg0x, ctbcpflgzx and ctbcpflgbx. ctppacselx bit 3 ctppacselx bit 2 ppp address and control field insertion management 0 0 address and control field contents set to all zeros. 0 1 address and control field contents contain fixed default values (i.e., address=0xff, control=0x03). (default). 10reserved. 1 1 address and control field contents are taken from the rtppacfdx register. ctpppix bit 4 ppp protocol field insertion management 1 ppp protocol field contents set to all zeros. 0 ppp protocol field contents are taken from the rtppfdx register. (default) ctbcpflgfx bit 5 ppp bcp flag f field insertion management 1 ppp bcp flag f field contents set to a one ( ? 1 ? ). (default) 0 ppp bcp flag f field contents set to a zero ( ? 0 ? ). ctbcpflg0x bit 6 ppp bcp flag 0 field insertion management 1 ppp bcp flag 0 field contents set to a one ( ? 1 ? ). 0 ppp bcp flag 0 field contents set to a zero ( ? 0 ? ). (default) ctbcpflgzx bit 7 ppp bcp flag z field insertion management 1 ppp bcp flag z field contents set to a one ( ? 1 ? ). (default) 0 ppp bcp flag z field contents set to a zero ( ? 0 ? ). ctbcpflgbx bit 8 ppp bcp flag b field insertion management 1 ppp bcp flag b field contents set to a one ( ? 1 ? ). 0 ppp bcp flag b field contents set to a zero ( ? 0 ? ). (default) - 172 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers the contents of the ppp bcp mac type field is configurable using the rtbcpmacx register. ppp padding mode to be applied is configurable. the rtbcppdmodex register allows to configure the type of padding mode to be used. the ppp padding octet alignment mode (i.e., used when fixed padding mode is enabled) is controlled by the rtbcppdalignx register. the ppp padding octet alignment calculation mode (i.e., used when fixed padding mode is enabled) is con- trolled by the ctbcppdcalcx register. the contents of the ppp pad octet (i.e., used when fixed padding mode is enabled) is configurable using the rtbcppadx register. rtbcpmacx (15-8) ppp bcp mac type field contents configuration 0x00 - 0xff indicates contents of the ppp bcp mac type field. (default = 0x01) rtbcppdmodex bit 1 rtbcppdmodex bit 0 ppp padding mode control 0 0 no padding is applied. (default) 0 1 a fixed padding mode is enabled. in this mode, the ppp bcp pads field is inserted to indicate the number of pad octets that have been inserted within the ppp frame payload. 10reserved. 11reserved. rtbcppdalignx bit 3 rtbcppdalignx bit 2 ppp padding octet alignment mode control 0 0 a 2 octet alignment boundary is used. (default) 0 1 a 4 octet alignment boundary is used. 1 0 a 8 octet alignment boundary is used. 1 1 a 16 octet alignment boundary is used. ctbcppdcalcx bit 10 ppp padding octet alignment calculation mode control 0 ppp padding octet alignment calculation is over payload area only. (default). 1 ppp padding octet alignment calculation is over entire frame area. (i.e., header, payload and fcs bytes) - 173 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers shared flag (start and closing) generation is configurable. idle flag generation and insertion is supported. the ctflagx register allows to configure the minimum number of flags to be inserted between two consecutive ppp frames. self-synchronous scrambler (x 43 +1 polynomial) can be enabled or disabled. the ctscrdx register allows to enable/disable scrambling of ppp frame. furthermore, the scrambler can be initialized to a default state using the ctscrinitx register. 16 or 32-bit fcs generation over all bits of the address, control, ppp control, ppp bcp flags, ppp bcp pads, ppp bcp mac type, payload information area (shaded area as shown in figure 55 ) and optional pad octet fields not including any opening/closing flags and abort sequences, is configurable using the ctpfcsx register. furthermore, the fcs generator can be initialized to a default state using the ctfcsinitiallx register. rtbcppadx (7-0) ppp pad field contents configuration 0x00 - 0xff indicates contents of the ppp pad octet when fixed padding mode is enabled. (default = 0x00) ctflagx bit 0 ppp flag insertion 0 a single flag are inserted between sequential ppp frames (i.e., a shared flag). 1 minimum of two flags are inserted between two consecutive ppp frames. (default). ctscrdx bit 2 ppp scrambling control 0 enable scrambling of ppp frame. (default) 1 disable scrambling of ppp frame. ctscrinitx bit 0 ppp scrambler initialization control 0 scrambler is initialized with an all zeros state. (default) 1 scrambler is initialized with an all ones state. ctpfcsx bit 1 ctpfcsx bit 0 ppp fcs generation/calculation mode 0 0 16 and 32-bit fcs generation/calculation is disabled. fcs octets are not inserted in the ppp frame. this also applies to any ppp bcp control frames received from the host and for transmission to sonet/sdh. 01reserved. - 174 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers for each ppp frame byte that is input to the fcs generator, the bit-order within the byte can be swapped/reversed using the ctfcsswapinx register. for each ppp fcs byte from the fcs generator, the bit-order within the fcs byte can be swapped/reversed using the ctfcsswapoutx register before transmission to sonet/sdh. this does not affect the fcs calcu- lation result but rather the transmission bit-order of each fcs byte into sonet/sdh. 1 0 only 16 fcs generation/calculation is enabled. two fcs octets are inserted in the ppp frame. this also applies to any ppp bcp control frames received from the host and for transmission to sonet/sdh. 1 1 only 32 fcs generation/calculation is enabled. four fcs octets are inserted in the ppp frame. this also applies to any ppp bcp control frames received from the host and for transmission to sonet/sdh. (default) ctfcsinitiallx bit 0 ppp fcs generator initialization control 0 fcs generator is initialized with an all zeros state. 1 fcs generator is initialized with an all ones state. (default) ctfcsswapinx bit 0 ppp fcs input swap control 0 for each ppp frame byte at the input of the fcs generator, the bit-order within is preserved (i.e., not swapped/reversed). in this case, the least significant bit of each byte is input first into the fcs generator. (default). 1 for each ppp frame byte at the input of the fcs generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice- versa). in this case, the most significant bit of each byte is input first into the fcs generator. ctfcsswapoutx bit 0 ppp fcs output swap control 0 for each ppp fcs byte output from the fcs generator, the bit-order within is preserved (i.e., not swapped/reversed) before being transmit to sonet/sdh. (default). 1 for each ppp fcs byte output from the fcs generator, the bit-order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa) before being transmit to sonet/sdh. ctpfcsx bit 1 ctpfcsx bit 0 ppp fcs generation/calculation mode - 175 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ability to insert fcs errors for testing is configurable using a self-clearing ctfcsex register (i.e., error is inserted only in a single frame). transparency processing (octet stuffing for flags and control escape) is supported. byte stuffing occurs between start and closing flags. stuffing replaces each byte within a ppp frame that matches the flag or control escape code bytes with a two-byte sequence. ability to force abort generation is configurable. the ctabtgx register allows to force (ctabtgx=1) the abortion of the current encapsulated frame by sending 0x7d and 0x7e bytes. detection of fifo overflow/underflow conditions and size (maximum) of ppp payload information field via alarm and interrupt generation. the detection of fifo overflow/underflow is observable according to the atppferrx alarm. the limit of the ppp payload information size (in octets) is programmable using the rtmaxflx(15-0) register. an alarm, atppmaxerx, is generated when the size of the ppp payload information field exceeds the value configured in rtmaxflx register. ability to insert ppp link control protocol (lcp)/network control protocol (ncp) control frames by the host is supported. a 64-byte buffer (using 64 rtctl_x(8-0) registers) per mac is provided to store a single ppp lcp/ncp control frame from the host. the msb bit (bit 8), when set to ? 1 ? , of each byte is a valid bit to indi- cate that the current byte (bits 7-0) is part of the ppp lcp/ncp control frame. the host must write a valid formatted (including overhead bytes) ppp control frame into the buffer such that only additional processing steps performed are: fcs calculation, byte stuffing, addition of flags and scrambling. the stctlbx status register (which can be accessed by the host) is provided to indicate the empty/full state of the buffer. a reset of the buffer can be generated using the ctctlbrstx register. this reset will cause the buffer to discard its contents and clear the stctlbx status register (stctlbx=0). below is an example of how the host can use this buffer: step 1: if the buffer is empty, stctlbx=0 and the host is allowed to write a ppp lcp/ncp control frame. step 2: once the ppp lcp/ncp control frame has been written. the host must set the stctlbx status register (stctlbx=1) to indicate that the ppp lcp/ncp control frame is ready for transmission. step 3: during the next ppp inter-frame window (i.e., after the closing flag of the preceding ppp frame and before the opening flag of the following ppp frame), the stored ppp lcp/ncp control frame is inserted into the datapath for transmission to sonet/sdh. ctfcsex bit 4 ppp fcs error insertion 0 the 16 or 32-bit fcs is transmitted without any error insertion. (default) 1 the 16 or 32-bit fcs is errored (i.e., inverted) before transmission. ctabtgx bit 5 ppp transmit abort generation 0 no abort generated. (default) 1 current frame under transmission (including bcp control frame from the host) is aborted by 0x7d followed by 0x7e. the first aborted packet will contain two abort indications. rtmaxflx (15-0) ppp payload information field size 0x0001 - 0x0640 indicates maximum number of octets in the ppp payload information field that is transmitted. (default = 0x0640) - 176 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers step 4: once the ppp lcp/ncp control frame has been transmitted, the stctlbx status register is cleared (stctlbx=0) by the ethermap-3 plus and an alarm, atctlx, is generated. the alarm can be used to provide an indication of the next available ppp lcp/ncp control frame transmission. ability to filter mapping of select ppp frames (i.e., frames with ppp protocol field=0x0031) for transmission to sonet/sdh is provided using ctbpdux register. transmission of all ppp lcp/ncp control frames (i.e., control frames received from the host) are not affected by this register. the ctoffx register can be used to filter mapping of all types of ppp frames (i.e., including ppp lcp/ncp control frames) for transmission to sonet/sdh. maintains transmit statistics counters. two types of counters are provided: the total number of ppp frame payloads transmitted (rpctppframex register) and the total number of ppp frame payload octets transmit- ted (rpctppbytex register) to sonet/sdh. these are also described in table 43 . in the receive direction (sonet/sdh-to-ethernet), for each decapsulation block configured for ppp, the following functions are supported: stctlbx bit 0 ppp lcp/ncp control frame buffer status indication 0 buffer is empty and is able to receive a new ppp lcp/ncp control frame. (default) 1 buffer is full and is not able to receive a new ppp lcp/ncp control frame. ctctlbrstx bit 0 ppp lcp/ncp control frame buffer reset control 0 buffer is not in reset state. (default) 1 buffer is in reset state. ctbpdux bit 9 selective ppp frame mapping filter control 0 ppp frames with ppp protocol field=0x0031 are allowed to pass for map- ping into sonet/sdh. (default) 1 only lcp/ncp-bcp frames from the host are mapped. ctoffx bit 6 generic ppp frame mapping filter control 0 all types of ppp frames (i.e., including ppp lcp/ncp control frames) are allowed to pass for mapping into sonet/sdh. (default) 1 all types of ppp frames (i.e., including ppp lcp/ncp control frames) are not allowed (i.e., frames are discarded) to pass for mapping into sonet/sdh. only flags (i.e., 0x7e octets) are mapped into sonet/sdh. - 177 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers decapsulate to extract the ethernet mac frame from within a ppp frame. field extraction and checking, except the start and closing flags, can be disabled through configuration. when field extraction and checking is enabled, the contents of the address, control, ppp protocol, ppp bcp flags and ppp bcp mac type fields of a received ppp frame are validated against configurable stored values. further, an option to discard frames with a mismatch of one of the fields, is configurable. the crpacselx register allows to configure the type of check to be performed on the address and control field contents of a received ppp frame. the crpprotx register allows to configure the type of check to be performed on the ppp protocol fields con- tents of a received ppp frame. the crpfgx register allows to configure the type of check to be performed on the ppp bcp flags field con- tents of a received ppp frame . the crpmacx register allows to configure the type of check to be performed on the ppp bcp mac type field contents of a received ppp frame. crpacselx bit 2 crpacselx bit 1 ppp address and control field contents check control 0 0 address and control field contents check is disabled. assume address and control fields are present. 0 1 address and control field contents checked against fixed values (i.e., address=0xff, control=0x03). (default). 1 0 reserved. 1 1 address and control field contents checked against the contents of rrpacfdx register. crpprotx bit 11 ppp protocol field contents check control 0 ppp protocol field contents check is disabled. 1 ppp protocol field contents checked against the contents of rrpprotfdx register. (default) crpfgx bit 5 ppp bcp flags field contents check control 0 ppp bcp flags field contents check is disabled. 1 ppp bcp flags field contents checked against the contents of rrpfgfdx register. (default) crpmacx bit 7 ppp bcp mac type field contents check control 0 ppp bcp mac type field contents check is disabled. 1 ppp bcp mac type field contents checked against the contents of rrpmacfdx register. (default) - 178 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers the crpacmmaex register allows to configure handling of ppp frame with mismatched address or control field contents. an alarm, arpacmmx, is generated when a mismatch is detected on the address or control field contents of a received ppp frame. the crpprotmmaex register allows to configure handling of ppp frame with mismatched ppp protocol field contents. an alarm, arpprotmmx, is generated when a mismatch is detected on the ppp protocol field contents of a received ppp frame. the crpfgmmaex register allows to configure handling of ppp frame with mismatched ppp bcp flags field contents. an alarm, arpfgmmx, is generated when a mismatch is detected on the ppp bcp flags field contents of a received ppp frame. the crpmacmmaex register allows to configure handling of ppp frame with mismatched ppp bcp mac type field contents. an alarm, arpmacmmx, is generated when a mismatch is detected on the ppp bcp mac type field contents of a received ppp frame. shared flag (start and closing) detection is configurable. idle flag detection and discard is supported. the crflagx register allows to configure the type of flag detection between consecutive ppp frames. crpacmmaex bit 0 ppp address and control field contents mismatch management 0 ppp frame with mismatched address or control field contents is discarded. (default) 1 ppp frame with mismatched address or control field contents is not discarded. crpprotmmaex bit 12 ppp protocol field contents mismatch management 0 ppp frame with mismatched ppp protocol field contents is discarded. (default) 1 ppp frame with mismatched ppp protocol field contents is not discarded. crpfgmmaex bit 6 ppp pcp flags field contents mismatch management 0 ppp frame with mismatched ppp bcp flags field contents is discarded. (default) 1 ppp frame with mismatched ppp bcp flags field contents is not discarded. crpmacmmaex bit 8 ppp bcp mac type field contents mismatch management 0 ppp frame with mismatched ppp bcp mac type field contents is discarded. (default) 1 ppp frame with mismatched ppp bcp mac type field contents is not discarded. crflagx bit 1 ppp flag detection control 0 at least two flags to be detected between ppp frames. (default). 1 at least a single flag to be detected between ppp frames (i.e., a shared flag). - 179 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers self-synchronous de-scrambler (x 43 +1 polynomial) can be enabled or disabled according to the crscrdx register. 16 or 32-bit fcs generation and checking over all bits of the address, control, ppp control, ppp bcp flags, ppp bcp pads, ppp bcp mac type, payload information area (shaded area as shown in figure 55 ) not including any opening/closing flags and abort sequences, is configurable. the crpfcsx register allows to configure enable/disable ppp fcs checking and the crpcrcsx register allows to configure for use of 16 or 32-bit fcs checking. further, an option is provided to process or discard ppp frames with a fcs error according to the crpppcserx register. an alarm, arpppfcser, is generated when a ppp frame is received with fcs error. for each received ppp frame byte that is input to the fcs generator for checking, the bit-order within the byte can be swapped/reversed using the crfcsswapinx register. transparency processing (octet de-stuffing for flags and control escape) is supported. byte de-stuffing occurs between start and closing flags. crscrdx bit 0 ppp descrambling control 0 enable descrambling of ppp frame. (default) 1 disable descrambling of ppp frame. crpfcsx bit 4 ppp fcs check control 0 fcs check is disabled and assume all fcs field octets are not present. 1 fcs check is enabled. (default) crpppcserx bit 10 ppp fcs check handling (used when fcs check is enabled as per crpfcsx register) 0 received ppp frames with fcs error are discarded. (default) 1 received ppp frames with fcs error are not discarded. crpcrcsx bit 3 ppp fcs check type select control 0 32-bit fcs checking used. (default) 1 16-bit fcs checking used. crfcsswapinx bit 0 ppp fcs input swap control 0 for each received ppp frame byte at the input of the fcs generator, the bit- order is preserved (i.e., not swapped/reversed). (default). 1 for each received ppp frame byte at the input of the fcs generator, the bit- order is not preserved (i.e., is swapped/reversed, msb becomes lsb and vice-versa). - 180 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ability to detect an abort indication via alarm and interrupt generation. to force an abort of the current frame, the crpppabtgx register needs to be set to 1. an alarm, arpppabtdx, is generated when an abort indication is detected (i.e., receive 0x7d followed by 0x7e) on the receive side. ability to select type of padding mode used for decapsulation using crbcppdmodex register. processing of invalid ppp frames as per rfc 1662. detection of size (minimum and maximum) of ppp frame via alarm and interrupt generation. the minimum size of the received ppp frame (in octets) can be configured using the rrpppminflx register (i.e., the number of octets between the opening and closing flags). an alarm, arpppshterx, is generated when the size of received ppp frame is less than four (when using 16-bit fcs) or six (when using 32-bit fcs) octets and this frame is aborted. an alarm, arpppminerx, is generated when the size of the received ppp frame is greater than four (when using 16-bit fcs) or six (when using 32-bit fcs) octets but less than the value configured in rrpppminflx register. the maximum size of the received ppp frame payload informa- tion field (in octets) can be configured using the rrmaxflx register. an alarm, arpppmaxerx, is gener- ated when the size of the received ppp frame payload information field (in octets) exceeds the value configured in rrmaxflx register. ability to filter and extract ppp lcp/ncp control frames by the host is supported. a 64-byte buffer (using 64 rrlmix_ (8-0) registers) per mac is provided to store a single ppp lcp/ncp control frame for the host extraction. the msb bit (bit 8), when set to ? 1 ? , of each byte is a valid bit to indicate that the current byte (bits 7-0) is part of the ppp lcp/ncp control frame. this applies up to the first byte where msb = 0 (bit 8); all other bytes after and including the byte with msb = 0 are not a part of the received frame. the host is pro- vided with a ppp lcp/ncp control frame such that only the following processing have been performed: fcs check, byte de-stuffing and removal of flags. the srctlbx status register (which can be accessed by the host) is provided to indicate the empty/full state of the buffer. a reset of the buffer can be generated using the crctlbrstx register. this reset will clear the srctlbx status register (srctlbx=0) and enable a new management/control frame to be received. the rrplcpx register is used to configure the ppp pro- tocol field value to be checked in order to extract the ppp lcp control frame and the rrctlmaska1x reg- ister is used as a bit level mask that is applied to the crplcpx register. the rrpncpx register is used to crpppabtgx bit 9 ppp abort generation 0 no frame aborted. (default) 1 current frame under receive is aborted. crbcppdmodex bit 13 ppp padding mode control 0 a fixed padding mode is used. 1 no padding is used. (default) rrpppminflx(7-0) ppp frame size 0x04 - 0xff indicates minimum number of octets present in a received ppp frame between opening and closing flags. (default = 0x04 when using 16-bit fcs or 0x06 when using 32-bit fcs) rrmaxflx(15-0) ppp frame payload information field size 0x0001 - 0x0640 indicates maximum number of octets in a received ppp frame payload information field. (default = 0x0640) - 181 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers configure the ppp protocol field value to be checked in order to extract the ppp ncp control frame and the rrctlmaskb1x register is used as a bit level mask that is applied to the crpncpx register. below is an example of how the host can use this buffer: step 1: if the buffer is empty, srctlbx=0 and the host is not allowed to read for a new ppp lcp/ncp control frame. step 2: once the ppp lcp/ncp control frame has been received, the srctlbx status register is set (srctlbx=1) by the ethermap-3 plus and an alarm, arctlrxx, is generated to indicate that the present ppp lcp/ncp control frame is ready for extraction by the host. no further ppp lcp/ncp control frames may be written into the buffer (i.e., are discarded silently) until the srctlbx status register is cleared. if the received ppp lcp/ncp control frame is bigger than the buffer size, an alarm, arctlberrx, is generated and the buffer must be cleared/reset by the host. step 3: once the ppp lcp/ncp control frame has been extracted, the srctlbx status register is cleared (srctlbx=0) by the host. this is to indicate that a follow-on received ppp lcp/ncp control frame may be written into the buffer. srctlbx bit 0 ppp lcp/ncp control frame buffer status indication 0 buffer is empty and no new ppp lcp/ncp control frame has been received/stored. (default) 1 buffer is full with a new ppp lcp/ncp control frame received. crctlbrstx bit 0 ppp lcp/ncp control frame buffer reset control 0 buffer is not in reset state. (default) 1 buffer is in reset state. rrplcpx(15-0) ppp lcp control frame ppp protocol field contents 0x0000 - 0xffff indicates contents of the lcp control frame ppp protocol field that is checked against a received control frame for extraction to the host. this is used in conjunction with the rrctlmaska1 mask register. (default = 0xc021) rrctlmaska1x(15-0) ppp lcp control frame ppp protocol field contents mask 0x0000 - 0xffff mask value that is applied to the rrplcpx register contents to aid in the filtering process. when the mask bit is set (i.e., to a 1), the corresponding bit of the rrplcpx register is used for filtering. (default = 0xffff) rrpncpx(15-0) ppp ncp control frame ppp protocol field contents 0x0000 - 0xffff indicates contents of the ncp control frame ppp protocol field that is checked against a received control frame for extraction to the host. this is used in conjunction with the rrctlmaskb1 mask register. (default = 0x8031) rrctlmaskb1x(15-0) ppp ncp control frame ppp protocol field contents mask 0x0000 - 0xffff mask value that is applied to the rrpncpx register contents to aid in the filtering process. when the mask bit is set (i.e., to a 1), the corresponding bit of the rrpncpx register is used for filtering. (default = 0xffff) - 182 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ability to filter decapsulation of select ppp frames (i.e., frames with ppp protocol field=0x0031) that are received from sonet/sdh is provided using crbpdux register. reception of all ppp lcp/ncp control frames (i.e., control frames destined for extraction by host) are not affected by this register. maintains receive statistics counters. all ppp receive side statistic counters are described in table 60 . crbpdux bit 14 selective ppp frame decapsulation filter control 0 received frames from sonet/sdh, with ppp protocol field=0x0031, are allowed to be decapsulated. 1 received frames from sonet/sdh, with ppp protocol field=0x0031, are not allowed (i.e., frames are discarded) to be decapsulated. (default) - 183 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers sdram controller sdram memory interface this interface is used to allow the mapper to connect an external sdram memory module. the external sdram memory module is used for buffering of ethernet traffic in both directions. the sdram memory interface comprises of a 32-bit data bus, 13-bit address bus, 2-bit bank address bus, 3-bit command bus, input/output mask bus, sdram clock (100 mhz) and control enable signals. the sdram control block will interface to a dynamic random access memory containing up to 256 mbits. it will support a quad-bank sdram with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). the external sdram will be accessed as 4 banks of 2k/4k/8k rows by 256 columns by 32 bits. in the memory module selected, the precharge command period (trp) minimum value must be lower than 30 ns. read and write accesses to the external sdram are burst oriented using alternative bank switching; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with issuing an active command, which is then followed by a read or write command. the address bits issued together with the active command are used to select the bank and row to be accessed (ba(1-0) select the bank, addr(12-0) select the row). the address bits issued together with the read or write command are used to select the starting column location for the burst access. the sdram interface block will require programmable read or write burst lengths of 2 locations. an auto precharge function may be enabled, to initiate a self-timed row precharge, at the end of the burst sequence. the 128 mb sdram interface block may change the row/column address on every clock cycle, in order to achieve a high-speed, fully random access. one bank in precharged while accessing one of the other three banks, thus hiding the precharge cycles and providing high-speed, random-access operation. the 128 mb sdram control block will operate with 3.3v, low-power memory block. all inputs and outputs are lvttl-compatible. cas latency please refer to timing diagrams sdram_read, sdram_write. the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the sdram interface can be programmed for a latency of three clock cycles: this means that data will be sampled on the third rising edge after the read command is issued. bank/row activation please refer to timing diagrams sdram_read, sdram_write. the active command will be issued before any read or write. after issuing the active, the read or write command may be issued to the selected row, subject to the t rcd specification. the sdram block controller is designed for sdram having a t rcd (min) lower than 20 ns; with a clock rate of 100 mhz, this implies that a read or write command can be issued on the second rising edge after the active command was issued. - 184 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers commands the following commands can be issued by the sdram controller (see the table below): reset configuration of sdram controller upon reset the sdram controller is configured for a 4 bank 64 mbit sdram. the default configuration parameters are: sdram size: sdram_cfg = 0 for a 64 mbit sdram. auto refresh period: sdram_trfc = 7. sdram auto refresh period expressed in 8 periods of sysclk input: sdrarp = 155 (decimal) which creates a 24 s/row auto refresh period. this register must be changed to 78 (decimal) for a 12 s/row auto refresh period. precharge command period: sdram_trp = 2 (cannot be changed). power-up initialization delay: sdrtinit = 100. indicates 100 units of 100 periods of the sysclk input, in other words, 10000 times sysclk. it is required by the sdram prior to issuing any command other than a command inhibit or a nop. number of auto refresh performed during initialization (full sdram auto-refresh): sdrinit_ar_mbr = 8. note: a configured value of 'n' will provide 'n+1' auto refresh cycles during the initialization period. mode register default value: mbr_value = 0 000 011 0 001. configuration changes/initialization after power-up, or in order to change any of the sdram configuration parameter, the following procedure must be used: 1. set the resets register at address 19482h to 0091h. 2. configure the sdram control and interface registers in data sheet table 62 . 3. set and clear the sdram_init bit, bit 0 at address 1d600h. 4. set the resets register at address 19482h to 0000h. note: there is no time constraint between step 3 and step 4. all the configuration registers dedicated to the sdram controller are described in table 62 of the memory map. command name cs ras cas we mask addr ba notes command inhibit nop h x x x x x x no operation nop l h h h x x x active l l h h x bank/row read l h l h l/h bank/col write l h l l l/h bank/col valid precharge l l h l x code x auto or self refresh l l l h x x x load mode register l l l l x op-code x write enable l active write inhibit h high z - 185 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers microprocessor access to sdram here is the procedure to perform a write access to the sdram: write the data to write in the 2 sixteen-bits registers up_data2wrmsb (address 0x1d63a) and up_data2wrlsb (address 0x1d638). write the address to write in the up_addr2wrmsb (bits 6 to 0 of 0x1d636 register) and up_addr2wrlsb (16 bits of 0x1d634 register) registers. set to 1 the up_wraddr2wr register (bit 0 of 0x1d63e register). this bit is cleared by the chip at the end of the sdram write access. here is the procedure to perform a read access to the sdram: write the address to read in the up_addr2rdmsb (bits 6 to 0 of 0x1d632 register) and up_addr2rdlsb (16 bits of 0x1d630 register) registers. set to 1 the up_wraddr2rd register (bit 0 of 0x1d63c register). this bit is cleared at the end of the sdram read access. when the up_wraddr2rd is cleared, the data is available in the up_datardlsb register (0x1d620 address) for the lsb value and up_datardmsb register (0x1d622 address) for the msb value. all the registers to access to the sdram with the microprocessor are described into the tables 63 and 64 of the memory map. - 186 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers reset operation general four types of reset are available in this device, external lead controlled hardware reset, microprocessor controlled hardware reset, microprocessor soft reset and microprocessor controlled global performance counters reset. external lead controlled hardware reset the reset external lead activates the hardware reset. the actions are as follows: the configuration bits are in default state (all ethernet mac disabled, sdram 64 mb configuration, encapsulation/de-encapsulation in laps mode, all the vt/vc are not allocated to any vcg, the telecom bus interface is disabled). all the interrupt bit mask are in disabling state. all the performance counters are cleared. a 2 microsecond wait time must be observed after the external lead controlled hardware reset is asserted before which any microprocessor accesses can be made. microprocessor controlled hardware reset the reseth register provides the same reset action as the reset external lead, but is directly addressable through the microprocessor interface. this reset is activated by writing a 0x91 to bits 7-0 of the reseth register. the register is self-clearing. a 2 microsecond wait time must be observed after the microprocessor controlled hardware reset is asserted before which any microprocessor accesses can be made. the reseth function is not available in motorola 860 mode. microprocessor controlled soft reset sixteen soft reset are available in the device, eight for each direction (ethernet to sonet/sdh and sonet/sdh to ethernet). the tx_resetsx byte registers (bits 7-0 of registers 0x19486-0x19494) are corresponding to the software reset of the ethernet line #0 to #7 in the transmit direction. the rx_resetsx byte registers (bits 7-0 of registers 0x19496-0x194a4) are corresponding to the software reset of the vcg #0 to #7 in the receive direction. when the value of the byte register of each software reset is equal to 91 hex, it activates the corresponding software reset. the actions are as follows: all the internal logic is initialized no impact on the control/configuration registers or counters to clear the reset action, it is necessary to change the value of the corresponding software reset byte register or to perform an external lead controller hardware reset or to activate the microprocessor controlled hardware reset (reseth). microprocessor controlled global performance counter reset when the resetc byte register (bits 7-0 of register 0x19484) is equal to 91 hex, it activates the global performance counter reset. the main actions is to clear all the performance counters. to clear the reset action, it is necessary to change the value of the global performance counter reset byte register or to perform an external lead controlled hardware reset or to activate the microprocessor controlled hardware reset (reseth). the reset action can also be cleared by the global software reset or any of the 16 per channel software resets. - 187 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers telecom bus operation general when the ethermap-3 plus is configured for drop timing, the add bus is byte and multi-frame synchronous with the drop bus, although delayed by one byte time because of internal processing. for example, if a byte in the stm-1 vc-4 structure using tug-3, tu-12 mapping is to be added to the add bus, the time of its placement is derived from the drop bus timing, and from software instructions specifying which tu-12 number is being added. note that the tu-12 drop selection can be different than the add bus selection. an option is provided which enables the drop bus timing signals to be sent as outputs on the add bus. when the device is configured for add bus timing, the add bus data, parity, and add indicator can be either derived from the input add bus clock, c1j1v1, and spe signals, or derived from internally generated clock, c1j1v1, and spe signals, which are also provided as outputs. when the internal timing generator is used, all timing outputs are derived from rtclk. drop bus interface the drop bus consists of the following leads: input data (dd(7-0)), input clock (dclk), input parity (dpar), input c1, j1, and optional v1 marker pulses (dc1j1v1), input payload indication (dspe). the most significant bit (msb) of the input data is assigned to dd7. the msb is defined as the first bit received in a sonet/sdh byte (i.e., bit 1 in the sonet/sdh byte). the bus rate is 19.44 mhz for sts-3 and stm-1 operation. the sts-1 rate is not supported. the drop bus is monitored for loss of clock. the loss of drop clock alarm is alossdclk at bit 0 of register 0x198c6. drop bus parity selection the parity selection for the drop bus is according to the following table. a parity error is indicated by the parityerror alarm at bit 1 of register defects. other than an alarm indication, no action is taken by the ethermap-3 plus . parityeven (bit 0 of register 0x1d57a) paritymode (bit 1 of register 0x1d57a) drop bus parity selection 0 0 odd parity is calculated for the data input leads (dd(7-0)). 0 1 odd parity is calculated for the input leads consisting of data (dd(7-0)), c1, j1, and v1 marker pulses (dc1j1v1), and the payload indicator (dspe). - 188 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers add bus interface the add bus consists of the following leads: output data (ad(7-0)), output parity (apar), output add-to-bus indicator (add ) the timing information can be input or output: input/output clock (aclk), input/output c1, j1, and optional v1 marker pulses (ac1j1v1), input/output payload indication (aspe), the most significant bit (msb) of the output data is assigned to ad7. the msb is defined as the first bit transmitted in a sonet/sdh byte (i.e., bit 1 in the sonet/sdh byte). the bus rate is 19.44 mhz for sts-3 and stm-1 operation. the sts-1 rate is not supported. add bus timing modes the add bus interface configuration and timing modes are shown in the following table. the abust lead selects either the drop bus or the add bus as the timing source for the add bus, i.e., drop bus or add bus timing mode. the abte lead is enabled in drop bus timing mode and either enables or tristates the add bus clock, c1j1v1, and spe outputs. the ctbadd control bit is enabled in add bus timing mode and selects the add bus clock, c1j1v1, and spe signals to be either inputs or outputs. 1 0 even parity is calculated for the input leads consisting of data (dd(7-0)), c1, j1, and v1 marker pulses (dc1j1v1), and the payload indicator (dspe). 1 1 even parity is calculated for the data input leads (dd(7-0)). parityeven (bit 0 of register 0x1d57a) paritymode (bit 1 of register 0x1d57a) drop bus parity selection - 189 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers add bus parity selection the parity selection for the add bus is according to the following table. note that the timing mode selected for the add bus must be consistent with the parity mode selected. ctbadd (bit 0, register 0x194a8) lead abust lead abte add bus configuration and timing mode 0 low x add bus timing mode: the output leads consist of data (ad(7-0)), parity (adpar), and add indicator (add ). the input leads consist of clock (aclk), c1, j1, v1 marker pulses (ac1j1v1), and payload indicator (aspe). refer to figure 12 . 1 low x add bus timing mode: all leads are output leads consisting of data (ad(7-0)), parity (adpar), add indicator (add ), clock (aclk), c1, j1, v1 marker pulses (ac1j1v1), and payload indicator (aspe). refer to figure 14 . 0 high low drop bus timing mode: the output leads consist of data (ad(7-0)), parity (adpar), add indicator (add ), clock (aclk), c1, j1, v1 marker pulses (ac1j1v1), and payload indicator (aspe). the clock, c1j1v1 and spe signals are derived from the drop bus. the v1 pulse is derived from either the v1 pulse present in the drop bus c1j1v1 signal, or from the drop side h4 byte detectors. refer to figure 10 . 0 high high drop bus timing mode: the output leads consist of data (ad(7-0)), parity (adpar), and add indicator (add ). the clock (aclk), c1, j1, and v1 marker pulses (ac1j1v1), and the payload indicator (aspe) leads are tristated. the data, par- ity, and add indicator signals are derived from the drop bus clock, c1j1v1, and spe signals. refer to figure 8 . parityeven (bit 13, register 0x184c8) paritymode (bit 12, register 0x184c8) add bus parity selection 0 0 odd parity is calculated for the data output leads (ad(7-0)). 0 1 odd parity is calculated for the output leads consisting of data (ad(7-0)), c1, j1, and v1 marker pulses (ac1j1v1), and the payload indicator (aspe). - 190 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers add bus delay options for controlling the delay of the add-bus data, parity and add indicator, relative to either the add bus or drop bus timing signals (clock, c1j1v1 and spe) are shown in the following table. the control field 'timingdelay' is used to set the phase relationship between the timing reference signals and the add bus data, parity and add indicator outputs by up to fifteen extra clock cycles. in the drop bus timing mode where the add bus timing signals are output, there is a fixed relationship between the input and output timing determined by selecting the activeedge (rising or falling) per figure 10 and figure 11 . the timingdelay parameter is used to select the phase relationship of the output data, parity and add indicator with respect to the input timing; therefore timingdelay affects only the delay of add bus data with respect to drop bus timing signals in this mode. the delay of the add bus data can be adjusted to match a wide variety of conditions, making it easy to use the ethermap-3 plus device in applications involving other transwitch as well as non-transwitch products. note: when using multiple ethermap-3 plus devices on the same telecom bus, the user has several options for system configuration. for example, ethermap-3 plus #1 may operate in add bus master mode, and the remaining ethermap-3 plus devices will operate in add slave mode; the timing delay should be configured to 1 on all devices. additionally, since ethermap-3 plus #1 will output its timing and data on the rising edge of the clock, it is advisable to configure the sampling edge of the add bus of the other ethermap-3 plus devices to the falling edge. 1 0 even parity is calculated for the data output leads (ad(7-0)). 1 1 even parity is calculated for output leads consisting of data (ad(7-0)), c1, j1, and v1 marker pulses (ac1j1v1), and the payload indicator (aspe). timingdelay (bits 10-7, register 0x184c8) timing mode add bus delay 1-f drop bus; add bus timing outputs tristated. the delay of add bus data, parity, and add indicator from the drop bus timing can be programmed (from 1 to 15 clock cycles). 1-f drop bus; add bus timing outputs active. the delay of add bus data, parity, add indicator, c1j1v1, and spe from the drop bus timing can be programmed (from 1 to 15 clock cycles). 1-f add bus (slave); add bus timing signals are inputs. the delay of add bus data, parity, and add indicator from the add bus timing can be programmed (from 1 to 15 clock cycles). 0-f add bus (master); add bus timing signals are outputs. the delay of add bus data, parity, and add indicator from the add bus timing can be programmed (from 0 to 15 clock cycles). parityeven (bit 13, register 0x184c8) paritymode (bit 12, register 0x184c8) add bus parity selection - 191 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers telecom bus tributary activation/tri-state control a priority scheme has been implemented to control the tri-state and activation of tributaries on the telecom add bus. when a tributary is made active, it is no longer possible to tri-state associated lower order tributaries. to tri-state a tributary, it is necessary to tri-state all associated higher order tributaries. in this way, individual tributaries within a tributary group can be selectively tri-stated. vc-3/vc-4 the data, parity, and add indicator corresponding to a vc-3 can be forced to a high impedance state by setting control bit highz_au3 at bit 3 of register 0x184e8 (vc-3 #1), 0x184ea (vc-3 #2), or 0x184ec (vc-3 #3) to a 1. when operating in the au-4 mode (control bit au_mode, bit 0 in register 0x184cc is a 1), the data, parity, and add indicator for the vc-4 can be forced to a high impedance state by setting all three highz_au3 control bits to a 1. correspondingly, when the highz_au3 control bit(s) are set to 0, the vc-3 or vc-4 data, parity and add indicator are activated. tug-3 when operating in the au-4 mode (control bit au_mode, bit 0 in register 0x184cc is a 1), the data, parity, and add indicator corresponding to a tug-3 can be controlled as follows (note that all three highz_au3 control bits are set to the same value for au-4 mode, and corresponding to the values shown in the following table): tug-2 the data, parity, and add indicator corresponding to a tug-2 can be forced to a high impedance state by setting control bit highz at bit 1 of register 0x18480 (tug-2 #1), 0x18482 (tug-2 #2), 0x18484 (tug-2 #3), ... or 0x184a8 (tug-2 #21) to a 1, provided the corresponding highz_au3 control bit is set to a 1 (au-3 mode), or the corresponding highz_tug3 and all three highz_au3 control bits are set to a 1 (au-4 mode). setting a corresponding higher order tributary to the active state also activates the tug-2 independent of the tug-2 highz control bit setting. a tug-2 can be selectively activated by setting all corresponding higher order highz control bits to a 1, and setting the selected tug-2 highz control bit to a 0. tu-11/tu-12 the data, parity, and add indicator corresponding to a tu-11 can be forced to a high impedance state by setting control bit highz at bit 0 of register 0x18500 (tu-11 #1), 0x18502 (tu-11 #2), 0x18504 (tu-11 #3), ... or 0x185a6 (tu-11 #84) to a 1. all corresponding higher order tributaries must be set to the high impedance state. setting a corresponding higher order tributary to the active state also activates the tu-11 independent of the tu-11 highz control bit setting. a tu-11 can be selectively activated by setting all corresponding higher order highz control bits to a 1, and setting the selected tu-11 highz control bit to a 0. address bit 4 (highz_tug3) bit 3 (highz_au3) operation 0x184e8 (tug-3 #1), 0x184ea (tug-3 #2), 0x184ec (tug-3 #3) x 0 the data, parity, and add indicator are active for all vc-4 poh, stuff, and tug-3 byte times. 0 1 the data, parity, and add indicator are active for each tug-3 in which the highz_tug3 control bit is set to 0 (inactive for vc-4 poh and stuff byte times) 1 1 the data, parity, and add indicator are inactive for each tug-3 in which the highz_tug3 control bit is set to 1 (unless tug-2 or tu-12 tributaries within the tug-3 are activated, causing activation of the data, parity, and add indicator for those tributaries). - 192 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers the data, parity, and add indicator corresponding to a tu-12 can be forced to a high impedance state by setting control bit highz at bit 0 of register 0x18500 (tu-12 #1), 0x18502 (tu-12 #2), 0x18504 (tu-12 #3), ... or 0x185a6 (tu-12 #63) to a 1. all corresponding higher order tributaries must be set to the high impedance state. setting a corresponding higher order tributary to the active state also activates the tu-12 independent of the tu-12 highz control bit setting. a tu-12 can be selectively activated by setting all corresponding higher order highz control bits to a 1, and setting the selected tu-12 highz control bit to a 0. - 193 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers loop backs mac loopback the mac loopback is enabled by setting bit 8 at address 0x00000 to '1'. when this bit is set, the transmit outputs of one given mac are looped back to the receive inputs of the same mac. the mac will operate at the same speed as its attached phy device. if the phy is not connected, the mac will run at 10 mbps. when this loopback is selected, frames are transmitted to the client. in gmii mode only, if this loopback is selected, a 125 mhz clock must be provided to the tx_clk input lead. figure 56. mac loopback demapper mapper 1 0 vcg_x active mac loopback mac_x vcg_x telecom bus side ethernet side - 194 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers telecom bus loopbacks the ethermap-3 plus supports two types of telecom bus loopbacks: sonet/sdh line side loopback from receive to transmit telecom bus: the drop bus signals are looped into the add bus leads. all programmed delays between data and timing in the add telecom bus block are disregarded and all add bus signals become outputs regardless of the timing mode selected. also, when this loopback is selected: a. in add bus timing slave mode, the drop data will not be passed through to the decapsulation block to the tx mac. b. in add bus timing master mode and drop bus timing modes, data will be passed through to the downstream blocks. ethernet or local side loopback from transmit to receive telecom bus: the add bus signals are looped into the demapper block and signals on the drop bus are ignored. the add bus data is also passed on to the external signal leads. when this loopback is selected, the c2 overhead byte expected on the drop side must match the c2 transmitted on the add side. figure 57. telecom bus loopbacks loopbackactive (bit 6 of register 0x184c8) sonet/sdh line side loopback 0 disabled (default) 1 enabled loopbackactive (bit 0 of register 0x1f754) ethernet/local side loopback 0 disabled (default) 1enabled demapper mapper 1 1 0 0 drop bus add bus local side loopbackactive loopbackactive line side - 195 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers boundary scan introduction the boundary scan interface block provides a five-lead test access port (tap) that conforms to the ieee 1149.1 standard. this standard provides external boundary scan functions to read and write the external input/output leads from the tap for board and component test. the ieee 1149.1 standard defines the requirements of a boundary scan architecture that has been specified by the ieee joint test action group (jtag). boundary scan is a specialized scan architecture that provides observability and controllability for the interface leads of the device. as shown in figure 58 , one cell of a boundary scan register is assigned to each input or output lead to be observed or tested (bidirectional leads may have two cells). the boundary scan capability is based on a test access port (tap) controller, instruction and bypass registers, and a boundary scan register bordering the input and output leads. the boundary scan test bus interface consists of four input signals (test clock (tck), test mode select (tms), test data input (tdi) and test reset (trs ) and a test data output (tdo) output signal. boundary scan signal timing is shown in figure 38 . the tap controller receives external control information via a test clock (tck) signal and a test mode select (tms) signal, and sends control signals to the internal scan paths. detailed information on the operation of this state machine can be found in the ieee 1149.1 standard. the serial scan path architecture consists of an instruction register, a boundary scan register and a bypass register. these three serial registers are connected in parallel between the test data input (tdi) and test data output (tdo) signals, as shown in figure 58 . the boundary scan function can be reset and disabled by holding lead trs low. when boundary scan testing is not being performed the boundary scan register is transparent, allowing the input and output signals to pass to and from the ethermap-3 plus devices internal logic. during boundary scan testing, the boundary scan reg- ister may disable the normal flow of input and output signals to allow the device to be controlled and observed via scan operations. boundary scan operation the maximum frequency the ethermap-3 plus device will support for boundary scan is 10 mhz. the timing diagrams for the boundary scan interface leads are shown in figure 58 . the ethermap-3 plus device performs the following boundary scan test instructions: the extest test instruction provides the ability to test the connectivity of the ethermap-3 plus device to external circuitry. the sample/preload test instruction provides the ability to examine the values of the input and output pins without interfering with device operation, and to initialize the boundary scan register with new values for the next operation. the bypass test instruction provides the ability to bypass the ethermap-3 plus boundary scan and instruction registers. the idcode test instruction provides a unique device identification for the ethermap-3 plus device. the highz test instruction provides the ability to drive all 3-state outputs and bidirectional pins to their high impedance state. the clamp test instruction provides the ability to drive the component pins of the chip from the boundary scan register, while the bypass register is selected as the serial path between tdi and tdo. the component pins will not switch while the clamp instruction is selected. - 196 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers boundary scan reset specific control of the trs lead is required in order to ensure that the boundary scan logic does not interfere with normal device operation. this lead must either be held low, asserted low, or asserted low then high (pulsed low), to asynchronously reset the test access port (tap) controller during power-up of the ethermap- 3 plus . if boundary scan testing is to be performed and the lead is held low, then a pull-down resistor value should be chosen which will allow the tester to drive this lead high, but still meet the v il requirements listed in the input, output and input/output parameters section of this data sheet for worst case leakage currents of all devices sharing this pull-down resistor. boundary scan schematic figure 58. boundary scan schematic boundary scan chain a boundary scan description language (bsdl) source file is available via the products page of the transwitch internet world wide web site at www.transwitch.com . tap controller bypass register instruction register tdi tdo in out controls boundary scan serial test data core logic of ethermap-3 plus boundary scan register signal input and output leads 3 device idcode register 32-bit - 197 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers memory information for tables 10 through 12 and 35 through 308 access is as follows: rw=read/write, r/cow=read/clear on write, ro=read only, rr=read-reset wo=write only and cow=clear on write. please note that initial values for status registers can change immediately after reset. table 9: memory map overview table / offset functional block description ta b l e 1 8 - table 23 offset = 0x00000 ethernet interface port #1 mac for smii port #1 and gmii interface configuration registers ta b l e 1 3 - table 17 offset = 0x00000 ethernet interface port #1 mac for smii port #1 and gmii interface status registers ta b l e 1 8 - table 23 offset = 0x02000 ethernet interface port #2 mac for smii port #2 configuration registers ta b l e 1 3 - table 17 offset = 0x02000 ethernet interface port #2 mac for smii port #2 status registers ta b l e 1 8 - table 23 offset = 0x04000 ethernet interface port #3 mac for smii port #3 configuration registers ta b l e 1 3 - table 17 offset = 0x04000 ethernet interface port #3 mac for smii port #3 status registers ta b l e 1 8 - table 23 offset = 0x06000 ethernet interface port #4 mac for smii port #4 configuration registers ta b l e 1 3 - table 17 offset = 0x06000 ethernet interface port #4 mac for smii port #4 status registers ta b l e 1 8 - table 23 offset = 0x08000 ethernet interface port #5 mac for smii port #5 configuration registers ta b l e 1 3 - table 17 offset = 0x08000 ethernet interface port #5 mac for smii port #5 status registers ta b l e 1 8 - table 23 offset = 0x0a000 ethernet interface port #6 mac for smii port #6 configuration registers ta b l e 1 3 - table 17 offset = 0x0a000 ethernet interface port #6 mac for smii port #6 status registers ta b l e 1 8 - table 23 offset = 0x0c000 ethernet interface port #7 mac for smii port #7 configuration registers ta b l e 1 3 - table 17 offset = 0x0c000 ethernet interface port #7 mac for smii port #7 status registers ta b l e 1 8 - table 23 offset = 0x0e000 ethernet interface port #8 mac for smii port #8 configuration registers ta b l e 1 3 - table 17 offset = 0x0e000 ethernet interface port #8 mac for smii port #8 status registers ta b l e 2 4 - table 29 ethernet mii management ta b l e 3 0 ethernet interface ports 1-8 general configuration ta b l e 3 1 - table 34 ethernet interface ports 1-8 alarms of the 8 ethernet interfaces ta b l e 6 5 ta b l e 7 1 ta b l e 7 2 transmit virtual concatenation virtual concatenation configuration per vcg and per member in low/high order ta b l e 7 3 transmit lcas lcas configuration per vcg and per member in low/high order - 198 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ta b l e 7 5 transmit virtual concatenation status information per vcg and per member in low/high order ta b l e 6 6 - table 70 transmit lcas lcas alarm/mask/interruption per vcg and per member in low/high order table 179 vci_rx_vc4_poh vc-4 poh monitor table 238 - ta b l e 2 4 2 vci_tx_vc3_poh vc-3 poh generator ta b l e 4 8 ta b l e 4 9 ta b l e 5 0 ta b l e 5 3 ta b l e 5 4 receive decapsulation block mac#1-8 configuration of the decapsulation blocks ta b l e 5 5 receive decapsulation block mac#1-8 control frame buffer for decapsulation blocks ta b l e 5 6 - table 60 receive decapsulation block mac#1-8 alarms, masks, interrupts and perfor- mance counters for all decapsulation blocks ta b l e 5 1 ta b l e 5 2 ta b l e 6 1 receive decapsulation block mac#1-8 status of the decapsulation blocks table 109 vci_tx_timing_generator table 162 vci_tx_lo_alarm_port transmit low order ring/alarm interface port table 294 vci_tx_combus transmit (add) telecom bus interface ta b l e 3 5 - table 39 transmit encapsulation block mac#1-8 configuration of the encapsulation blocks ta b l e 4 0 transmit encapsulation block mac#1-8 control frame buffer for encapsulation blocks ta b l e 4 1 - table 47 transmit encapsulation block mac#1-8 status, alarms, performance counters, interrupts of encapsulation blocks ta b l e 7 6 ta b l e 8 1 ta b l e 8 2 receive virtual concatenation and lcas processing block virtual concatenation configuration per vcg and per member in low/high order & lcas configuration ta b l e 7 7 - table 80 receive virtual concatenation and lcas processing block alarm, mask, interrupts ta b l e 8 3 - table 85 receive virtual concatenation and lcas processing block status information per vcg and per member in low/high order ta b l e 9 1 ta b l e 9 8 ethernet buffering and flow control in tx ethernet to sonet/sdh direction configuration registers ta b l e 9 2 - table 97 ta b l e 9 9 - table 103 ethernet buffering and flow control in tx ethernet to sonet/sdh direction status, alarm, interrupt, performance counters table 168 vci_tx_alarm_port transmit high order ring/alarm interface port table 210 vci_rx_tu3_ptr tu-3 pointer tracker table 236 vci_tx_tu3_ptr tu-3 pointer generator table 238 - ta b l e 2 4 2 vci_tx_vc4_poh vc-4 poh generator table 163 vci_rx_lo_alarm_port receive low order ring/alarm interface port table 9: memory map overview table / offset functional block description - 199 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers notes: 1. dclk clock is always needed for accessing the registers of the vci_rx_combus virtual component (or "block"). dclk clock is needed for accessing all the blocks in the mapper/demapper part when in drop bus timing mode. in these two cases, when the dclk clock is missing, an acknowledge is generated after 256 rtclk clock cycles. 2. in all timing modes, when a wrong (not existent) address is accessed, an acknowledge is generated after or 256 rtclk clock cycles. this is not true for the mac block: if wrong (not existent) address within the mac block is accessed, no acknowledge is generated. 3. during the initial configuration of the device, a) drop timing mode: the input dclk will be required; b) add slave timing mode: the input aclk will be required; c) add master timing mode: the output aclk must be pulled high with a weak pull-up (~10k ohm). after a hard reset, the first microprocessor access must be to set the ctbadd register to 1. at this moment, the ethermap-3 plus will be able to drive the clock. table 167 vci_rx_alarm_port receive high order ring/alarm interface port ta b l e 8 6 ethernet frame format block ethernet to sonet/sdh direction configuration registers ta b l e 8 7 - table 90 ethernet frame format block ethernet to sonet/sdh direction alarms, status, interrupt, performance counters ta b l e 1 0 - table 12 general configuration of ethermap-3 plus device id, general status, hardware/soft- ware reset table 212 vci_au_retimer high order retimer table 267 vci_rx_combus receive (drop) telecom bus interface 0x1d240 vci_ettc transmit ethernet fifo controller table 104 vci_mapdemap table 166 vci_vtmpr_ic table 261 vci_c3_to_aug1_ic ta b l e 6 2 vci_ramc sdram controller table 223 vci_l3xcon sts-1/vc-3/tug-3 time slot inter- change blocks table 305 vci_combus_ic table 308 vci_vtmp_top_ic table 135 vci_lo_demapper_poh low order poh monitor table 116 vci_lo_mapper table 131 vci_lo_demapper table 182 vci_rx_vc3_poh vc-3 poh monitor table 250 vci_l3_retimer tu-3 retimer table 9: memory map overview table / offset functional block description - 200 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers general device registers table 10 through 12 - general configuration and status of the device table 10: general device configuration (rw) address bit hw symbol init description 0x19480 7-0 reseth 0x0000 global hard reset 0x91: reset state, self-clearing others: non reset state a 2 microsecond wait time must be observed after 0x91 is written, before which any other microprocessor accesses can be made. this function is not available in motorola 860 mode. 0x19482 7-0 resets 0x0000 global soft reset 0x19484 7-0 resetc 0x0000 performance counter reset 0x91: reset state others: non reset state 0x19486 ? 0x19494 7-0 tx_resetsx 0x0000 tx soft reset for vcg channels 0-7 (ethernet to sonet direction) 0x91: reset state others: non reset state this reset must be activated for a minimum of 16 s. 0x19496 ? 0x194a4 7-0 rx_resetsx 0x0000 rx soft reset for vcg channels 0-7 (sonet to ethernet direction) 0x91: reset state others: non reset state this reset must be activated for a minimum of 16 s. 0x194a6 0 ccrov 0x0000 non-saturating mode for the performance counters 1: non saturating mode ==> roll over to 0 0: saturating mode. performance counters are cleared on read. 0x194a8 0 ctbadd 0x0000 add bus timing configuration mode (linked with abust and abte inputs) 0: add telecom bus in slave mode 1: add telecom bus in master mode 0x194aa ? 0x194c8 15-0 internalx (0-15) 0x0000 reserved table 11: general device status (ro) address bit hw symbol init description 0x19440 0 gmii/smii 0x0000 status of the gmii/smii input pin 0x19442 0 highz 0x0000 status of the highz input pin 0x19444 0 abte 0x0000 status of the abte input pin 0x19446 0 abust 0x0000 status of the abust input pin 0x19448 0 phy/mac 0x0000 status of the phy/mac input pin 0x1944a 0 sync_dir 0x0000 status of the sync_dir input pin table 12: id registers (ro) address bit hw symbol init description 0x19400 15-0 manufactureid 0x00d7 manufacture id 0x19402 15-0 partnumber 0x4236 part number 0x19404 15-0 versionmask see description device version level - device mask level 0x0001 = txc-04236-aibg, revision b - 201 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ethernet mac registers the mac tables shown below are for smii port one, and the gmii interface. the starting address for smii port two is offset by 0x02000, the starting address for smii port three is offset by 0x04000, the starting address for smii port four is offset by 0x06000, the starting address for smii port five is offset by 0x08000, the starting address for smii port six is offset by 0x0a000, the starting address for smii port seven is offset by 0x0c000, and the starting address for smii port eight is offset by 0x0e000. all mac registers must be accessed as 16-bit register pairs, even when only a 16-bit register access is needed. registers 0x00000 and 0x00002 are a pair, registers 0x00004 and 0x00006 are a pair, ....etc. for writes, the 16 msbs (address bit 0 is high) must be written first. for reads, the 16 lsbs (address bit 0 is low) must be read first. tables 13 through 17 - status information of the mac table 13: mac combined receive and transmit counters address bit hw symbol init description 0x01080 15-0 tr64_lower 0x0000 transmit and receive 64 byte frame counter (lower 16 bits): incremented for each good or bad frame transmitted and received which is 64 bytes in length inclusive (excluding framing bits but including fcs bytes). 0x01082 8-0 tr64_upper 0x0000 transmit and receive 64 byte frame counter (upper 9 bits): incremented for each good or bad frame transmitted and received which is 64 bytes in length inclusive (excluding framing bits but including fcs bytes). 0x01084 15-0 tr127_lower 0x0000 transmit and receive 65 to 127 byte frame counter (lower 16 bits): incremented for each good or bad frame transmitted and received which is 65 to 127 bytes in length inclusive (excluding framing bits but including fcs bytes). 0x01086 8-0 tr127_upper 0x0000 transmit and receive 65 to 127 byte frame counter (upper 9 bits): incremented for each good or bad frame transmitted and received which is 65 to 127 bytes in length inclusive (excluding framing bits but including fcs bytes). 0x01088 15-0 tr255_lower 0x0000 transmit and receive 128 to 255 byte frame counter (lower 16 bits): incremented for each good or bad frame transmitted and received which is 128 to 255 bytes in length inclusive (excluding framing bits but including fcs bytes). 0x0108a 8-0 tr255_upper 0x0000 transmit and receive 128 to 255 byte frame counter (upper 9 bits): incremented for each good or bad frame transmitted and received which is 128 to 255 bytes in length inclusive (excluding framing bits but including fcs bytes). 0x0108c 15-0 tr511_lower 0x0000 transmit and receive 256 to 511 byte frame counter (lower 16 bits): incremented for each good or bad frame transmitted and received which is 256 to 511 bytes in length inclusive (excluding framing bits but including fcs bytes). 0x0108e 8-0 tr511_upper 0x0000 transmit and receive 256 to 511 byte frame counter (upper 9 bits): incremented for each good or bad frame transmitted and received which is 256 to 511 bytes in length inclusive (excluding framing bits but including fcs bytes). 0x01090 15-0 tr1k_lower 0x0000 transmit and receive 512 to 1023 byte frame counter (lower 16 bits): incremented for each good or bad frame transmitted and received which is 512 to 1023 bytes in length inclusive (excluding framing bits but including fcs bytes). 0x01092 8-0 tr1k_upper 0x0000 transmit and receive 512 to 1023 byte frame counter (upper 9 bits): incremented for each good or bad frame transmitted and received which is 512 to 1023 bytes in length inclusive (excluding framing bits but including fcs bytes). 0x01094 15-0 trmax_lower 0x0000 transmit and receive 1024 to 1518 byte frame counter (lower 16 bits): incre- mented for each good or bad frame transmitted and received which is 1024 to 1518 bytes in length inclusive (excluding framing bits but including fcs bytes). 0x01096 8-0 trmax_upper 0x0000 transmit and receive 1024 to 1518 byte frame counter (upper 9 bits): incremented for each good or bad frame transmitted and received which is 1024 to 1518 bytes in length inclusive (excluding framing bits but including fcs bytes). - 202 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x01098 15-0 trmgv_lower 0x0000 transmit and receive 1519 to 1522 byte vlan frame counter (lower 16 bits): incremented for each good or bad frame transmitted and received which is 1024 to 1518 bytes in length inclusive (excluding framing bits but including fcs bytes). 0x0109a 8-0 trmgv_upper 0x0000 transmit and receive 1519 to 1522 byte vlan frame counter (upper 9 bits): incre- mented for each good or bad frame transmitted and received which is 1024 to 1518 bytes in length inclusive (excluding framing bits but including fcs bytes). table 14: mac receive counters address bit hw symbol init description 0x0109c 15-0 rbyt_lower 0x0000 receive byte counter (lower 16 bits): the statistic counter register is incremented by the byte count of frames received with 0 to 1518 bytes (i.e., includes all overhead bytes such as da/sa/tl), including those in bad packets, excluding framing bits (i.e., preamble, sfd) but including fcs bytes. 0x0109e 11-0 rbyt_upper 0x0000 receive byte counter (upper 12 bits): the statistic counter register is incremented by the byte count of frames received with 0 to 1518 bytes (i.e., includes all overhead bytes such as da/sa/tl), including those in bad packets, excluding framing bits (i.e., preamble, sfd) but including fcs bytes. 0x010a0 15-0 rpkt_lower 0x0000 receive packet counter (lower 16 bits): incremented for each frame received packet (including bad packets, all unicast, broadcast, and multicast packets). 0x010a2 8-0 rpkt_upper 0x0000 receive packet counter (upper 9 bits): incremented for each frame received packet (including bad packets, all unicast, broadcast, and multicast packets). 0x010a4 15-0 rfcs_lower 0x0000 receive fcs error counter (lower 16 bits): incremented for each frame received that has a integral 64 to 1518 length and contains a frame check sequence error. 0x010a6 1-0 rfcs_upper 0x0000 receive fcs error counter (upper 2 bits): incremented for each frame received that has a integral 64 to 1518 length and contains a frame check sequence error. 0x010a8 15-0 rmca_lower 0x0000 receive multicast packet counter (lower 16 bits): incremented for each multicast good frame of lengths 64 to 1518 (non vlan) or 1522 (vlan) excluding broadcast frames. this does not look at range/length errors. 0x010aa 8-0 rmca_upper 0x0000 receive multicast packet counter (upper 9 bits): incremented for each multicast good frame of lengths 64 to 1518 (non vlan) or 1522 (vlan) excluding broadcast frames. this does not look at range/length errors. 0x010ac 15-0 rbca_lower 0x0000 receive broadcast packet counter (lower 16 bits): incremented for each broadcast good frame of lengths 64 to 1518 (non vlan) or 1522 (vlan) excluding multicast frames. this does not look at range/length errors. 0x010ae 8-0 rbca_upper 0x0000 receive broadcast packet counter (upper 9 bits): incremented for each broadcast good frame of lengths 64 to 1518 (non vlan) or 1522 (vlan) excluding multicast frames. this does not look at range/length errors. 0x010b0 15-0 rxcf_lower 0x0000 receive control frame packet counter (lower 16 bits): incremented for each mac control frame received (pause and unsupported). 0x010b2 1-0 rxcf_upper 0x0000 receive control frame packet counter (upper 2 bits): incremented for each mac control frame received (pause and unsupported). 0x010b4 15-0 rxpf_lower 0x0000 receive pause frame packet counter (lower 16 bits): incremented each time a valid pause mac control frame is received. 0x010b6 1-0 rxpf_upper 0x0000 receive pause frame packet counter (upper 2 bits): incremented each time a valid pause mac control frame is received. 0x010b8 15-0 rxuo_lower 0x0000 receive unknown opcode counter (lower 16 bits): incremented each time a mac control frame is received which contains an opcode other than a pause. 0x010ba 1-0 rxuo_upper 0x0000 receive unknown opcode counter (upper 2 bits): incremented each time a mac control frame is received which contains an opcode other than a pause. table 13: mac combined receive and transmit counters address bit hw symbol init description - 203 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x010bc 15-0 raln_lower 0x0000 receive alignment error counter (lower 16 bits): incremented for each received frame from 64 to 1518 (non vlan) or 1522 (vlan) which contains an invalid fcs and is not an integral number of bytes. 0x010be 1-0 raln_upper 0x0000 receive alignment error counter (upper 2 bits): incremented for each received frame from 64 to 1518 (non vlan) or 1522 (vlan) which contains an invalid fcs and is not an integral number of bytes. 0x010c0 15-0 rflr_lower 0x0000 receive frame length error counter (lower 16 bits): incremented for each frame received in which the 802.3 length field did not match the number of data bytes actually received (46 - 1500 bytes). the counter is not incremented if the length field is not a valid 802.3 length, such as an ethertype value. 0x010c2 1-0 rflr_upper 0x0000 receive frame length error counter (upper 2 bits): incremented for each frame received in which the 802.3 length field did not match the number of data bytes actually received (46 - 1500 bytes). the counter is not incremented if the length field is not a valid 802.3 length, such as an ethertype value. 0x010c4 15-0 rcde_lower 0x0000 receive code error counter (lower 16 bits): incremented each time a valid carrier was present and at least one invalid data symbol was detected. 0x010c6 1-0 rcde_upper 0x0000 receive code error counter (upper 2 bits): incremented each time a valid carrier was present and at least one invalid data symbol was detected. 0x010c8 15-0 rcse_lower 0x0000 receive false carrier counter (lower 16 bits): incremented each time a false car- rier is detected during idle, as defined by a 1 on rx_er and an '0xe' on rxd. the event is reported along with the statistics generated on the next received frame. only one false carrier condition can be detected and logged between frames. 0x010ca 1-0 rcse_upper 0x0000 receive false carrier counter (upper 2 bits): incremented each time a false carrier is detected during idle, as defined by a 1 on rx_er and an '0xe' on rxd. the event is reported along with the statistics generated on the next received frame. only one false carrier condition can be detected and logged between frames. 0x010cc 15-0 rund_lower 0x0000 receive undersize packet counter (lower 16 bits): incremented each time a frame is received which is less than 64 bytes in length and contains a valid fcs and were otherwise well formed. this does not look at range length errors. 0x010ce 1-0 rund_upper 0x0000 receive undersize packet counter (upper 2 bits): incremented each time a frame is received which is less than 64 bytes in length and contains a valid fcs and were otherwise well formed. this does not look at range length errors. 0x010d0 15-0 rovr_lower 0x0000 receive oversize packet counter (lower 16 bits): incremented each time a frame is received which exceeded 1518 (non vlan) or 1522 (vlan) and contains a valid fcs and were otherwise well formed. this does not look at range length errors. 0x010d2 1-0 rovr_upper 0x0000 receive oversize packet counter (upper 2 bits): incremented each time a frame is received which exceeded 1518 (non vlan) or 1522 (vlan) and contains a valid fcs and were otherwise well formed. this does not look at range length errors. 0x010d4 15-0 rfrg_lower 0x0000 receive fragments counter (lower 16 bits): incremented for each frame received which is less than 64 bytes in length and contains an invalid fcs, includes integral and non-integral lengths. 0x010d6 1-0 rfrg_upper 0x0000 receive fragments counter (upper 2 bits): incremented for each frame received which is less than 64 bytes in length and contains an invalid fcs, includes integral and non-integral lengths. 0x010d8 15-0 rjbr_lower 0x0000 receive jabber counter (lower 16 bits): incremented for frames received which exceed 1518 (non vlan) or 1522 (vlan) bytes and contains an invalid fcs, includes alignment errors. 0x010da 1-0 rjbr_upper 0x0000 receive jabber counter (upper 2 bits): incremented for frames received which exceed 1518 (non vlan) or 1522 (vlan) bytes and contains an invalid fcs, includes alignment errors. 0x010dc 15-0 reserved 0x0000 reserved table 14: mac receive counters address bit hw symbol init description - 204 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x010de 1-0 reserved 0x0000 reserved table 15: mac transmit counters address bit hw symbol init description 0x010e0 15-0 tbyt_lower 0x0000 transmit byte counter (lower 16 bits): incremented by the number of bytes that were put on the wire including fragments of frames that were involved with collisions. this count does not include preamble/sfd or jam bytes. 0x010e2 11-0 tbyt_upper 0x0000 transmit byte counter (upper 12 bits): incremented by the number of bytes that were put on the wire including fragments of frames that were involved with collisions. this count does not include preamble/sfd or jam bytes. 0x010e4 15-0 tpkt_lower 0x0000 transmit packet counter (lower 16 bits): incremented for each transmitted packet (including bad packets, excessive deferred packets, excessive collision packets, late col- lision packets, all unicast, broadcast, and multicast packets). 0x010e6 8-0 tpkt_upper 0x0000 transmit packet counter (upper 9 bits): incremented for each transmitted packet (including bad packets, excessive deferred packets, excessive collision packets, late col- lision packets, all unicast, broadcast, and multicast packets). 0x010e8 15-0 tcma_lower 0x0000 transmit multicast packet counter (lower 16 bits): incremented for each multicast valid frame transmitted (excluding broadcast frames). 0x010ea 8-0 tcma_upper 0x0000 transmit multicast packet counter (upper 9 bits): incremented for each multicast valid frame transmitted (excluding broadcast frames). 0x010ec 15-0 tcba_lower 0x0000 transmit broadcast packet counter (lower 16 bits): incremented for each broadcast frame transmitted (excluding multicast frames). 0x010ee 8-0 tcba_upper 0x0000 transmit broadcast packet counter (upper 9 bits): incremented for each broadcast frame transmitted (excluding multicast frames). 0x010f0 15-0 txpf_lower 0x0000 transmit pause frame packet counter (lower 16 bits): incremented each time a valid pause mac control frame is transmitted. 0x010f2 1-0 txpf_upper 0x0000 transmit pause frame packet counter (upper 2 bits): incremented each time a valid pause mac control frame is transmitted. 0x010f4 15-0 tdfr_lower 0x0000 transmit deferral packet counter (lower 16 bits): incremented each time a packet is deferred on its first transmission attempt. does not include frames involved in collisions. 0x010f6 1-0 tdfr_upper 0x0000 transmit deferral packet counter (upper 2 bits): incremented each time a packet is deferred on its first transmission attempt. does not include frames involved in collisions. 0x010f8 15-0 tedf_lower 0x0000 transmit excessive deferral packet counter (lower 16 bits): incremented each time a frame is aborted for an excessive period of time 0x010fa 1-0 tedf_upper 0x0000 transmit excessive deferral packet counter (upper 2 bits): incremented each time a frame is aborted for an excessive period of time 0x010fc 15-0 tscl_lower 0x0000 transmit single collision packet counter (lower 16 bits): incremented each time a packet is transmitted which experienced exactly one collision during transmission 0x010fe 1-0 tscl_upper 0x0000 transmit single collision packet counter (upper 2 bits): incremented each time a packet is transmitted which experienced exactly one collision during transmission 0x01100 15-0 tmcl_lower 0x0000 transmit multiple collision packet counter (lower 16 bits): incremented each time a frame which experienced 2-15 collisions (including any late collisions) during transmis- sion as defined in the retransmission maximum value. 0x01102 1-0 tmcl_upper 0x0000 transmit multiple collision packet counter (upper 2 bits): incremented each time a frame which experienced 2-15 collisions (including any late collisions) during transmis- sion as defined in the retransmission maximum value. table 14: mac receive counters address bit hw symbol init description - 205 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x01104 15-0 tlcl_lower 0x0000 transmit late collision packet counter (lower 16 bits): incremented each time a packet which experienced a late collision during a transmission attempt. 0x01106 1-0 tlcl_upper 0x0000 transmit late collision packet counter (upper 2 bits): incremented each time a packet which experienced a late collision during a transmission attempt. 0x01108 15-0 txcl_lower 0x0000 transmit excessive collision packet counter (lower 16 bits): incremented each time a packet experienced 16 collisions during transmission and was aborted. 0x0110a 1-0 txcl_upper 0x0000 transmit excessive collision packet counter (upper 2 bits): incremented each time a packet experienced 16 collisions during transmission and was aborted. 0x0110c 15-0 tncl_lower 0x0000 transmit total collision packet counter (lower 16 bits): incremented by the number of collisions experienced during the transmission of a frame as defined as the simulta- neous presence of signals in the transmit and receive. this register does not include collisions that occur in an excessive collision condition. 0x011oe 1-0 tncl_upper 0x0000 transmit total collision packet counter (upper 2 bits): incremented by the number of col- lisions experienced during the transmission of a frame as defined as the simultaneous presence of signals in the transmit and receive. this register does not include colli- sions that occur in an excessive collision condition. 0x01110 15-0 reserved 0x0000 reserved 0x01112 1-0 reserved 0x0000 reserved 0x01114 15-0 reserved 0x0000 reserved 0x01116 1-0 reserved 0x0000 reserved 0x01118 15-0 tjbr_lower 0x0000 transmit jabber frame counter (lower 16 bits): incremented for each oversized trans- mitted frame with an incorrect fcs value. 0x0111a 1-0 tjbr_upper 0x0000 transmit jabber frame counter (upper 2 bits): incremented for each oversized transmit- ted frame with an incorrect fcs value. 0x0111c 15-0 tfcs_lower 0x0000 transmit fcs error counter (lower 16 bits): incremented for every valid sized packet with an incorrect fcs value. 0x0111e 1-0 tfcs_upper 0x0000 transmit fcs error counter (upper 2 bits): incremented for every valid sized packet with an incorrect fcs value. 0x01120 15-0 txcf_lower 0x0000 transmit control frame counter (lower 16 bits): incremented for every valid size frame with a type field signifying a control frame. 0x01122 1-0 txcf_upper 0x0000 transmit control frame counter (upper 2 bits): incremented for every valid size frame with a type field signifying a control frame. 0x01124 15-0 tovr_lower 0x0000 transmit oversize frame counter (lower 16 bits): incremented for each oversized trans- mitted frame with an correct fcs value. 0x01126 1-0 tovr_upper 0x0000 transmit oversize frame counter (upper 2 bits): incremented for each oversized trans- mitted frame with an correct fcs value. 0x01128 15-0 tund_lower 0x0000 transmit undersize frame counter (lower 16 bits): incremented for every frame less then 64 bytes, with a correct fcs value. when in half-duplex mode, the actual transmit undersize frame count is determined by tund_lower (register 0x01128), tund_upper (register 0x0112a), txcl_lower (register 0x01108), txcl_upper (register 0x0110a), tlcl_lower (register 0x01104) and tlcl_upper (register 0x01106). 0x0112a 1-0 tund_upper 0x0000 transmit undersize frame counter (upper 2 bits): incremented for every frame less then 64 bytes, with a correct fcs value. when in half-duplex mode, the actual transmit undersize frame count is determined by tund_lower (register 0x01128), tund_upper (register 0x0112a), txcl_lower (register 0x01108), txcl_upper (register 0x0110a), tlcl_lower (register 0x01104) and tlcl_upper (register 0x01106). table 15: mac transmit counters address bit hw symbol init description - 206 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 16: mac interface status registers note: carry register bits are cleared on carry register write while respective bit is asserted. when one of the below carry mask bits are set to zero, the corresponding interrupt bit is allowed to cause interrupt indications on output carry. 0x0112c 15-0 tfrg_lower 0x0000 transmit fragment counter (lower 16 bits): incremented for every frame less then 64 bytes, with a incorrect fcs value. 0x0112e 1-0 tfrg_upper 0x0000 transmit fragment counter (upper 2 bits): incremented for every frame less then 64 bytes, with a incorrect fcs value. address bit hw symbol init description 0x0003c 0 jabber 0x0000 jabber: when read as a '1', the mac has detected a jabber condition. when read as a '0', the mac has not detected a jabber condition. this bit latches high. 1 sqe error sqe error: when read as a '1', the mac has detected an sqe error. when read as a '0', the mac has not detected an sqe error. this bit latches high. 2 loss of carrier loss of carrier: when read as a '1', the mac has detected a loss of carrier. when read as a '0', the mac has not detected a loss of carrier. this bit latches high. 3 reserved 4 speed speed: when read as a '1', the serial mii phy is operating at 100 mbit/s mode. when read as a '0', the serial mii phy is operating at 10 mbit/s. 5 full duplex full duplex: when read as a '1', the serial mii phy is operating in full duplex mode. when read as a '0', the serial mii phy is operating in half duplex mode. 6 link ok link ok: when read as a '1', the serial mii phy has detected a valid link. when read as a '0', the serial mii phy has not detected a valid link. 7 jabber jabber: when read as a '1', the serial mii phy has detected a jabber condition on the link. when read as a '0', the serial mii phy has not detected a jabber condition. 8 clash clash: when read as a '1', the serial mii module is in mac to mac mode with the partner in 10 mbit/s and/or half duplex mode indicative of a configuration error. when read as a '0', the serial mii module is either in phy mode or in a properly configured mac to mac mode. 9 excess defer excess defer: this bit sets when the mac excessively defers a trans- mission. it clears when read. this bit latches high. its default is '0'. 15-10 reserved table 15: mac transmit counters address bit hw symbol init description - 207 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 17: mac carry and carry mask registers address bit hw symbol init description 0x01130 0 reserved 0 reserved 1 c1rjb 0 carry register 1 rjbr counter carry bit 2 c1rfr 0 carry register 1 rfrg counter carry bit 3 c1rov 0 carry register 1 rovr counter carry bit 4 c1run 0 carry register 1 rund counter carry bit 5 c1rcs 0 carry register 1 rcse counter carry bit 6 c1rcd 0 carry register 1 rcde counter carry bit 7 c1rfl 0 carry register 1 rflr counter carry bit 8 c1ral 0 carry register 1 raln counter carry bit 9 c1rxu 0 carry register 1 rxuo counter carry bit 10 c1rxp 0 carry register 1 rxpf counter carry bit 11 c1rxc 0 carry register 1 rxcf counter carry bit 12 c1rbc 0 carry register 1 rbca counter carry bit 13 c1rmc 0 carry register 1 rmca counter carry bit 14 c1rfc 0 carry register 1 rfcs counter carry bit 15 c1rpk 0 carry register 1 rpkt counter carry bit 0x01132 0 c1rby 0 carry register 1 rbyt counter carry bit 9 c1mgv 0 carry register 1 trmgv counter carry bit 10 c1max 0 carry register 1 trmax counter carry bit 11 c11k 0 carry register 1 tr1k counter carry bit 12 c1511 0 carry register 1 tr511 counter carry bit 13 c1255 0 carry register 1 tr255 counter carry bit 14 c1127 0 carry register 1 tr127 counter carry bit 15 c164 0 carry register 1 tr64 counter carry bit - 208 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x01134 0 reserved 0 reserved 1 reserved 0 reserved 2 c2tnc 0 carry register 2 tncl counter carry bit 3 c2txc 0 carry register 2 txcl counter carry bit 4 c2tlc 0 carry register 2 tlcl counter carry bit 5 c2tma 0 carry register 2 tmal counter carry bit 6 c2tsc 0 carry register 2 tscl counter carry bit 7 c2ted 0 carry register 2 tedf counter carry bit 8 c2tdf 0 carry register 2 tdfr counter carry bit 9 c2tpf 0 carry register 2 txpf counter carry bit 10 c2tbc 0 carry register 2 tbca counter carry bit 11 c2tmc 0 carry register 2 tmca counter carry bit 12 c2tpk 0 carry register 2 tpkt counter carry bit 13 c2tby 0 carry register 2 tbyt counter carry bit 14 c2tfg 0 carry register 2 tfrg counter carry bit 15 c2tun 0 carry register 2 tund counter carry bit 0x01136 0 c2tov 0 carry register 2 tovr counter carry bit 1 c2tcf 0 carry register 2 txcf counter carry bit 2 c2tfc 0 carry register 2 tfcs counter carry bit 3 c2tjb 0 carry register 2 tjbr counter carry bit 0x01138 0 reserved 1 reserved 1 m1rjb 1 mask register 1 rjbr counter carry bit 2 m1rfr 1 mask register 1 rfrg counter carry bit 3 m1rov 1 mask register 1 rovr counter carry bit 4 m1run 1 mask register 1 rund counter carry bit 5 m1rcs 1 mask register 1 rcse counter carry bit 6 m1rcd 1 mask register 1 rck0 counter carry bit 7 m1rfl 1 mask register 1 rflr counter carry bit 8 m1ral 1 mask register 1 raln counter carry bit 9 m1rxu 1 mask register 1 rxuo counter carry bit 10 m1rxp 1 mask register 1 rxpf counter carry bit 11 m1rxc 1 mask register 1 rxcf counter carry bit 12 m1rbc 1 mask register 1 rbca counter carry bit 13 m1rmc 1 mask register 1 rmca counter carry bit 14 m1rfc 1 mask register 1 rfcs counter carry bit 15 m1rpk 1 mask register 1 rpkt counter carry bit table 17: mac carry and carry mask registers address bit hw symbol init description - 209 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x0113a 0 m1rby 1 mask register 1 rbyt counter carry bit 9 m1mgv 1 mask register 1 trmgv counter carry bit 10 m1max 1 mask register 1 trmax counter carry bit 11 m11k 1 mask register 1 tr1k counter carry bit 12 m1511 1 mask register 1 tr511 counter carry bit 13 m1255 1 mask register 1 tr255 counter carry bit 14 m1127 1 mask register 1 tr127 counter carry bit 15 m164 1 mask register 1 tr64 counter carry bit 0x0113c 0 reserved 1 reserved 1 reserved 1 reserved 2 m2tnc 1 mask register 2 tncl counter carry bit 3 m2txc 1 mask register 2 txcl counter carry bit 4 m2tlc 1 mask register 2 tlcl counter carry bit 5 m2tma 1 mask register 2 tmal counter carry bit 6 m2tsc 1 mask register 2 tscl counter carry bit 7 m2ted 1 mask register 2 tedf counter carry bit 8 m2tdf 1 mask register 2 tdfr counter carry bit 9 m2tpf 1 mask register 2 txpf counter carry bit 10 m2tbc 1 mask register 2 tbca counter carry bit 11 m2tmc 1 mask register 2 tmca counter carry bit 12 m2tpk 1 mask register 2 tpd0 counter carry bit 13 m2tby 1 mask register 2 tbyt counter carry bit 14 m2tfg 1 mask register 2 tfrg counter carry bit 13 m2tby 1 mask register 2 tbyt counter carry bit 15 m2tun 1 mask register 2 tund counter carry bit 0x0113e 0 m2tov 1 mask register 2 tovr counter carry bit 1 m2tcf 1 mask register 2 txcf counter carry bit 2 m2tfc 1 mask register 2 tfcs counter carry bit 3 m2tjb 1 mask register 2 tjbr counter carry bit table 17: mac carry and carry mask registers address bit hw symbol init description - 210 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tables 18 through 23 - configuration of the mac table 18: mac configuration registers address bit hw symbol init description 0x00000 0 transmit enable 0x0000 transmit enable: setting this bit will allow the mac to transmit frames from the system. clearing this bit will prevent the transmission of frames. its default is '0'. it is possible for one frame to be transmitted after the transmit enable bit is set to zero. to avoid this the transmit mac can be disabled by using the reset tx mac control bit. 1 synchronized enable synchronized transmit: read only status bit - a one indicates that the transmit enable is synchronized to the transmit stream. 2 receive enable receive enable: setting this bit will allow the mac to receive frames from the phy. clearing this bit will prevent the reception of frames. its default is '0'. 3 synchronized received enable synchronized receive enable: read only status bit - a one indicates that the receive enable is synchronized to the receive data stream. 4 transmit flow control enable transmit flow control enable: setting this bit will allow the transmit mac control to send pause flow control frames when requested by the sys- tem. clearing this bit prevents the transmit mac control from sending flow control frames. default is '0'. 5 receive flow control enable receive flow control enable: setting this bit will cause the receive mac control to detect and act on pause flow control frames. clearing this bit causes the receive mac control to ignore pause flow control frames. its default is '0'. 7-6 reserved 8 loop back loop back: setting this bit will cause the mac transmit outputs to be looped back to the mac receive inputs. clearing this bit results in normal operation. default is '0'. when this loopback is selected, frames are transmitted to the cli- ent. 15-9 reserved 0x00002 0 reset tx function 0x8000 reset tx function: setting this bit will put the transmit function block in reset. this block performs the frame transmission protocol. its default is '0'. 1 reset rx function reset rx function: setting this bit will put the receive function block in reset. this block performs the receive frame protocol. its default is '0'. 2 reset tx mac control reset tx mac control: setting this bit will put the transmit mac control block in reset. this block multiplexes data and control frame transfers. it also responds to xoff pause control frames. its default is '0'. 3 reset rx mac control reset rx mac control: setting this bit will put the receive mac control block in reset. this block detects control frames and contains the pause timers. its default is '0'. 13-4 reserved 14 reserved 15 soft reset soft reset: setting this bit will put all modules within the mac in reset except the host interface. the host interface is reset via hrst. its default is '1'. this bit must remain set to 1 during configuration of the port, associated encap- sulation/decapsulation blocks and mapper/demapper blocks. (i.e., this should be cleared only after the reset of the desired blocks, including macs, are con- figured.) - 211 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 19: mac station address registers 0x00004 0 full duplex 0x7000 full duplex: setting this bit will configure the mac to operate in full duplex mode. clearing this bit will configure the mac to operate in half duplex mode only. its default is '1'. 1 crc enable crc enable: set this bit to have the mac append a crc on all frames. clear this bit if frames presented to the mac have a valid length and contain a valid crc. if he configuration bit pad/crc enable or the per-packet pad/crc enable is set, crc enable is ignored. its defaults is '0' 2 pad / crc enable pad / crc enable: set this bit to have the mac pad all short frames and append a crc to every frame whether or not padding was required. clear this bit if frames presented to the mac have a valid length and contain a crc. its defaults is '0'. 3 reserved 4 length field checking length field checking: set this bit to cause the mac to check the frame's length field to ensure it matches the actual data field length. clear this bit if no length field checking is desired. its default is '0'. 5 huge frame enable huge frame enable: set this bit to allow frames longer than the maxi- mum frame length to be transmitted and received. clear this bit to have the mac limit the length of frames at the maximum frame length value. its default is '0'. 7-6 reserved 9-8 interface mode interface mode: this field determines the type of interface the mac is con- nected to: interface mode bit 9 bit 8 reserved 0 0 nibble mode (10/100 mbit/s smii) 0 1 byte mode (1000 mbit/s gmii) 1 0 reserved 1 1 its default is '0x0'. 11-10 reserved 15-12 preamble length preamble length: this field determines the length of the preamble field of the packet, in bytes. valid range for this field is 0x2 through 0x7 and the default is 0x7. address bit hw symbol init description 0x00040 7-0 station address 0x0000 station address, 4 th octet: this field holds the fourth octet of the station address. the fourth octet is stored in 7:0 and defaults to '0x00'. 15-8 station address station address, 3 rd octet: this field holds the third octet of the station address. the third octet is stored in 15:8 and defaults to '0x00'. 0x00042 7-0 station address 0x0000 station address, 2 nd octet: this field holds the second octet of the station address. the second octet is stored in 23:16 and defaults to '0x00'. 15-8 station address station address, 1 st octet: this field holds the first octet of the station address. the first octet is stored in 31:24 and defaults to '0x00'. table 18: mac configuration registers address bit hw symbol init description - 212 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 20: mac ipg / ifg registers 0x00046 7-0 station address 0x0000 station address, 6 th octet: this field holds the sixth octet of the station address. the sixth octet is stored in 23:16 and defaults to '0x00'. 15-8 station address station address, 5 th octet: this field holds the fifth octet of the station address. the fifth octet is stored in 31:24 and defaults to '0x00'. address bit hw symbol init description 0x00008 6-0 back to back inter packet gap 0x5060 full duplex inter-packet-gap: sets the minimum interpacket gap between back-to-back transmitted packets in full duplex mode. program this field to the number of bit times of ipg desired, from 0x0c to 0x7f. the default setting of 0x60 (96d) represents the standard minimum ipg of 96 bit times. 7 reserved 15-8 minimum ifg enforcement minimum ifg enforcement: sets the minimum number of bit times of interframe gap that is enforced between received frames. a frame fol- lowing an undersized ifg is dropped. set the register to the desired ifg in bit times plus 0x40. the default setting of 0x50 enforces a minimum ifg of 16 bit times. range is from 0x40 to 0xff. 0x0000a 6-0 ipgr2 0x4060 half duplex inter-packet-gap (ipgr2): sets the minimum inter- packet gap for half duplex mode. ipg2 is the time between the end of a received packet and the start of a transmitted packet, or the time between two transmitted packets, as measured at the smii interface of the ether- map-3. set the register to the number of desired bit times plus 0x04. the range of values for ipgr2 is from 0x1c to 0x7f and defaults to 0x60. 7 reserved 14-8 ipgr1 non-back-to-back inter-packet-gap part 1 (ipgr1): sets the carriersense window referenced in ieee 802.3/4.2.3.2.1 'carrier defer- ence'. if carrier is detected during the timing of ipg1, the mac defers to carrier. if, however, carrier becomes active after ipg1, the mac continues timing to the end of ipg2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. to set the register, use the equation: ipgr1 = ipg2 - ipg1 - 0x0c where ipgr1 is the register value, ipg1 is the carriersense window in bit times and ipg2 is the total ipg in bit times (not the ipgr2 register value) the range of values for ipg1 is from 0 to ipg2. the register default is 0x40. to follow the two-thirds/one-thirds (96/64) guideline: 96 - 64 - 12 = 20 = 0x14. 15 reserved address bit hw symbol init description - 213 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 21: mac half duplex registers table 22: mac maximum frame registers address bit hw symbol init description 0x0000c 9-0 collision window 0xf037 collision window: sets the collision window which is the number of slot times from the beginning of transmission during which collisions can occur in properly configured networks. set the register to the frame byte count at the end of the desired window. the default of 0x37 yields the stan- dard 512 slot window (frame count of 55 bytes plus the preamble and sfd). range is from 0 to 0x3f. 11-10 reserved 15-12 retransmission maximum retransmission maximum: sets the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. the default of 0xf is the standard attemptlimit of 16. range is from 0 to 0xf. 0x0000e 0 excessive defer 0x00a1 excessive defer: setting this bit will configure the tx mac to allow the transmission of a packet that has been excessively deferred. clearing this bit will cause the tx mac to abort the transmission of a packet that has been excessively deferred. its default is '1'. 1 no backoff no backoff: setting this bit will configure the tx mac to immediately re- transmit following a collision. clearing this bit will cause the tx mac to fol- low the binary exponential back off rule. its default is '0'. 2 back pressure no backoff back pressure no backoff: setting this bit will configure the tx mac to immediately re-transmit, following a collision, during back pressure operation. clearing this bit will cause the tx mac to follow the binary expo- nential back off rule. its default is '0'. 3alternate binary expo- nential back- off enable alternate binary exponential backoff enable: setting this bit will configure the tx mac to use the alternate binary exponential backoff truncation register value instead of the 802.3 standard of ten, as described on page 135 . clearing this bit will cause the tx mac to follow the standard binary exponential back off rule. its default is '0'. 7-4 alternate binary expo- nential back- off truncation: alternate binary exponential backoff truncation: this field is used when alternate binary exponential backoff enable is set. the value programmed is substituted for the ethernet standard value of ten. its default is '0xa'. 15-8 reserved address bit hw symbol init description 0x00010 15-0 maximum frame length 0x0600 maximum frame length: this field resets to 0x0600 (1536d), which represents the maximum frame size in both the transmit and receive directions. if a different maximum length restriction is desired, program this 16-bit field. - 214 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 23: mac test registers address bit hw symbol init description 0x0001c 0 shortcut slot time 0x0000 shortcut slot time: this bit allows the slot time counter to expire regardless of the current count. this bit is for testing purposes only. its default is '0'. 1 test pause test pause: setting this bit allows the mac to be paused via the host interface for testing purposes. its default is '0'. 2 reserved 3 maximum backoff maximum backoff: setting this bit will cause the mac to backoff for the maximum possible length of time. this test bit is used to predict back- off times in half duplex mode. its default is '0'. 15-4 reserved - 215 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tables 24 through 29 - mii management interface (used for mac0 only) table 24: mac mii mgmt configuration registers table 25: mac mii mgmt command registers address bit hw symbol init description 0x00020 2-0 mgmt clock select 0x0000 mgmt clock select: this field determines the clock frequency of the mgmt clock (mdc). according to the following table: mgmt clock select bit 2 bit 1 bit 0 source clock divided by 4 0 0 0 source clock divided by 4 0 0 1 source clock divided by 6 0 1 0 source clock divided by 8 0 1 1 source clock divided by 10 1 0 0 source clock divided by 14 1 0 1 source clock divided by 20 1 1 0 source clock divided by 28 1 1 1 its default is '000'. 3 reserved 4 preamble sup- pression preamble suppression: setting this bit causes the mii mgmt to suppress preamble generation and reduce the mgmt cycle from 64 clocks to 32 clocks. this is in accordance with ieee 802.3/22.2.4.4.2. clearing this bit causes the mii mgmt to perform mgmt read/write cycles with the 32 clocks of preamble. its default is '0'. 5 phyinc phy increment: automatically increments phy address in scan mode. default is ? 0 ? (off). 15-6 reserved 0x00022 14-0 reserved 0x0000 15 reset mii mgmt reset mii mgmt: setting this bit resets the mii mgmt. clearing this bit allows the mii mgmt to perform mgmt read/write cycles as requested via the host interface. its default is '0'. address bit hw symbol init description 0x00024 0 read cycle 0x0000 read cycle: this bit causes the mii mgmt to perform a single read cycle when transitioned from 0 to 1. the read data is returned in register 0x00030 (mii mgmt status). its default is '0'. 1 scan cycle scan cycle: this bit causes the mii mgmt to perform read cycles con- tinuously. this is useful for monitoring link fail for example. its default is '0'. 15-2 reserved - 216 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 26: mac mii mgmt address registers table 27: mac mii mgmt control registers table 28: mac mii mgmt status registers table 29: mac mii mgmt indicators registers address bit hw symbol init description 0x00028 4-0 register address 0x0000 register address: this field represents the 5-bit register address field of mgmt cycles. up to 32 registers can be accessed. its default is 'tx'. 7-5 reserved 12-8 phy address phy address: this field represents the 5-bit phy address field of mgmt cycles. up to 31 phys can be addressed (0 is reserved). its default is '0x00'. 15-13 reserved address bit hw symbol init description 0x0002c 15-0 mii mgmt control 0x0000 mii mgmt control (phy control): when written, an mii mgmt write cycle is performed using the 16-bit data and the pre-configured phy and register addresses from the mii mgmt address register (0x00028). its default is '0x0000'. address bit hw symbol init description 0x00030 15-0 mii mgmt status 0x0000 mii mgmt status (phy status): following an mii mgmt read cycle, the 16-bit data can be read from this location. its default is '0x0000'. address bit hw symbol init description 0x00034 0 busy 0x0000 busy: when '1' is returned - indicates mii mgmt block is currently per- forming an mii mgmt read or write cycle. 1 scanning scanning: when '1' is returned - indicates a scan operation (continuous mii mgmt read cycles) is in progress. 2 not valid not valid: when '1' is returned - indicates mii mgmt read cycle has not completed and the read data is not yet valid. 15-3 reserved - 217 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ethernet mac registers note: throughout all the following sections of the memory map, we will use the suffix ? d ? for registers which indicate a defect, "a" for registers which indicate an alarm, "c" for control registers, "rpc" for performance counters. also we use suffix "x" to index the eight mac ? s. tables 30 through 34 - configuration, alarms and interrupts of the ethernet macs table 30: mac block - general configuration (rw) address bit hw symbol init description 0x1d340 7-0 autoz 0x00ff mac: automatic zero addressed statistics counter value for the mac 1: all statistics counters saturate and are cleared on read 0: all statistics counters roll-over and are not cleared on read one bit per mac (lsb for mac0, ..., msb for mac7) 0x1d342 7-0 sten 0x0000 mac: statistics enable 1: statistics are enabled 0: statistics are disabled one bit per mac (lsb for mac0, ..., msb for mac7) 0x1d344 1-0 cinrt_sotern_core 0x0001 alarm latching configuration for the mac alarm group ( table 33 ) criteria used to create latched alarms from the raw (unlatched) alarms. 00: positive level 01: rising edge (default) 10: falling edge 11: rising or falling edge 0x1d346 0x1d34c 0x1d352 0x1d358 0x1d35e 0x1d364 0x1d36a 0x1d370 15-0 rhwpt_x 0xffff flow control: high pause time value for mac0-7 when exceeding the set high watermark value. the contents of this register are inserted into the outgoing pause frame in the pause_time field. recommended value for gmii mode is 0x3a98. recommended value for smii mode is 0x012c. 0x1d348 0x1d34e 0x1d354 0x1d35a 0x1d360 0x1d366 0x1d36c 0x1d372 15-0 rlwpt_x 0x0000 flow control: low pause time value for mac0-7 when receding below the low watermark value. the contents of this register are inserted into the outgoing pause frame in the pause_time field. recommended value for both smii and gmii modes is 0x0000. 0x1d34a 0x1d350 0x1d356 0x1d35c 0x1d362 0x1d368 0x1d36e 0x1d374 15-0 rhipse_x 0xbeeb flow control: internal local pause timer value for the mac0-7. after being loaded with the value in the rhwpt_x register, the internal pause timer is decremented until it reaches this value, so a smaller value in this reg- ister results in a longer time between sampling the txfifo depth. recommended value for gmii mode is 0x2710. recommended value for smii mode is 0x0032. table 31: mac block - alarms (ro) address bit hw symbol init description 0x1d300 7-0 carryx 0x0000 carry overflow alarm for the mac0-7 0: no carry overflow 1: carry overflow alarm one bit per mac (lsb for mac0, ..., msb for mac7) - 218 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 32: mac block - alarm and interrupt masks (rw) address bit hw symbol init description 0x1d320 7-0 macarryx 0x00ff carry overflow alarm mask for the mac0-7 1: alarm is masked 0: alarm is not masked one bit per mac (lsb for mac0, ..., msb for mac7) 0x1d322 0 mamac_global_interrupt 0x0001 global interrupt mask for the mac part 1: interrupt is masked 0: interrupt is not masked table 33: mac block - latched alarms (rr) address bit hw symbol init description 0x1d310 7-0 l1carryx 0x0000 carry overflow latched alarm for the mac0-7 1: alarm is latched. cleared on read 0: no alarm is latched one bit per mac (lsb for mac0, ..., msb for mac7) table 34: mac block - interrupts (ro) address bit hw symbol init description 0x1d330 0 mac_carry_interrupt 0x0000 global carry alarm interrupt for the mac 1: interrupt is masked 0: interrupt is not masked 0x1d332 0 mac_global_interrupt 0x0000 global alarm interrupt for the mac 1: interrupt is masked 0: interrupt is not masked - 219 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tx encapsulation registers tables 35 through 47 - configuration, status and alarms of the encapsulation block table 35: encapsulation block - general configuration (rw) address bit hw symbol init description 0x1fc00 0x1ffe0 0x101e0 0x105e0 0x109e0 0x10de0 0x111e0 0x115e0 1-0 ctencapx 0x0008 transmit side encapsulation mode selection for mac0-7 00: laps (default) 01: lapf 10: gfp 11: ppp 2 ctscrdx tx encapsulation: laps/ppp scrambling control for mac0-7 0: enable scrambling for laps/ppp frame. (default) 1: disable scrambling for laps/ppp frame. 3 ctfcsx tx encapsulation: fcs enabling for mac0-7 (laps/lapf) 0: fcs calculation disabled and the fcs field octets are not inserted. 1: fcs calculation enabled and the fcs field octets are inserted. (default) 4 ctfcsex tx encapsulation: fcs error insertion for mac0-7 (laps/lapf/gfp) 0: fcs is transmitted without any inserted errors. (default) 1: fcs is transmitted with errors inserted. 5 ctabtgx tx encapsulation: force abort generation for mac0-7 (laps/gfp/ppp) 0: no action 1: frame(s) currently in transmission are aborted (i.e., while held at '1', will cause continuous aborts). in gfp mode an error is inserted in the payload fcs field. in laps/ppp mode 0x7d is transmitted, followed by 0x7e. notes: 1) this bit is a level type. 2) when fcs is enabled, a packet is transmitted with inverted fcs. 3) if asserted and deasserted between packets, the next packet is not aborted. 4) if asserted during gfp idle frame, 1, 2, 3 or all 4 bytes of the idle frame may be inverted. 5) in ppp mode, the first aborted packet will contain two abort indications. 6 ctoffx tx encapsulation: suspend frame mapping in sonet/sdh for mac0-7 (laps/lapf/gfp) 0: encapsulated frames are mapped to sonet/sdh tributaries for transmis- sion. (default) 1: encapsulated frames are not mapped to sonet/sdh tributaries for trans- mission. instead only flags (laps/lapf) or idle frames (gfp) are mapped to sonet/sdh tributaries. 7 ctpscrdx tx encapsulation: gfp payload scrambling control for mac0-7 (gfp) 0: enable scrambling of gfp payload area only. (default) 1: disable scrambling of gfp payload area. 0x1fc02 0 end_init_micro 0x0000 end of microprocessor initialization must be set to ? 1 ? after completion of the device initialization phase. this bit is automatically cleared after a hard reset is provided to the device. this bit only needs to be set once after the chip has been reset by a hard reset or through the reseth bit. it does not need to be modified afterwards to change configuration bits on the fly. see ? encapsulation/decapsulation ? on page 139 section for changing encapsulation/decapsulation registers on the fly. only a hard reset or the reseth bit can clear this bit. 0x1fc04 0x1ffe2 0x101e2 0x105e2 0x109e2 0x10de2 0x111e2 0x115e2 15-0 rtmaxflx 0x0640 tx laps/lapf/gfp/ppp: max frame length for mac0-7 configures the maximum number of bytes per frame, including the fcs bytes, that will be accepted from a mac for encapsulation. frames which exceed this length are discarded and corresponding alarms and counters are triggered default is 0x640 (decimal 1600). - 220 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1fc06 0x1ffe4 0x101e4 0x105e4 0x109e4 0x10de4 0x111e4 0x115e4 0 ctscrinitx 0x0000 tx laps/gfp/ppp: scrambler initial value for mac0-7 0: on reset, initialize the 43-bit shift register to all zeros (default). 1: on reset, initialize the 43-bit shift register to all ones. 0x1fc08 0x1ffe6 0x101e6 0x105e6 0x109e6 0x10de6 0x111e6 0x115e6 0 ctfcsinitallx 0x0001 tx laps/lapf/gfp/ppp: initial value of fcs generation registers for mac0-7 0: on reset, initialize the fcs generation shift register to all zeros. 1: on reset, initialize the fcs generation shift register to all ones (default). 0x1fc0a 0x1ffe8 0x101e8 0x105e8 0x109e8 0x10de8 0x111e8 0x115e8 0 ctfcsswapinx 0x0000 tx laps/lapf/gfp/ppp: bit swapping of fcs generation input for mac0-7 at the input to the fcs generator, all data bytes over which the fcs is calcu- lated, can be bit swapped (i.e., msb <--> lsb). 0: data bytes are not modified (default). 1: data bytes are bit swapped. 0x1fc0c 0x1ffea 0x101ea 0x105ea 0x109ea 0x10dea 0x111ea 0x115ea 0 ctfcsswapoutx 0x0000 tx laps/lapf/gfp/ppp: bit swapping of fcs generation output for mac0- 7 at the output of the fcs generator, all data bytes over which the fcs was calculated and the fcs bytes, can be bit swapped (i.e., msb <--> lsb). 0: data bytes and fcs bytes are not modified (default). 1: data bytes and fcs bytes are bit swapped. 0x1fc0e 0x1ffec 0x101ec 0x105ec 0x109ec 0x10dec 0x111ec 0x115ec 0 cthecinitallx 0x0000 tx gfp: hec generation initial value for mac0-7 in gfp mode, this bit is used to control the initial value of the hec genera- tion shift register. 0: on reset, initialize the hec generation register to all zeros (default). 1: on reset, initialize the hec generation register to all ones. 0x1fc10 0x1ffee 0x101ee 0x105ee 0x109ee 0x10dee 0x111ee 0x115ee 0 cthecswapinx 0x0000 tx gfp/ppp: bit swapping of hec generation input for mac0-7 in gfp mode, at the input to the hec generator, all bytes over which the hec is to be calculated can be bit swapped (i.e., msb <--> lsb). 0: header bytes are not modified (default). 1: header bytes are bit swapped. 0x1fc12 0x1fff0 0x101f0 0x105f0 0x109f0 0x10df0 0x111f0 0x115f0 0 cthecswapoutx 0x0000 tx gfp: bit swapping of hec generation output for mac0-7 in gpf mode, at the output of the hec generator, all bytes over which the hec was calculated, and the hec bytes, can be bit swapped (i.e., msb <--> lsb). 0: header bytes and hec bytes are not modified. 1: header bytes and hec bytes are bit swapped. table 35: encapsulation block - general configuration (rw) address bit hw symbol init description - 221 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1fc14 0x1fff2 0x101f2 0x105f2 0x109f2 0x10df2 0x111f2 0x115f2 0 ctctlbrstx 0x0000 tx laps/lapf/gfp/ppp: resets the control frame buffer for mac0-7 writing a 1 to this bit causes the control frame buffer to discard its present contents. the control frame buffer empty alarm will be set for the corre- sponding mac (atctlxx). table 36: encapsulation block - laps configuration (rw) address bit hw symbol init description 0x1fda0 0x1ffb0 0x101b0 0x105b0 0x109b0 0x10db0 0x111b0 0x115b0 0 ctflagx 0x0003 tx laps/lapf/ppp: number of flag insertions between laps/lapf frames for mac0-7 0: single flag is present between frames (i.e., a shared flag). 1: two flags are present between frames. (default). 2-1 ctacselx tx laps: address and control field insertion management for mac0- 7 00: address and control field contents are fixed to zero 01: address = 0x04 and control = 0x03 (default) 10: reserved 11: address and control field contents inserted from rtacfdx register 3 ctsapix tx laps: sapi field insertion for mac0-7 0: sapi field contents inserted from rtsapfdx register 1: sapi field contents are fixed to zero 4 ctlppdux tx laps: enable laps frame mapping sonet/sdh for mac0-7 0: all laps frames are mapped into the sonet/sdh stream. 1: laps frames containing ethernet frames from the macs are not mapped. laps control frames from the host continue to be mapped. 0x1fda2 0x1ffb2 0x101b2 0x105b2 0x109b2 0x10db2 0x111b2 0x115b2 15-0 rtacfdx 0x0403 tx laps: configurable address and control field contents for mac0-7 upper byte (bits 15-8) = content of the address field. default set to 0x04. lower byte (bits 7-0) = content of the control field. default set to 0x03. 0x1fda4 0x1ffb4 0x101b4 0x105b4 0x109b4 0x10db4 0x111b4 0x115b4 15-0 rtsapfdx 0xfe01 tx laps: configurable sapi field contents for mac0-7 upper byte (bits 15-8) = content of the first sapi octet field. default set to 0xfe. lower byte (bits 7-0) = content of the second sapi octet field. default set to 0x01. table 35: encapsulation block - general configuration (rw) address bit hw symbol init description - 222 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 37: encapsulation block - lapf configuration (rw) address bit hw symbol init description 0x1fd80 0x1ff80 0x10180 0x10580 0x10980 0x10d80 0x11180 0x11580 0 ctfecnx 0x0000 tx lapf: setting of fecn field for mac0-7 0: transmit fecn bit set to 0. (default) 1: transmit fecn bit set to 1. 1 ctbecnx tx lapf: setting of becn field for mac0-7 0: transmit becn bit set to 0. (default) 1: transmit becn bit set to 1. 2 ctdex tx lapf: setting of de field for mac0-7 0: transmit de bit set to 0. (default) 1: transmit de bit set to 1. 3 ctlfacnopselx tx lapf: address, control, oui, nlpid and pid fields insertion con- trol for mac0-7 0: address, control, oui, nlpid and pid field content insertion enabled. (default) address field contents taken from rtdlcix, ctcrx, ctfecnx, ctbecnx and ctdex registers. control field contents taken from rtlfcntlx register. nlpid field contents taken from rtnlpidx register. oui field contents taken from rtouix register. pid field contents taken from rtpidx register. 1: address, control, nlpid, oui and pid field contents insertion is disabled. these fields are all set to zero. 4 ctlfpadx tx lapf: pad field insertion control for mac0-7 0: pad field insertion enabled and field contents are taken from the rtpadx register. only one pad field octet is inserted regarding to the alignment of payload information to a two octet boundary (even length frame). 1: pad field insertion disabled. no insertion of pad field in lapf frame. 5 ctcrx tx lapf: setting of command/response (c/r) field for mac0-7 0: transmit c/r bit set to 0. (default) 1: transmit c/r bit set to 1. 6 ctlfpdux tx lapf: lapf frame mapping enable into sonet/sdh stream for mac0-7 0x1fd82 0x1ff82 0x10182 0x10582 0x10982 0x10d82 0x11182 0x11582 9-0 rtdlcix 0x0010 tx lapf: configurable dlci field contents for mac0-7 range 0x010 to 0x3df: indicates dlci field contents when insertion is enabled. default is 0x010. 0x1fd84 0x1ff84 0x10184 0x10584 0x10984 0x10d84 0x11184 0x11584 7-0 rtlfcntlx 0x0003 tx lapf: configurable control field contents for mac0-7 range 0x00-0xff: indicates control field contents when insertion is enabled. default is 0x03. 0x1fd86 0x1ff86 0x10186 0x10586 0x10986 0x10d86 0x11186 0x11586 7-0 rtpadx 0x0000 tx lapf: configurable pad field contents for mac0-7 range 0x00-0xff: indicates pad field contents when insertion is enabled. default is 0x00. - 223 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1fd88 0x1ff88 0x10188 0x10588 0x10988 0x10d88 0x11188 0x11588 7-0 rtnlpidx 0x0080 tx lapf: configurable nlpid field contents for mac0-7 range 0x00-0xff: indicates nlpid field contents when insertion is enabled. default is 0x80. 0x1fd8a 0x1ff8a 0x1018a 0x1058a 0x1098a 0x10d8a 0x1118a 0x1158a 7-0 rtouix(1) 0x0000 tx lapf: configurable oui field contents (msb bits) for mac0-7 range 0x00-0xff: indicates oui (msb bits) field contents when insertion is enabled. default is 0x00. 0x1fd8c 0x1ff8c 0x1018c 0x1058c 0x1098c 0x10d8c 0x1118c 0x1158c 15-0 rtouix(0) 0x80c2 tx lapf: configurable oui field contents (lsb bits) for mac0-7 range 0x0000-0xffff: indicates oui (lsb bits) field contents when inser- tion is enabled. default is 0x80c2. 0x1fd8e 0x1ff8e 0x1018e 0x1058e 0x1098e 0x10d8e 0x1118e 0x1158e 15-0 rtpidx 0x0007 tx lapf: configurable pid field contents for mac0-7 range 0x0000-0xffff: indicates pid field contents when insertion is enabled. default is 0x0007. table 38: encapsulation block - gfp configuration (rw) address bit hw symbol init description 0x1fcc0 0x1ffd0 0x101d0 0x105d0 0x109d0 0x10dd0 0x111d0 0x115d0 2-0 cptix 0x0100 tx gfp: configurable pti field contents for mac0-7 range 0x0-0x7: indicates contents of the pti field for gfp client data frames only. default is 0x0. 3 cpfix tx gfp: payload fcs indicator control for mac0-7 0: the pfi bit within the gfp payload header is set to zero (0). gfp payload fcs field is not inserted. (default) 1: the pfi bit within the gfp payload header is set to one (1). gfp payload fcs field is inserted. 7-4 cexix tx gfp: configurable exi field contents for mac0-7 range 0x0-0xf: indicates contents of the exi field within the gfp payload header. default is 0x0. 15-8 cupix tx gfp: configurable upi field contents for mac0-7 range 0x00-0xff: indicates contents of the upi field for gfp client data frames only. default is 0x01. table 37: encapsulation block - lapf configuration (rw) address bit hw symbol init description - 224 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1fcc2 0x1ffd2 0x101d2 0x105d2 0x109d2 0x10dd2 0x111d2 0x115d2 7-0 cfecidx 0x0000 tx gfp: configurable cid field contents for mac0-7 range 0x00-0xff: indicates contents of the cid field within the gfp exten- sion header when using gfp linear frame structure. default is 0x00. 15-8 csparex tx gfp: configurable spare field contents for mac0-7 range 0x00-0xff: indicates contents of the spare field within the gfp extension header when using gfp linear frame structure. default is 0x00. 0x1fcc4 0x1ffd4 0x101d4 0x105d4 0x109d4 0x10dd4 0x111d4 0x115d4 0 ctchecerrx 0x0000 tx gfp: core header hec error insertion control for mac0-7 0: disable chec error insertion. (default) 1: a single chec error is inserted by inverting all the bits in the calculated chec field. this bit self-clears after the errored frame is transmitted. 1 ctthecerrx tx gfp: type header hec error insertion control for mac0-7 0: disable thec error insertion. (default) 1: a single thec error is inserted by inverting all the bits in the calculated thec field. this bit self-clears after the errored frame is transmitted. 2 ctehecerrx tx gfp: extension header hec error insertion control for mac0-7 0: disable ehec error insertion. (default) 1: a single ehec error is inserted by inverting all the bits in the calculated ehec field. this bit self-clears after the errored frame is transmitted. 3 ctcscrx tx gfp: core header scrambling control for mac0-7: 0: enable scrambling of gfp core header only. (default) 1: disable scrambling of gfp core header only. 4 ctgfptxcsfx tx gfp: csf frame transmit mode control for mac0-7 0: disable gfp csf frame transmit mode. (default) 1: enable gfp csf frame transmit mode. one csf frame is transmitted every 100 ms, with interim gfp idle frames. client data frames are not trans- mitted. 5 ctgfppdux txgfp: gfp frame mapping enable into sonet/sdh stream for mac0-7 0: all gfp frames are mapped into the sonet/sdh stream. 1: gfp frames containing ethernet frames from the macs are not mapped. client management/control frames from the host continue to be mapped. 0x1fcc6 0x1ffd6 0x101d6 0x105d6 0x109d6 0x10dd6 0x111d6 0x115d6 3-0 cidtablex_0 see note below tx gfp: cid table word 0 for mac0-7 (used in linear mode with cexi = 1) bit 3: 0 = this entry of the table is not valid (default); 1 = this entry of the table is valid. bits 2-0: (range 0x0-0x7) indicates the number of the selected mac port. (default=0x0) 7-4 cidtablex_1 tx gfp: cid table word 1 for mac0-7 (used in linear mode with cexi = 1) bit 3: 0 = this entry of the table is not valid (default); 1 = this entry of the table is valid. bits 2-0: (range 0x0-0x7) indicates the number of the selected mac port. (default=0x0) 11-8 cidtablex_2 tx gfp: cid table word 2 for mac0-7 (used in linear mode with cexi = 1) bit 3: 0 = this entry of the table is not valid (default); 1 = this entry of the table is valid. bits 2-0: (range 0x0-0x7) indicates the number of the selected mac port. (default=0x0) 15-12 cidtablex_3 tx gfp: cid table word 3 for mac0-7 (used in linear mode with cexi = 1) bit 3: 0 = this entry of the table is not valid (default); 1 = this entry of the table is valid. bits 2-0: (range 0x0-0x7) indicates the number of the selected mac port. (default=0x0) note: write all 0s to all 8 registers before configuring cid table to ensure that unused vcgs have 0 in their tx cid table. table 38: encapsulation block - gfp configuration (rw) address bit hw symbol init description - 225 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1fcc8 0x1ffd8 0x101d8 0x105d8 0x109d8 0x10dd8 0x111d8 0x115d8 3-0 cidtablex_4 see note below tx gfp: cid table word 4 for mac0-7 (used in linear mode with cexi = 1) bit 3: 0 = this entry of the table is not valid (default); 1 = this entry of the table is valid. bits 2-0: (range 0x0-0x7) indicates the number of the selected mac port. (default=0x0) 7-4 cidtablex_5 tx gfp: cid table word 5 for mac0-7 (used in linear mode with cexi = 1) bit 3: 0 = this entry of the table is not valid (default); 1 = this entry of the table is valid. bits 2-0: (range 0x0-0x7) indicates the number of the selected mac port. (default=0x0) 11-8 cidtablex_6 tx gfp: cid table word 6 for mac0-7 (used in linear mode with cexi = 1) bit 3: 0 = this entry of the table is not valid (default); 1 = this entry of the table is valid. bits 2-0: (range 0x0-0x7) indicates the number of the selected mac port. (default=0x0) 15-12 cidtablex_7 tx gfp: cid table word 7 for mac0-7 (used in linear mode with cexi = 1) bit 3: 0 = this entry of the table is not valid (default); 1 = this entry of the table is valid. bits 2-0: (range 0x0-0x7) indicates the number of the selected mac port. (default=0x0) note: write all 0s to all 8 registers before configuring cid table to ensure that unused vcgs have 0 in their tx cid table. table 38: encapsulation block - gfp configuration (rw) address bit hw symbol init description - 226 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 39: encapsulation block - ppp configuration (rw) address bit hw symbol init description 0x1fce0 0x1ff40 0x10140 0x10540 0x10940 0x10d40 0x11140 0x11540 1-0 ctpfcsx 0x00a7 tx ppp: fcs generation mode for mac0-7 00: disable fcs generation 01: reserved 10: enable 16-bit fcs generation. two fcs bytes are inserted. 11: enable 32-bit fcs generation. four fcs bytes are inserted. (default) 3-2 ctppacselx tx ppp: address and control field insertion for mac0-7 00: disable insertion: all address and control fields are set to zero. 01: fixed insertion (default): the address field is inserted as 0xff, the con- trol field is inserted as 0x03. 10: reserved 11: programmable insertion: address and control fields are inserted from the rtppacfdx register. 4 ctpppix tx ppp: protocol field insertion for mac0-7 0: enabled (default): protocol fields are inserted from the rtppfdx register. 1: disabled: protocol fields are set to zero. 5 ctbcpflgfx tx ppp: bcp flag f value for mac0-7 0: insert 0. 1: insert 1. (default) 6 ctbcpflg0x tx ppp: bcp flag 0 value for mac0-7 0: insert 0. (default) 1: insert 1. 7 ctbcpflgzx tx ppp: bcp flag z value for mac0-7 0: insert 0. 1: insert 1. (default) 8 ctbcpflgbx tx ppp: bcp flag b value for mac0-7 0: insert 0. (default) 1: insert 1. 9 ctbpdux tx ppp: frame mapping enable into sonet/sdh for mac0-7 0: all ppp frames are mapped into the sonet/sdh stream (default). 1: only lcp/ncp-bcp frames from the host are mapped. 10 ctbcppdcalcx tx ppp: control bit for payload or entire frame padding 0: calculation of the number of padding octets on payload only (default) 1: calculation of the number of padding octets on the whole frame (header + payload + fcs) 0x1fce2 0x1ff42 0x10142 0x10542 0x10942 0x10d42 0x11142 0x11542 1-0 rtbcppdmodex 0x0020 tx ppp: padding mode for mac0-7 00: no padding is used (default). 01: fixed padding mode. the pads field of the bcp frame indicates the number of padding bytes that were inserted. 10: reserved 11: reserved. 3-2 rtbcppdalignx tx ppp: octet alignment boundary configuration for mac0-7 configures the alignment boundary when using fixed or self-describing padding mode. 00: 2 octet alignment boundary (default). 01: 4 octet alignment boundary. 10: 8 octet alignment boundary. 11: 16 octet alignment boundary. 7-4 ctbcppdmpvx reserved - 227 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1fce4 0x1ff44 0x10144 0x10544 0x10944 0x10d44 0x11144 0x11544 7-0 rtbcppadx 0x0100 tx ppp: pad value for mac0-7 contents of the ppp pad bytes when fixed padding is used. default is 0x00. values of 0x7d or 0x7e will result in incorrect byte stuffing and should be avoided. 15-8 rtbcpmacx tx ppp: mac type field value for mac0-7 indicates the value of the mac type field to be inserted into the ppp bcp frame. default is 0x01. 0x1fce6 0x1ff46 0x10146 0x10546 0x10946 0x10d46 0x11146 0x11546 15-0 rtppacfdx 0xff03 tx ppp: address and control field values for mac0-7 15-8: address field. default is 0xff. 7-0: control field. default is 0x03. 0x1fce8 0x1ff48 0x10148 0x10548 0x10948 0x10d48 0x11148 0x11548 15-0 rtppfdx 0x0031 tx ppp: protocol field values for mac0-7 15-8: first protocol byte. default is 0x00. 7-0: second protocol byte. default is 0x31. table 40: encapsulation block - control frame buffers (rw) address bit hw symbol init description 0x1fd00- 0x1fd7e 0x1fe00- 0x1fe7e 0x10000- 0x1007e 0x10400- 0x1047e 0x10800- 0x1087e 0x10c00- 0x10c7e 0x11000- 0x1107e 0x11400- 0x1147e 8-0 rtctl_x_0- rtctl_x_63 0x0000 tx control frame buffer for mac0 to mac7 each control buffer can carry up to 64 bytes. msb bit of each word indicates if the byte (8 lsb bits of each word) is carry- ing or not control frame information (msb=1 means carrying, msb=0 means not carrying). table 39: encapsulation block - ppp configuration (rw) address bit hw symbol init description - 228 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers the following performance counters can be accessed in saturating mode or roll-over mode, depending on the state of the ccrov control bit. in saturating mode, counters do not count past their terminal count and are cleared to zero when read. in roll-over mode, counters roll-over to zero after reaching their terminal count, and are not cleared when read. table 41: encapsulation block - status (rw) address bit hw symbol init description 0x1fdb0 0x1ffc8 0x101c8 0x105c8 0x109c8 0x10dc8 0x111c8 0x115c8 0 stctlbx 0x0000 tx status: lmi buffer full for mac0-7 indicates the status of the tx control frame buffer for each respective mac (rtctl_x_n). the host should poll this bit before writing to the frame buffer. 0: empty 1: full table 42: encapsulation block - status registers (ro) address bit hw symbol init description 0x1fdb4 0x1ffcc 0x101cc 0x105cc 0x109cc 0x10dcc 0x111cc 0x115cc 0 enc_rst_end_initx 0x0000 tx status: reset complete for mac0-7 a one indicates the encapsulation block for each respective mac has completed its initialization after receiving a hard or a soft reset. table 43: encapsulation block - performance counters address bit hw symbol init description 0x1fc80 0x1ff00 0x10100 0x10500 0x10900 0x10d00 0x11100 0x11500 15-0 rpctgfpbytex_lsb 0x0000 tx gfp: gfp byte counter for mac0-7 - lsb counts the total number of bytes in gfp frame payloads transmitted to sonet/sdh. this counter does not include the count of host inserted gfp client man- agement control frames. this counter does include the count of all fields of a gfp frame (including the ethernet mac frame). 0x1fc82 0x1ff02 0x10102 0x10502 0x10902 0x10d02 0x11102 0x11502 15-0 rpctgfpbytex_msb 0x0000 tx gfp: gfp byte counter for mac0-7 - msb this counter does not include the count of host inserted gfp client man- agement control frames. this counter does include the count of all fields of a gfp frame (including the ethernet mac frame). 0x1fc84 0x1ff04 0x10104 0x10504 0x10904 0x10d04 0x11104 0x11504 15-0 rpctgfpframex_lsb 0x0000 tx gfp: gfp payload counter for mac0-7 - lsb counts the total number of gfp frame payloads transmitted to sonet/sdh. this counter does not include the count of host inserted gfp client man- agement control frames. - 229 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1fc86 0x1ff06 0x10106 0x10506 0x10906 0x10d06 0x11106 0x11506 15-0 rpctgfpframex_msb 0x0000 tx gfp: gfp payload counter for mac0-7 - msb this counter does not include the count of host inserted gfp client man- agement control frames. 0x1fc88 0x1ff08 0x10108 0x10508 0x10908 0x10d08 0x11108 0x11508 15-0 rpctlapsbytex_lsb 0x0000 tx laps: laps byte counter for mac0-7 - lsb counts the total number of bytes in laps frame payloads transmitted to sonet/sdh. this counter does not include the count of host inserted laps control frames. this counter does include the count of all fields of a laps frame (including the ethernet mac frame). 0x1fc8a 0x1ff0a 0x1010a 0x1050a 0x1090a 0x10d0a 0x1110a 0x1150a 15-0 rpctlapsbytex_msb 0x0000 tx laps: laps byte counter for mac0-7 - msb this counter does not include the count of host inserted laps control frames. this counter does include the count of all fields of a laps frame (including the ethernet mac frame). 0x1fc8c 0x1ff0c 0x1010c 0x1050c 0x1090c 0x10d0c 0x1110c 0x1150c 15-0 rpctlapsframex_lsb 0x0000 tx laps: laps frame counter for mac0-7 - lsb counts the total number of laps frames transmitted to sonet/sdh. this counter does not include the count of host inserted laps control frames. 0x1fc8e 0x1ff0e 0x1010e 0x1050e 0x1090e 0x10d0e 0x1110e 0x1150e 15-0 rpctlapsframex_msb 0x0000 tx laps: laps frame counter for mac0-7 - msb this counter does not include the count of host inserted laps control frames. 0x1fc90 0x1ff10 0x10110 0x10510 0x10910 0x10d10 0x11110 0x11510 15-0 rpctlapfbytex_lsb 0x0000 tx lapf: lapf byte counter for mac0-7 - lsb counts the total number of bytes in lapf frame payloads transmitted to sonet/sdh. this counter does not include the count of host inserted lapf lmi frames. this counter does include the count of all fields of a lapf frame (including the ethernet mac frame). 0x1fc92 0x1ff12 0x10112 0x10512 0x10912 0x10d12 0x11112 0x11512 15-0 rpctlapfbytex_msb 0x0000 tx lapf: lapf byte counter for mac0-7 - msb this counter does not include the count of host inserted lapf lmi frames. this counter does include the count of all fields of a lapf frame (including the ethernet mac frame). table 43: encapsulation block - performance counters address bit hw symbol init description - 230 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1fc94 0x1ff14 0x10114 0x10514 0x10914 0x10d14 0x11114 0x11514 15-0 rpctlapfframex_lsb 0x0000 tx lapf: lapf frame counter for mac0-7 - lsb counts the total number of lapf frames transmitted to sonet/sdh. this counter does not include the count of host inserted lapf lmi frames. 0x1fc96 0x1ff16 0x10116 0x10516 0x10916 0x10d16 0x11116 0x11516 15-0 rpctlapfframex_msb 0x0000 tx lapf: lapf frame counter for mac0-7 - msb this counter does not include the count of host inserted lapf lmi frames. 0x1fc98 0x1ff18 0x10118 0x10518 0x10918 0x10d18 0x11118 0x11518 15-0 rpctppbytex_lsb 0x0000 tx ppp: ppp byte counter for mac0-7 - lsb counts the total number of bytes in ppp frame payloads transmitted to sonet/sdh. this counter does not include the count of host inserted ppp lcp/ncp- bcp frames. this counter does include the count of all fields of a ppp frame (including the ethernet mac frame). 0x1fc9a 0x1ff1a 0x1011a 0x1051a 0x1091a 0x10d1a 0x1111a 0x1151a 15-0 rpctppbytex_msb 0x0000 tx ppp: ppp byte counter for mac0-7 - msb this counter does not include the count of host inserted ppp lcp/ncp- bcp frames. this counter does include the count of all fields of a ppp frame (including the ethernet mac frame). 0x1fc9c 0x1ff1c 0x1011c 0x1051c 0x1091c 0x10d1c 0x1111c 0x1151c 15-0 rpctppframex_lsb 0x0000 tx ppp: ppp frame counter for mac0-7 - lsb counts the total number of ppp frames transmitted to sonet/sdh. this counter does not include the count of host inserted ppp lcp/ncp- bcp frames. 0x1fc9e 0x1ff1e 0x1011e 0x1051e 0x1091e 0x10d1e 0x1111e 0x1151e 15-0 rpctppframex_msb 0x0000 tx ppp: ppp frame counter for mac0-7 - msb this counter does not include the count of host inserted ppp lcp/ncp- bcp frames. table 43: encapsulation block - performance counters address bit hw symbol init description - 231 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 44: encapsulation block - alarms (ro) address bit hw symbol init description 0x1fdb8 0x1ffa0 0x101a0 0x105a0 0x109a0 0x10da0 0x111a0 0x115a0 0 atgfpcsfx 0x0000 tx gfp: csf indication alarm for mac0-7 1: csf frame mode is enabled. (i.e., while ctgfptxcsfx=1, this alarm is con- stantly set. it does not clear while idle frames are transmit in between the csf frames.) 0: on expiry of 100 ms period 1 atgfpfmerrx tx gfp: incomplete ethernet frame alarm for mac0-7 1: while in the middle of an ethernet frame transmission, no further bytes of that frame are available. 0: follow-on frame is complete and correct. note: the alarm will typically occur when a txfifo overflow occurs and control bit ctrstram=1. 2 atgfpmaxerx tx gfp: max frame length error mac0-7 1: frame length is higher than rtmaxflx(15:0) register 0: after next correct frame (less than the limit) 3 atlfferrx tx lapf: fifo error for mac0-7 1: underflow/overflow of the tx fifo during middle of transfer 0: on tx fifo reset after the alarm entry 4 atlfmaxerx tx lapf: max frame length error for mac0-7 1: frame length is higher than rtmaxflx(15:0) register 0: after next correct frame (less than the limit) 5 atlpferrx tx laps: fifo error alarm for mac0-7 1: underflow/overflow of the tx fifo during middle of transfer 0: on tx fifo reset after the alarm entry 6 atmaxerx tx laps: max frame length error for mac0-7 1: frame length is higher than rtmaxflx(15:0) register 0: after next correct frame (less than the limit) 7 atppferrx tx ppp: fifo error for mac0-7 1: underflow/overflow of the tx fifo during middle of transfer 0: on tx fifo reset after the alarm entry 8 atppmaxerx tx ppp: max frame length error for mac0-7 1: frame length is higher than rtmaxflx(15:0) register 0: after next correct frame (less than the limit) 9 atppmpvdropx tx ppp: padding error for mac0-7 1: number of padding bytes exceeds the value in the rtbcppdmpv(7:4) register 0: after next correct frame 10 atctlxx tx laps/lapf/gfp/ppp: control frame buffer empty alarm for mac0-7 1: control frame buffer is empty 0: control frame buffer is full 11 count_encx count status bit (perf mon counter is saturated) for mac0-7 1: when any of the performance counters of each encapsulation block (associ- ated to each mac) has reached its maximum value in the saturating mode only 0: after being read by the microprocessor - 232 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 45: encapsulation block - alarm and interrupt masks (rw) address bit hw symbol init description 0x1fdc0 0x1ffa8 0x101a8 0x105a8 0x109a8 0x10da8 0x111a8 0x115a8 0 matgfpcsfx 0x07ff tx gfp: csf indication alarm mask for mac0-7 1: masked (default) 0: not masked 1 matgfpfmerrx tx gfp: incomplete ethernet frame alarm mask for mac0-7 1: masked (default) 0: not masked 2 matgfpmaxerx tx gfp: max frame length error alarm mask for mac0-7 1: masked (default) 0: not masked 3 matlfferrx tx lapf: fifo error alarm mask for mac0-7 1: masked (default) 0: not masked 4 matlfmaxerx tx lapf: max frame length error alarm mask for mac0-7 1: masked (default) 0: not masked 5 matlpferrx tx laps: fifo error alarm mask for mac0-7 1: masked (default) 0: not masked 6 matmaxerx tx laps: max frame length error alarm mask for mac0-7 1: masked (default) 0: not masked 7 matppferrx tx ppp: fifo error alarm mask for mac0-7 1: masked (default) 0: not masked 8 matppmaxerx tx ppp: max frame length error alarm mask for mac0-7 1: masked (default) 0: not masked 9 matppmpvdropx tx ppp: padding error alarm mask for mac0-7 1: masked (default) 0: not masked 10 matctlxx tx laps/lapf/gfp/ppp: control frame buffer empty alarm mask for mac0-7 1: masked (default) 0: not masked 0x1fdc2 7-0 maencx_lapf_interrupt 0x00ff tx lapf: mask interrupt for mac0-7 1: masked (default) 0: not masked 0x1fdc4 7-0 maencx_laps_interrupt 0x00ff tx laps: mask interrupt for mac0-7 1: masked (default) 0: not masked 0x1fdc6 7-0 maencx_gfp_interrupt 0x00ff tx gfp: mask interrupt for mac0-7 1: masked (default) 0: not masked 0x1fdc8 7-0 maencx_ppp_interrupt 0x00ff tx ppp: mask interrupt for mac0-7 1: masked (default) 0: not masked 0x1fdca 7-0 maencx_ctl_interrupt 0x00ff tx ctl: mask interrupt for mac0-7 1: masked (default) 0: not masked 0x1fdcc 0 maglobaltxlapf 0x0001 tx lapf: global interrupt mask 1: interrupt for lapf alarms for all mac is masked (default) 0: interrupt for lapf alarms for all mac is not masked - 233 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1fdce 0 maglobaltxlaps 0x0001 tx laps: global interrupt mask 1: interrupt for laps alarms for all mac is masked (default) 0: interrupt for laps alarms for all mac is not masked 0x1fdd0 0 maglobaltxgfp 0x0001 tx gfp: global interrupt mask 1: interrupt for gfp alarms for all mac is masked (default) 0: interrupt for gfp alarms for all mac is not masked 0x1fdd2 0 maglobaltxppp 0x0001 tx ppp: global interrupt mask 1: interrupt for ppp alarms for all mac is masked (default) 0: interrupt for ppp alarms for all mac is not masked 0x1fdd4 0 maglobaltxctl 0x0001 tx ctl: global interrupt mask 1: interrupt for ctl alarms for all mac is masked (default) 0: interrupt for ctl alarms for all mac is not masked 0x1fdd6 0 maencap_20m_interrupt 0x0001 tx: global interrupt mask 1: interrupt for all alarms for all mac is masked (default) 0: interrupt for all alarms for all mac is not masked 0x1fdd8 0x1fdda 0x1fddc 0x1fdde 0x1fde0 0x1fde2 0x1fde4 0x1fde6 0 mcount_encx 0x0001 count status bit mask for mac0-7 1: count status bit for each mac is masked (default) 0: count status for each mac is not masked 0x1fde8 0 mcount_enc_20m 0x0001 global count status bit mask 1: global count status bit for all mac is masked (default) 0: global count status for all mac is not masked table 46: encapsulation block - interrupts (ro) address bit hw symbol init description 0x1fc40 0x1ff60 0x10160 0x10560 0x10960 0x10d60 0x11160 0x11560 0 encapx_lapf_interrupt 0x0000 transmit lapf alarm interrupt for mac0-7 1: interrupt for all lapf alarms for each mac 0: no interrupt 0x1fc42 0x1ff62 0x10162 0x10562 0x10962 0x10d62 0x11162 0x11562 0 encapx_laps_interrupt 0x0000 transmit laps alarm interrupt for mac0-7 1: interrupt for all laps alarms for each mac 0: no interrupt 0x1fc44 0x1ff64 0x10164 0x10564 0x10964 0x10d64 0x11164 0x11564 0 encapx_gfp_interrupt 0x0000 transmit gfp alarm interrupt for mac0-7 1: interrupt for all gfp alarms for each mac 0: no interrupt table 45: encapsulation block - alarm and interrupt masks (rw) address bit hw symbol init description - 234 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1fc46 0x1ff66 0x10166 0x10566 0x10966 0x10d66 0x11166 0x11566 0 encapx_ppp_interrupt 0x0000 transmit ppp alarm interrupt for mac0-7 1: interrupt for all ppp alarms for each mac 0: no interrupt 0x1fc48 0x1ff68 0x10168 0x10568 0x10968 0x10d68 0x11168 0x11568 0 encapx_ctl_interrupt 0x0000 transmit ctl alarm interrupt for mac0-7 1: interrupt for all ctl alarms for each mac 0: no interrupt 0x1fc4a 0 txlapf_interrupt 0x0000 global transmit lapf alarm interrupt 1: interrupt for all lapf alarms for all mac 0: no interrupt 0x1fc4c 0 txlaps_interrupt 0x0000 global transmit laps alarm interrupt 1: interrupt for all laps alarms for all mac 0: no interrupt 0x1fc4e 0 txgfp_interrupt 0x0000 global transmit gfp alarm interrupt 1: interrupt for all gfp alarms for all mac 0: no interrupt 0x1fc50 0 txppp_interrupt 0x0000 global transmit ppp alarm interrupt 1: interrupt for all ppp alarms for all mac 0: no interrupt 0x1fc52 0 txctl_interrupt 0x0000 global transmit ctl alarm interrupt 1: interrupt for all ctl alarms for all mac 0: no interrupt 0x1fc54 0 count_interrupt 0x0000 global transmit latched count status bit interrupt 1: interrupt for all latched count status bits 0: no interrupt 0x1fc56 0 encap_20m_interrupt 0x0000 global transmit encapsulation alarm interrupt 1: interrupt for all alarms for all mac before mask 0: no interrupt 0x1fc58 0 encap_global_interrupt 0x0000 global masked transmit encapsulation alarm interrupt 1: interrupt for all alarms for all mac after mask 0: no interrupt table 46: encapsulation block - interrupts (ro) address bit hw symbol init description - 235 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 47: encapsulation block - latched alarms (rr) address bit hw symbol init description 0x1fdbc 0x1ffc0 0x101c0 0x105c0 0x109c0 0x10dc0 0x111c0 0x115c0 0 l1atgfpcsfx 0x0000 tx gfp: latched csf indication alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 1 l1atgfpfmerrx tx gfp: latched incomplete ethernet frame alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 2 l1atgfpmaxerx tx gfp: latched max frame length error for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 3 l1atlfferrx tx lapf: latched fifo error for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 4 l1atlfmaxerx tx lapf: latched max frame length error for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 5 l1atlpferrx tx laps: latched fifo error for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 6 l1atmaxerx tx laps: latched max frame length error for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 7 l1atppferrx tx ppp: latched fifo error for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 8 l1atppmaxerx tx ppp: latched max frame length error for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 9 l1atppmpvdropx tx ppp: latched padding error for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 10 l1atctlxx tx laps/lapf/gfp/ppp: latched control frame buffer empty alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 11 lcount_encx transmit latched count status bit alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched - 236 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers rx decapsulation registers tables 48 through 61 - configuration, status and alarms of the decapsulation block table 48: decapsulation block - general configuration (rw) address bit hw symbol init description 0x1eac0 0x11980 0x11d80 0x12180 0x12580 0x12980 0x12d80 0x13180 1-0 crdecapx 0x0000 receive side decapsulation mode selection for mac0-7 00: see crhdlcx bit below 01: lapf 10: gfp 11: disabled (i.e., no decapsulation is used and block is not used). 0x1eac2 0x11982 0x11d82 0x12182 0x12582 0x12982 0x12d82 0x13182 0 crfcmodex 0x0000 sonet-to-ethernet direction: handling of pause received from sonet/sdh side for macs 0-7 0: pause frames received from sonet/sdh are discarded. (default) 1: pause frames received from sonet/sdh are not discarded and passed onto the ethernet line side. 0x1eac4 0x11984 0x11d84 0x12184 0x12584 0x12984 0x12d84 0x13184 0 crhdlcx 0x0000 rx hdlc encapsulation mode for mac0-7 effective only when crdecapx = 00. 0: laps (default) 1: ppp 0x1eac6 0x11986 0x11d86 0x12186 0x12586 0x12986 0x12d86 0x13186 0 crctlbrstx 0x0000 rx lapf/laps/gfp/ppp: control frame buffer reset for mac0-7 0: reset is not active 1: reset is active 0x1eaca 0x1198a 0x11d8a 0x1218a 0x1258a 0x1298a 0x12d8a 0x1318a 0 crfcsswapinx 0x0000 0: data provided as protocol stated 1: data swapped (msb<-> lsb of the protocol) 0x1eacc 1-0 cinrt_grphol 0x0001 alarm latching configuration for the hol alarm group ( table 58 ) criteria used to create latched alarms from the raw (unlatched) alarms. 00: positive level 01: rising edge 10: falling edge 11: rising or falling edge - 237 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1eace 0x1198c 0x11d8c 0x1218c 0x1258c 0x1298c 0x12d8c 0x1318c 15-0 rrmaxflx 0x0640 rx laps/lapf/gfp/ppp: max frame length for mac0-7 configures the maximum number of bytes per frame, including the fcs bytes, that will be accepted by a mac. frames which exceed this length are discarded and corresponding alarms and counters are triggered default is 0x640 (decimal 1600). 0x1ead0 0x1198e 0x11d8e 0x1218e 0x1258e 0x1298e 0x12d8e 0x1318e 15-0 rrctlmaskax 0xffff mask for filtering laps, gfp and ppp lcp/control frames for channel x laps: mask (per bit basis) in addition to the rsapfdx register to check the sapi field. gfp: mask (per bit basis) in addition to the rrgfpcpx register to check the pti, pfi, exi and upi fields ppp: mask (per bit basis) in addition to the comparison with 0xc021 to detect the lcp control frame. 1: mask is not active 0: mask is active 0x1ead2 0x11990 0x11d90 0x12190 0x12590 0x12990 0x12d90 0x13190 15-0 rrctlmaskbx 0xffff mask for filtering ppp ncp/control frames for channel x mask (per bit basis) in addition to the comparison with 0x8031 to detect the ncp control frame. 1: mask is not active 0: mask is active table 48: decapsulation block - general configuration (rw) address bit hw symbol init description - 238 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 49: decapsulation block - laps configuration (rw) address bit hw symbol init description 0x1ebf0 0x11870 0x11c70 0x12070 0x12470 0x12870 0x12c70 0x13070 0 crscrdx 0x022c rx laps: descrambling control for mac0-7 0: enable descrambling. (default) 1: disable descrambling. 1 crflagx rx laps: flag detection for mac0-7 0: at least two flags to be detected between two consecutive laps frames. (default) 1: at least a single flag to be detected between two consecutive laps frames (i.e., shared flag detection). 2 crfcsx rx laps: fcs enable for mac0-7 0: fcs checking disabled (assume no fcs octets are present) 1: fcs checking enabled. (default) 4-3 cracselx rx laps: address and control checking for mac0-7 00: address and control field contents checking is disabled 01: address and control field contents checking with fixed values. address field content is always checked against 0x04 and control field content is always checked against 0x03. (default) 10: reserved 11: address and control field contents checked against the rracfdx register. 5 crsapix rx laps: sapi checking for mac0-7 0: sapi field contents checking is disabled 1: sapi field contents checked against the rrsapfdx register. (default) 6 crmmaex rx laps: address, control or sapi mismatch for mac0-7 0: laps frame with mismatched address or control or sapi field contents is discarded. (default) 1: laps frame with mismatched address or control or sapi field contents is not discarded. 7 crlpabtgx rx laps: receive frame abort control for mac0-7 0: no action. (default) 1: current frame being received is aborted. 8 crlpfcserx rx laps: fcs discard control for mac0-7 to be used only when fcs checking is enabled as per crfcsx register. 0: received laps framed with fcs errors are discarded (default) 1: received laps frames with fcs errors are not discarded 9 crlppdux rx laps: decapsulation disable for mac0-7 0: decapsulation of laps frames enabled 1: disabled except for control frames 0x1ebf2 0x11872 0x11c72 0x12072 0x12472 0x12872 0x12c72 0x13072 7-0 rrlpminflx 0x0006 rx laps: min laps frame size received for mac0-7 0x06 - 0xff: minimum number of octets in a received laps frame between the opening and closing flags. for laps frames received with less than six octets, an alarm arlpsshterx is gen- erated. decapsulated frames that are less than 5 bytes won ? t pass through the mac. 0x1ebf4 0x11874 0x11c74 0x12074 0x12474 0x12874 0x12c74 0x13074 15-0 rracfdx 0x0403 rx laps: address and control field contents for mac0-7 upper byte (bits 15-8) = content of the address field. default is 0x04. lower byte (bits 7-0) = content of the control field. default is 0x03. - 239 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1ebf6 0x11876 0x11c76 0x12076 0x12476 0x12876 0x12c76 0x13076 15-0 rrsapfdx 0xfe01 rx laps: sapi field contents for mac0-7 upper byte (bits 15-8) = content of the first sapi octet field. default is 0xfe. lower byte (bits 7-0) = content of the second sapi octet field. default is 0x01. 0x1ebf8 0x11878 0x11c78 0x12078 0x12478 0x12878 0x12c78 0x13078 15-0 rrlpcpx 0x0000 rx laps: laps control frame filter only laps control frames with sapi protocol field values matching this register are sent to the host. table 49: decapsulation block - laps configuration (rw) address bit hw symbol init description - 240 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 50: decapsulation block - lapf configuration (rw) address bit hw symbol init description 0x1ea80 0x119a0 0x11da0 0x121a0 0x125a0 0x129a0 0x12da0 0x131a0 0 crlfflagx 0x00a0 rx lapf: flag detection for mac0-7 0: at least two flags to be detected between two consecutive lapf frames. (default) 1: at least a single flag to be detected between two consecutive lapf frames (i.e., shared flag detection). 1 crlfacnopselx rx lapf: address and control and oui and nlpid and pid field contents checking control for mac0-7 0: address and control and oui and nlpid and pid field contents check- ing enabled. (default) address field contents are checked against rrlfadrx control field contents are checked against rrlfcntlx oui field contents are checked against rrouix nlpid field contents are checked against rrnlpidx pid field contents are checked against rrpidx 1: address and control and oui and nlpid and pid field contents check- ing disabled. 2 crlmidlcix rx lapf: lmi frame dlci value selection for mac0-7 0: dlci = 0 to be checked to filter lmi frame. (default) 1: dlci = 1023 to be checked to filter lmi frame. 3 crlfpadx rx lapf: lapf pad contents checking for mac0-7 0: lapf pad field contents checked against the rrpadx register. (default) 1: lapf pad field contents checking is disabled. 4 crlfmmaex rx lapf: address or control or oui or nlpid or pid or pad field con- tents mismatch discard frame control for mac0-7 0: lapf frame with mismatched address or control or oui or nlpid or pid or pad field contents is discarded. 1: lapf frame with mismatched address or control or oui or nlpid or pid or pad field contents is not discarded. (default) 5 crlffcsx rx lapf: fcs enable for mac0-7 0: lapf fcs checking disabled and assume the two fcs field octets are not present. (default) 1: lapf fcs checking enabled. 6 crlffcserx rx lapf: fcs discard for mac0-7 0: received lapf frames with fcs error are discarded. 1: received lapf frames with fcs error are not discarded. (default) 7 crlfpdux rx lapf: lapf frame types for mac0-7 0: all lapf frame types received frames from sonet/sdh are allowed to be decapsulated. 1: only lapf lmi frames matching the crlmidlcix register are allowed to be decapsulated. (default) 0x1ea82 0x119a2 0x11da2 0x121a2 0x125a2 0x129a2 0x12da2 0x131a2 7-0 rrlfminflx 0x0003 rx lapf: min. lapf frame size received for mac0-7 0x03 - 0xff: minimum number of octets in a received lapf frame between the address field and closing flag. for lapf frames received with less than three octets, an alarm arlfsserx is generated. decapsulated frames that are less than 5 bytes won ? t pass through the mac. - 241 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1ea84 0x119a4 0x11da4 0x121a4 0x125a4 0x129a4 0x12da4 0x131a4 15-0 rrlfadrx 0x0401 rx lapf: address field contents for mac0-7 upper byte (bits 15-8) = contents of the upper dlci (bits 15-10) and c/r (bit 9) and ea (bit 8) fields. default set to 0x04. lower byte (bits 7-0) = contents of the lower dlci (bits 7-4) and fecn (bit 3) and becn (bit 2) and de (bit 1) and ea (bit 0) fields. default set to 0x01. 0x1ea86 0x119a6 0x11da6 0x121a6 0x125a6 0x129a6 0x12da6 0x131a6 7-0 rrlfcntlx 0x0003 rx lapf: control field contents for mac0-7 range 0x00-0xff: indicates control field contents when checking is enabled. default set to 0x03. 0x1ea88 0x119a8 0x11da8 0x121a8 0x125a8 0x129a8 0x12da8 0x131a8 7-0 rrpadx 0x0000 rx lapf: pad field contents for mac0-7 range 0x00-0xff: indicates pad field contents when checking is enabled. default set to 0x00. 0x1ea8a 0x119aa 0x11daa 0x121aa 0x125aa 0x129aa 0x12daa 0x131aa 7-0 rrnlpidx 0x0080 rx lapf: nlpid field contents for mac0-7 range 0x00-0xff: indicates nlpid field contents when checking is enabled. default set to 0x80. 0x1ea8c 0x119ac 0x11dac 0x121ac 0x125ac 0x129ac 0x12dac 0x131ac 7-0 rrouix(1) 0x0000 rx lapf: oui field contents (msb bits) for mac0-7 range 0x00-0xff: indicates oui field (msb bits) contents when checking is enabled. default set to 0x00. 0x1ea8e 0x119ae 0x11dae 0x121ae 0x125ae 0x129ae 0x12dae 0x131ae 15-0 rrouix(0) 0x80c2 rx lapf: oui field contents (lsb bits) for mac0-7 range 0x0000-0xffff: indicates oui field (lsb bits) contents when checking is enabled. default set to 0x80c2. 0x1ea90 0x119b0 0x11db0 0x121b0 0x125b0 0x129b0 0x12db0 0x131b0 15-0 rrpidx 0x0007 rx lapf: pid field contents for mac0-7 upper byte (bits 15-8) = contents of the first pid octet field. default set to 0x00. lower byte (bits 7-0) = contents of the second pid octet field. default set to 0x07. table 50: decapsulation block - lapf configuration (rw) address bit hw symbol init description - 242 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 51: decapsulation block - control buffer status (rw) address bit hw symbol init description 0x1ebe0 0x11860 0x11c60 0x12060 0x12460 0x12860 0x12c60 0x13060 0 srctlbx 0x0000 rx lapf/laps/ppp/gfp: control buffer full for mac0-7 0: control buffer is empty (host read access is disabled) 1: control buffer contains a single complete control frame (host read access is enabled). once the control frame is read, the host needs to clear this bit in order to detect the arrival of another lmi frame. table 52: decapsulation block - link status (ro) address bit hw symbol init description 0x1ebe8 0x11868 0x11c68 0x12068 0x12468 0x12868 0x12c68 0x13068 0 slnkstsx 0x0000 rx lapf: link status for mac0-7 0: lapf link is down. (default) 1: lapf link is up. 1 reserved reserved - 243 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 53: decapsulation block - gfp configuration (rw) address bit hw symbol init description 0x1eb40 0x119f0 0x11df0 0x121f0 0x125f0 0x129f0 0x12df0 0x131f0 0 crcdscrx 0x0800 rx gfp: core header descrambling disable for mac0-7 0: enable descrambling of gfp core header only. (default) 1: disable descrambling of gfp core header only. 1 crcordisx rx gfp: core header single-bit error correction control for mac0-7 0: enable single bit error correction and all frames with single bit error corrected are passed. frames with multiple-bit errors are discarded. (default) 1: disable single bit error correction. all frames with errors are discarded. 2 crthecsx rx gfp: type header single-bit error correction control for mac0-7 0: enable single bit error correction and all frames with single bit error corrected are passed. frames with multiple-bit errors are discarded. (default) 1: disable single bit error correction. all frames with errors are discarded. 3 crehecsx rx gfp: extension header single-bit error correction control for mac0-7 0: enable single bit error correction and all frames with single bit error corrected are passed. frames with multiple-bit errors are discarded. (default) 1: disable single bit error correction. all frames with errors are discarded. 4 crpscrdx rx gfp: payload area descrambling control for mac0-7 0: enable descrambling of gfp payload area only. (default) 1: disable descrambling of gfp payload area only. 7-5 crdeltax rx gfp: re-synchronization control for mac0-7 0x0-0x7: indicates values of delta to be used in the gfp delineation process. (default=0x1) 8 crgfpabtgx rx gfp: receive frame abort control for mac0-7 0: no action. (default) 1: current frame being received is aborted. 9 crgfpfcserx rx gfp: fcs discard for mac0-7 0: received gfp frames with fcs error are discarded. (default) 1: received gfp frames with fcs error are not discarded. 10 crgfphdrx rx gfp: null/linear header processing control for mac0-7 0: only null extension header frame are processed. other frame types are dis- carded. (default) 1: only linear extension header frame are processed. other frame types are dis- carded 11 crgfppdu0 rx gfp: decapsulation disable for mac0-7 0: decapsulation of frames enabled 1: disabled except for control frames 0x1eb42 0x119f2 0x11df2 0x121f2 0x125f2 0x129f2 0x12df2 0x131f2 7-0 crgfpcidx0 0x0000 rx gfp: cid value 0 for vcg0-7 0x00-0xff: cid value #0 (among the list of allowed eight cid values) per vcg to be compared with the actual received cid field value. 15-8 crgfpcidx1 rx gfp: cid value 1 for vcg0-7 0x00-0xff: cid value #1 (among the list of allowed eight cid values) per vcg to be compared with the actual received cid value. 0x1eb44 0x119f4 0x11df4 0x121f4 0x125f4 0x129f4 0x12df4 0x131f4 7-0 crgfpcidx2 0x0000 rx gfp: cid value 2 for vcg0-7 0x00-0xff: cid value #2 (among the list of allowed eight cid values) per vcg to be compared with the actual received cid value. 15-8 crgfpcidx3 rx gfp: cid value 3 for vcg0-7 0x00-0xff: cid value #3 (among the list of allowed eight cid values) per vcg to be compared with the actual received cid value. - 244 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1eb46 0x119f6 0x11df6 0x121f6 0x125f6 0x129f6 0x12df6 0x131f6 7-0 crgfpcidx4 0x0000 rx gfp: cid value 4 for vcg0-7 0x00-0xff: cid value #4 (among the list of allowed eight cid values) per vcg to be compared with the actual received cid value. 15-8 crgfpcidx5 rx gfp: cid value 5 for vcg0-7 0x00-0xff: cid value #5 (among the list of allowed eight cid values) per vcg to be compared with the actual received cid value. 0x1eb48 0x119f8 0x11df8 0x121f8 0x125f8 0x129f8 0x12df8 0x131f8 7-0 crgfpcidx6 0x0000 rx gfp: cid value 6 for vcg0-7 0x00-0xff: cid value #6 (among the list of allowed eight cid values) per vcg to be compared with the actual received cid value. 15-8 crgfpcidx7 rx gfp: cid value 7 for vcg0-7 0x00-0xff: cid value #7 (among the list of allowed eight cid values) per vcg to be compared with the actual received cid value. 0x1eb4a 0x119fa 0x11dfa 0x121fa 0x125fa 0x129fa 0x12dfa 0x131fa 7-0 clecidx 0x00ff rx gfp: local-end cid field configuration for mac0-7 0x00-0xff: indicates a unique local-end cid value assigned to a local mac port. (default=0x00) 0x1eb4c 0x119fc 0x11dfc 0x121fc 0x125fc 0x129fc 0x12dfc 0x131fc 15-0 rrgfpcpx 0x8000 rx gfp: control frame filter gfp client management/control frames with type field values matching this register are forwarded to the host. default is 0x9000. bits 15-13: pti field bit 12: pfi field bits 11-8: exi field bits 7-0: upi field table 53: decapsulation block - gfp configuration (rw) address bit hw symbol init description - 245 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 54: decapsulation block - ppp configuration (rw) address bit hw symbol init description 0x1eba0 0x11840 0x11c40 0x12040 0x12440 0x12840 0x12c40 0x13040 0 crpacmmaex 0x48b2 rx ppp: address and control discard control for mac0-7 0: discard ppp frames with mismatched address or control fields (default) 1: no discard of mismatched frames 2-1 crpacselx rx ppp: address and control checking for mac0-7 00: address and control field contents checking is disabled 01: address and control field contents checking with fixed val- ues. address field content is always checked against 0xff and control field content is always checked against 0x03. (default) 10: reserved 11: address and control field contents checked against the rrpacfdx register. 3 crpcrcsx rx ppp: fcs algorithm for mac0-7 0: crc-32 (default) 1: crc-16 4 crpfcsx rx ppp: fcs enable for mac0-7 0: fcs checking disabled (assume no fcs octets are present) 1: fcs checking enabled (default) 5 crpfgx rx ppp: flag field matching for mac0-7 0: disabled 1: bcp flag fields are matched against the rrpfpgfdx register (default) 6 crpfgmmaex rx ppp: flag field discard control for mac0-7 0: discard ppp frames with mismatched flag fields (default) 1: no discard of mismatched frames 7 crpmacx rx ppp: type field matching for mac0-7 0: disabled 1: bcp type fields are matched against the rrpmacfdx register (default) 8 crpmacmmaex rx ppp: type field discard control for mac0-7 0: discard ppp frames with mismatched type fields (default) 1: no discard of mismatched frames 9 crpppabtgx rx ppp: receive frame abort control for mac0-7 0: no action. (default) 1: current frame being received is aborted. 10 crpppcserx rx ppp: fcs discard for mac0-7 0: received ppp frames with fcs error are discarded. (default) 1: received ppp frames with fcs error are not discarded. 11 crpprotx rx ppp: protocol field matching for mac0-7 0: disabled 1: protocol fields are matched against the rrpprotfdx register (default) 12 crpprotmmaex rx ppp: protocol field discard control for mac0-7 0: discard ppp frames with mismatched protocol fields (default) 1: no discard of mismatched frames 13 crbcppdmodex rx ppp: padding mode for ppp/bcp frames for mac0-7 0: disabled (default) 1: fixed padding mode is used 14 crbpdux rx ppp: frame decapsulation enable for mac0-7 0: all ppp frames are decapsulated from the sonet/sdh stream. 1: ppp frames with protocol field = 0x0031 are not decapsulated. lcp/ncp-bcp frames for the host continue to be decapsulated (default). - 246 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1eba2 0x11842 0x11c42 0x12042 0x12442 0x12842 0x12c42 0x13042 15-0 rrpacfdx 0xff03 rx ppp: address and control values for mac0-7 bits 15-8: address field bits 7-0: control field 0x1eba4 0x11844 0x11c44 0x12044 0x12444 0x12844 0x12c44 0x13044 3-0 rrpfpgfdx 0x000a rx ppp: bcp flag field match register for mac0-7 bit 3 is the expected f bit, bit 2 is the expected 0 bit, bit 1 is the expected z bit, and bit 0 is the expected b bit. 0x1eba6 0x11846 0x11c46 0x12046 0x12446 0x12846 0x12c46 0x13046 15-0 rrplcpx 0xc021 rx ppp: lcp frame filter for mac0-7 only lcp frames with ppp protocol field values matching this register are forwarded to the host. default is 0xc021. 0x1eba8 0x11848 0x11c48 0x12048 0x12448 0x12848 0x12c48 0x13048 7-0 rrpmacfdx 0x0101 rx ppp: bcp type field match register for mac0-7 rx gfp: gfp upi field match register for mac0-7 in gfp mode, client data frames with mismatched type header upi fields are discarded and the rgfpeerrx alarm is asserted. 0x1ebaa 0x1184a 0x11c4a 0x1204a 0x1244a 0x1284a 0x12c4a 0x1304a 15-0 rrpncpx 0x8031 rx ppp: ncp-bcp frame filter for mac0-7 only ncp-bcp frames with ppp protocol field values matching this register are forwarded to the host. default is 0x8031. 0x1ebac 0x1184c 0x11c4c 0x1204c 0x1244c 0x1284c 0x12c4c 0x1304c 7-0 rrpppminflx 0x0006 rx ppp: min frame length for mac0-7 indicates the minimum number of octets that must be present in a received frame (between two flags). frames smaller than this length but greater than 4 (16-bit fcs) or 6 (32-bit fcs) are not discarded, but trigger appropriate alarms and counters. default is 0x04 for 16-bit fcs, 0x06 for 32-bit fcs. 0x1ebae 0x1184e 0x11c4e 0x1204e 0x1244e 0x1284e 0x12c4e 0x1304e 15-0 rrpprotfdx 0x0031 rx ppp: protocol field match register for mac0-7 bits 15-8: first octet of protocol field bits 7-0: second octet of protocol field table 54: decapsulation block - ppp configuration (rw) address bit hw symbol init description - 247 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 55: decapsulation block - lmi buffers (ro) address bit hw symbol init description 0x1e900 ? 0x1e97e 0x11900 ? 0x1197e 0x11d00 ? 0x11d7e 0x12100 ? 0x1217e 0x12500 ? 0x1257e 0x12900 ? 0x1297e 0x12d00 ? 0x12d7e 0x13100 ? 0x1317e 8-0 rrlmix_[64] 0x0000 rx lapf: lmi buffers 0 through 63 for mac0-7 note: each address buffer utilizes bits 8-0. each mac has 64 bytes x 8 bits of storage for a single lapf lmi frame. the msb bit (bit 8), when set to ? 1 ? of each byte, indicates that this byte (bits 7-0) is part of the lapf lmi frame. this holds true up to the first byte where the msb bit (bit 8) is set to 0. all bytes after and including the byte with the msb bit (bit 8) set to 0, should be ignored by the host. table 56: decapsulation block - alarms (ro) address bit hw symbol init description note: the gfp decapsulation alarms are only updated when: 1) at least one tributary is assigned to the vcg, and 2) none of the tributaries assigned to the vcg have sonet/sdh failures such as ssf, deg, ais, plm, uneq or lom. 0x1ebc0 0x11800 0x11c00 0x12000 0x12400 0x12800 0x12c00 0x13000 0 alnkstsdwnx 0x0000 rx lapf: link down alarm for mac0-7 0: no alarm 1: detection of the transition from link up to link down 1 alnkstsupx rx lapf: link up alarm for mac0-7 0: no alarm 1: detection of the transition from link down to link up 2 arlfabtdx rx lapf: abort indication for mac0-7 0: no alarm. 1: detection of an aborted frame. cleared on the next valid frame. 3 arlffcerx rx lapf: fcs error for mac0-7 0: no alarm 1: detection of a frame with fcs error. cleared on the next valid frame 4 arlffserx rx lapf: frame size error for mac0-7 0: no alarm 1: detection of a frame with length less than 3 bytes. cleared on the next valid frame 5 arlfmaxerx rx lapf: max frame size error for mac0-7 0: no alarm 1: detection of a frame with length higher than rrmaxflx register 6 arlfminerx rx lapf: min frame size error for mac0-7 0: no alarm 1: detection of a frame with length lower than rrminflx register 7 arlfmmx rx lapf: frame mismatch error for mac0-7 0: no alarm 1: detection of a frame with error on address, control, nlpid, oui, pad or pid field. cleared on the next valid frame. - 248 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1ebc2 0x11802 0x11c02 0x12002 0x12402 0x12802 0x12c02 0x13002 0 arlpsabtdx 0x0000 rx laps: abort indication for mac0-7 0: no alarm. 1: detection of an aborted frame. cleared on the next valid frame. 1 arlpsfcserx rx laps: fcs error for mac0-7 0: no alarm 1: detection of a laps frame with fcs error. cleared on the next valid frame 2 arlpsfmmx rx laps: frame mismatch error for mac0-7 0: no alarm 1: detection of a frame with error on address, control or sapi field. cleared on the next valid frame. 3 arlpsminerx rx laps: min frame size error for mac0-7 0: no alarm 1: detection of a frame with length lower than rrlpminflx register 4 arlpsshterx rx laps: frame size error for mac0-7 0: no alarm 1: detection of a frame with length less than 6 bytes. cleared on the next valid frame 5 arlpsmaxerx rx laps: max frame size error for mac0-7 0: no alarm 1: detection of a frame with length higher than rrmaxflx register table 56: decapsulation block - alarms (ro) address bit hw symbol init description - 249 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1ebc4 0x11804 0x11c04 0x12004 0x12404 0x12804 0x12c04 0x13004 0 argfpciderrx 0x0000 rx gfp: frame cid error for mac0-7 0: no alarm 1: detection of an unsupported value of cid. cleared on the next valid frame with correct cid value or an idle frame. 1 argfpehecerrx rx gfp: ehec error for mac0-7 0: no alarm 1: detection of a single bit error on the ehec. cleared on the reception of a frame with no error on ehec or reception of an idle frame. 2 argfpexierrx rx gfp: exi error for mac0-7 0: no alarm 1: detection of a mismatch of the exi value with the crgfphdrx register. cleared on the next valid frame. 3 argfpfcserx rx gfp: payload area fcs error for mac0-7 0: no alarm 1: detection of a frame with payload fcs error. cleared on the next valid frame. 4 argfpfecsfx rx gfp: far end csf indication for mac0-7 0: no alarm 1: detection of a csf indication. cleared on receipt of the first valid gfp cli- ent data frame, or after failing to receive 3 csf indications in 3 seconds. 5 argfphuntx rx gfp: hunt state alarm for mac0-7 0: state machine is in a state different from hunt 1: state machine is in a hunt state 6 argfplofx rx gfp: loss of frame delineation alarm for mac0-7 0: no alarm 1: while in sync state, when a core header with multiple-bit errors is detected or a single-bit error detected and transitions to the hunt state. cleared on entering in sync state 7 argfpmaxerx rx gfp: max length error for mac0-7 0: no alarm 1: detection of a frame with length higher than rrmaxflx register 8 argfpmchecerrx rx gfp: multiple bit error for mac0-7 0: no alarm 1: detection of multiple-bit errors in the core header while in hunt, pre- sync or sync states. cleared on reception of a frame without multiple-bit errors in the core header or reception of an idle frame. 9 argfppresyncx rx gfp: presync state alarm for mac0-7 0: state machine is in a state different from presync 1: state machine is in a presync state 10 argfpptierrx rx gfp: pti error for mac0-7 0: no alarm 1: detection of a received pti value different from 000 or 100. cleared on correct received pti value or on reception of gfp idle frame. 11 argfpschecerrx rx gfp: single bit error for mac0-7 0: no alarm 1: while in sync state, when a core header with single-bit errors is detected while in hunt or presync or sync states. cleared on reception of no sin- gle-bit error frame or gfp idle frame reception table 56: decapsulation block - alarms (ro) address bit hw symbol init description - 250 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1ebc4 0x11804 0x11c04 0x12004 0x12404 0x12804 0x12c04 0x13004 12 argfpsyncx 0x0000 rx gfp: sync state alarm for mac0-7 0: state machine is in a state different from sync 1: state machine is in a sync state 13 argfpthecerrx rx gfp: type header check error for mac0-7 14 argfpeerrx rx gfp: upi error for mac0-7 0x1ebc6 0x11806 0x11c06 0x12006 0x12406 0x12806 0x12c06 0x13006 0 argfpfecsfcidx0 0x0000 rx gfp: far end csf indication 0 per matching cid alarm for mac0-7 0: no alarm 1: detection of a matching cid value #0 and far end csf indication. cleared on reception of cid matching value or after failing to receive 3 csf indica- tions in 3000 ms. 1 argfpfecsfcidx1 rx gfp: far end csf indication 1 per matching cid alarm for mac0-7 0: no alarm 1: detection of a matching cid value #1 and far end csf indication. cleared on reception of cid matching value or after failing to receive 3 csf indica- tions in 3000 ms. 2 argfpfecsfcidx2 rx gfp: far end csf indication 2 per matching cid alarm for mac0-7 0: no alarm 1: detection of a matching cid value #2 and far end csf indication. cleared on reception of cid matching value or after failing to receive 3 csf indica- tions in 3000 ms. 3 argfpfecsfcidx3 rx gfp: far end csf indication 3 per matching cid alarm for mac0-7 0: no alarm 1: detection of a matching cid value #3 and far end csf indication. cleared on reception of cid matching value or after failing to receive 3 csf indica- tions in 3000 ms. 4 argfpfecsfcidx4 rx gfp: far end csf indication 4 per matching cid alarm for mac0-7 0: no alarm 1: detection of a matching cid value #4 and far end csf indication. cleared on reception of cid matching value or after failing to receive 3 csf indica- tions in 3000 ms. 5 argfpfecsfcidx5 rx gfp: far end csf indication 5 per matching cid alarm for mac0-7 0: no alarm 1: detection of a matching cid value #5 and far end csf indication. cleared on reception of cid matching value or after failing to receive 3 csf indica- tions in 3000 ms. 6 argfpfecsfcidx6 rx gfp: far end csf indication 6 per matching cid alarm for mac0-7 0: no alarm 1: detection of a matching cid value #6 and far end csf indication. cleared on reception of cid matching value or after failing to receive 3 csf indica- tions in 3000 ms. 7 argfpfecsfcidx7 rx gfp: far end csf indication 7 per matching cid alarm for mac0-7 0: no alarm 1: detection of a matching cid value #7 and far end csf indication. cleared on reception of cid matching value or after failing to receive 3 csf indica- tions in 3000 ms. 0x1ebca 0x1180a 0x11c0a 0x1200a 0x1240a 0x1280a 0x12c0a 0x1300a 0 arctlrxx 0x0000 rx laps/lapf/gfp/ppp: host frame received alarm for mac0-7 1 arctlberrx rx laps/lapf/gfp/ppp: control frame buffer overflow for mac0-7 table 56: decapsulation block - alarms (ro) address bit hw symbol init description - 251 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1ebcc 0x1180c 0x11c0c 0x1200c 0x1240c 0x1280c 0x12c0c 0x1300c 0 count_decapx 0x0000 rx decapsulation: count status bit for mac0-7 1: when any of the performance counters of each decapsulation block (asso- ciated to each vcg) has reached its maximum value in the saturating mode only 0: after being read by the microprocessor table 57: decapsulation block - alarm and interrupt masks (rw) address bit hw symbol init description 0x1ea00 0x119c0 0x11dc0 0x121c0 0x125c0 0x129c0 0x12dc0 0x131c0 0 malnkstsdwnx 0x00ff rx lapf: link down alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 1 malnkstsupx rx lapf: link up alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 2 marlfabtdx rx lapf: abort indication mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 3 marlffcerx rx lapf: fcs error mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 4 marlffserx rx lapf: frame size error mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 5 marlfmaxerx rx lapf: max frame size error mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 6 marlfminerx rx lapf: min frame size error mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 7 marlfmmx rx lapf: frame mismatch error mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 0x1ea02 0x119c2 0x11dc2 0x121c2 0x125c2 0x129c2 0x12dc2 0x131c2 0 marlpsabtdx 0x003f rx laps: abort indication mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 1 marlpsfcserx rx laps: fcs error alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 2 marlpsfmmx rx laps: frame mismatch error alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 3 marlpsminerx rx laps: min frame size error alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 4 marlpsshterx rx laps: frame size error alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 5 marlpsmaxerx rx laps: max frame size error alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked table 56: decapsulation block - alarms (ro) address bit hw symbol init description - 252 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1ea04 0x119c4 0x11dc4 0x121c4 0x125c4 0x129c4 0x12dc4 0x131c4 0 margfpciderrx 0x7fff rx gfp: frame cid error alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 1 margfpehecerrx rx gfp: ehec error alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 2 margfpexierrx rx gfp: exi error alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 3 margfpfcserx rx gfp: payload area fcs error alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 4 margfpfecsfx rx gfp: far end csf indication mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 5 margfphuntx rx gfp: hunt state alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 6 margfplofx rx gfp: loss of frame delineation alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 7 margfpmaxerx rx gfp: maximum length error alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 8 margfpmchecerrx rx gfp: multiple bit error alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 9 margfppresyncx rx gfp: presync state alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 10 margfpptierrx rx gfp: pti error alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 11 margfpschecerrx rx gfp: single bit error alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 12 margfpsyncx rx gfp: sync state alarm mask for mac0 1: alarm is masked (default) 0: alarm is not masked 13 margfpthecerrx rx gfp: type header check error alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 14 margfpupierrx rx gfp: upi error alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked table 57: decapsulation block - alarm and interrupt masks (rw) address bit hw symbol init description - 253 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1ea06 0x119c6 0x11dc6 0x121c6 0x125c6 0x129c6 0x12dc6 0x131c6 0 margfpfecsfcidx0 0x00ff rx gfp: far end csf indication 0 per matching cid alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 1 margfpfecsfcidx1 rx gfp: far end csf indication 1 per matching cid alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 2 margfpfecsfcidx2 rx gfp: far end csf indication 2 per matching cid alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 3 margfpfecsfcidx3 rx gfp: far end csf indication 3 per matching cid alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 4 margfpfecsfcidx4 rx gfp: far end csf indication 4 per matching cid alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 5 margfpfecsfcidx5 rx gfp: far end csf indication 5 per matching cid alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 6 margfpfecsfcidx6 rx gfp: far end csf indication 6 per matching cid alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 7 margfpfecsfcidx7 rx gfp: far end csf indication 7 per matching cid alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 0x1ea08 0x119c8 0x11dc8 0x121c8 0x125c8 0x129c8 0x12dc8 0x131c8 0 marpacmmx 0x01ff rx ppp: address or control field mismatch error alarm mask for mac0-7 1 marpfgmmx rx ppp: bcp flags field mismatch error alarm mask for mac0-7 2 marpmacmmx rx ppp: bcp mac type field mismatch error alarm mask for mac0-7 3 marpppabtdx rx ppp: abort indication alarm mask for mac0-7 4 marpppfcserx rx ppp: fcs error alarm mask for mac0-7 5 marpppmaxerx rx ppp: max frame size error alarm mask for mac0-7 6 marpppminerx rx ppp: min frame size error alarm mask for mac0-7 7 marpppshterx rx ppp: frame size error alarm mask for mac0-7 8 marpprotmmx rx ppp: ppp protocol field mismatch error alarm mask for mac0-7 0x1ea0a 0x119ca 0x11dca 0x121ca 0x125ca 0x129ca 0x12dca 0x131ca 0 marctlrxx 0x0003 rx laps/lapf/gfp/ppp: host frame received alarm mask 1 marctlberrx rx laps/lapf/gfp/ppp: control frame buffer overflow alarm mask 0x1ea0c 7-0 maegenx_lapf_interrupt 0x00ff rx lapf: interrupt mask for mac0-7 1: interrupt for all lapf alarms of each mac is masked (default) 0: interrupt for all lapf alarms of each mac is not masked 0x1ea0e 7-0 maegenx_laps_interrupt 0x00ff rx laps: interrupt mask for mac0-7 1: interrupt for all laps alarms of each mac is masked (default) 0: interrupt for all laps alarms of each mac is not masked 0x1ea10 7-0 maegenx_gfp_interrupt 0x00ff rx gfp: interrupt mask for mac0-7 1: interrupt for all gfp alarms of each mac is masked (default) 0: interrupt for all gfp alarms of each mac is not masked table 57: decapsulation block - alarm and interrupt masks (rw) address bit hw symbol init description - 254 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1ea12 7-0 maegenx_gfpcid_interrupt 0x00ff rx lapf: cid interrupt mask for mac0-7 1: interrupt for all cid alarms of each mac is masked (default) 0: interrupt for all cid alarms of each mac is not masked 0x1ea14 7-0 maegenx_ppp_interrupt 0x00ff rx ppp: interrupt alarm mask for mac0-7 1: interrupt for all ppp alarms of each mac is masked (default) 0: interrupt for all ppp alarms of each mac is not masked 0x1ea16 7-0 maegenx_ctlrx_interrupt 0x00ff rx laps/lapf/gfp/ppp: host interrupt alarm mask for mac0-7 1: interrupt for all frames to the host from each mac is masked (default) 0: interrupt for all frames to the host from each mac is not masked 0x1ea18 7-0 mcount_decapx 0x00ff rx decapsulation: global count status bit mask 1: count status is masked (default) 0: count status is not masked 0x1ea1a 0 maglobalrxlapf 0x0001 rx lapf: global interrupt mask 1: interrupt for all lapf alarms of all mac is masked (default) 0: interrupt for all lapf alarms of all mac is not masked 0x1ea1c 0 maglobalrxlaps 0x0001 rx laps: global interrupt mask 1: interrupt for all laps alarms of all mac is masked (default) 0: interrupt for all laps alarms of all mac is not masked 0x1ea1e 0 maglobalrxgfp 0x0001 rx gfp: global interrupt mask 1: interrupt for all gfp alarms of all mac is masked (default) 0: interrupt for all gfp alarms of all mac is not masked 0x1ea20 0 maglobalrxgfpcid 0x0001 rx gfp: global cid interrupt mask 1: interrupt for all cid alarms of all mac is masked (default) 0: interrupt for all cid alarms of all mac is not masked 0x1ea22 0 maglobalrxppp 0x0001 rx ppp: global interrupt mask 1: interrupt for all ppp alarms of all mac is masked (default) 0: interrupt for all ppp alarms of all mac is not masked 0x1ea24 0 maglobalrxctl 0x0001 rx laps/lapf/gfp/ppp: global host frame interruption for mac0 1: interrupt for all frames to the host from mac0 is masked (default) 0: interrupt for all frames to the host from mac0 is not masked 0x1ea26 0 madecap_100m_interrupt 0x0001 rx: global mask interrupt 1: interrupt of all decapsulation blocks (all modes) is masked (default) 0: interrupt of all decapsulation blocks (all modes) is not masked 0x1ea28 0 mcount_decap_100m 0x0001 global count status bit mask for physical block sdram controller 1: count status bit of all decapsulation blocks is masked (default) 0: count status bit of all decapsulation blocks is not masked table 57: decapsulation block - alarm and interrupt masks (rw) address bit hw symbol init description - 255 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 58: decapsulation block - latched alarms (rr) address bit hw symbol init description 0x1eb60 0x11820 0x11c20 0x12020 0x12420 0x12820 0x12c20 0x13020 0 l1alnkstsdwnx 0x0000 rx lapf: link status down latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 1 l1alnkstsupx rx lapf: link status up latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 2 l1arlfabtdx rx lapf: abort indication latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 3 l1arlffcerx rx lapf: fcs error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 4 l1arlffserx rx lapf: frame size error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 5 l1arlfmaxerx rx lapf: max frame size error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 6 l1arlfminerx rx lapf: min frame size error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 7 l1arlfmmx rx lapf: frame mismatch error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 0x1eb62 0x11822 0x11c22 0x12022 0x12422 0x12822 0x12c22 0x13022 0 l1arlpsabtdx 0x0000 rx laps: abort indication latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 1 l1arlpsfcserx rx laps: fcs error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 2 l1arlpsfmmx rx laps: frame mismatch error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 3 l1arlpsminerx rx laps: min frame size error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 4 l1arlpsshterx rx laps: frame size error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 5 l1arlpsmaxerx rx laps: max frame size error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched - 256 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1eb64 0x11824 0x11c24 0x12024 0x12424 0x12824 0x12c24 0x13024 0 l1argfpciderrx 0x0000 rx gfp: frame cid error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 1 l1argfpehecerrx rx gfp: extension header check error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 2 l1argfpexierrx rx gfp: exi error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 3 l1argfpfcserx rx gfp: payload area fcs check error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 4 l1argfpfecsfx rx gfp: far end csf indication latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 5 l1argfphuntx rx gfp: hunt state latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 6 l1argfplofx rx gfp: loss of frame delineation latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 7 l1argfpmaxerx rx gfp: maximum length error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 8 l1argfpmchecerrx rx gfp: multiple bit error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 9 l1argfppresyncx rx gfp: presync state latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 10 l1argfpptierrx rx gfp: pti error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 11 l1argfpschecerrx rx gfp: single bit error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 12 l1argfpsyncx rx gfp: sync state latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 13 l1argfpthecerrx rx gfp: type header check error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 14 l1argfpupierrx rx gfp: upi error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched table 58: decapsulation block - latched alarms (rr) address bit hw symbol init description - 257 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1eb66 0x11826 0x11c26 0x12026 0x12426 0x12826 0x12c26 0x13026 0 l1argfpfecsfcidx0 0x0000 rx gfp: far end csf indication 0 per matching cid latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 1 l1argfpfecsfcidx1 rx gfp: far end csf indication 1 per matching cid latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 2 l1argfpfecsfcidx2 rx gfp: far end csf indication 2 per matching cid latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 3 l1argfpfecsfcidx3 rx gfp: far end csf indication 3 per matching cid latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 4 l1argfpfecsfcidx4 rx gfp: far end csf indication 4 per matching cid latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 5 l1argfpfecsfcidx5 rx gfp: far end csf indication 5 per matching cid latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 6 l1argfpfecsfcidx6 rx gfp: far end csf indication 6 per matching cid latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 7 l1argfpfecsfcidx7 rx gfp: far end csf indication 7 per matching cid latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 0x1eb68 0x11828 0x11c28 0x12028 0x12428 0x12828 0x12c28 0x13028 0 l1arpacmmx 0x0000 rx ppp: address or control field mismatch error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 1 l1arpfgmmx rx ppp: bcp flags field mismatch error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 2 l1arpmacmmx rx ppp: bcp mac type field mismatch error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 3 l1arpppabtdx rx ppp: abort indication latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 4 l1arpppfcserx rx ppp: fcs error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 5 l1arpppmaxerx rx ppp: max frame size error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 6 l1arpppminerx rx ppp: min frame size error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 7 l1arpppshterx rx ppp: frame size error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 8 l1arpprotmmx rx ppp: ppp protocol field mismatch error latched alarm for mac0-7 1: alarm is latched (clear on read) for each mac 0: no alarm is latched table 58: decapsulation block - latched alarms (rr) address bit hw symbol init description - 258 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1eb6a 0x1182a 0x11c2a 0x1202a 0x1242a 0x1282a 0x12c2a 0x1302a 0 l1arctlrxx 0x0000 rx laps/lapf/gfp/ppp: host frame received latched alarm 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 1 l1arctlberrx rx laps/lapf/gfp/ppp: control frame buffer overflow latched alarm 1: alarm is latched (clear on read) for each mac 0: no alarm is latched 0x1eb6c 0x1182c 0x11c2c 0x1202c 0x1242c 0x1282c 0x12c2c 0x1302c 0 lcount_decapx 0x0000 rx de-encapsulation: latched status bit count for mac0-7 1: status bit count is latched for each mac 0: status bit count is not latched for each mac table 59: decapsulation block - interrupts (ro) address bit hw symbol init description 0x1eb00 0x119d0 0x11dd0 0x121d0 0x125d0 0x129d0 0x12dd0 0x131d0 0 lapf_interrupt 0x0000 rx lapf: interruption for mac0-7 1: interrupt for all lapf alarms for each mac 0: no interrupt 0x1eb02 0x119d2 0x11dd2 0x121d2 0x125d2 0x129d2 0x12dd2 0x131d2 0 laps_interrupt 0x0000 rx laps: interruption for mac0-7 1: interrupt for all laps alarms for each mac 0: no interrupt 0x1eb04 0x119d4 0x11dd4 0x121d4 0x125d4 0x129d4 0x12dd4 0x131d4 0 gfp_interrupt 0x0000 rx gfp: interruption for mac0-7 1: interrupt for all gfp alarms for each mac 0: no interrupt 0x1eb06 0x119d6 0x11dd6 0x121d6 0x125d6 0x129d6 0x12dd6 0x131d6 0 gfpcid_interrupt 0x0000 rx gfp: cid interruption for mac0-7 1: interrupt for all cid alarms for each mac 0: no interrupt table 58: decapsulation block - latched alarms (rr) address bit hw symbol init description - 259 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers the following performance counters can be accessed in saturating mode or roll-over mode, depending on the state of the ccrov control bit. in saturating mode, counters do not count past their terminal count and are cleared to zero when read. in roll-over mode, counters roll-over to zero after reaching their terminal count, and are not cleared when read. 0x1eb08 0x119d8 0x11dd8 0x121d8 0x125d8 0x129d8 0x12dd8 0x131d8 0 ppp_interrupt 0x0000 rx ppp: interruption for mac0-7 1: interrupt for all ppp alarms for each mac 0: no interrupt 0x1eb0a 0x119da 0x11dda 0x121da 0x125da 0x129da 0x12dda 0x131da 0 ctlrx_interrupt 0x0000 rx laps/lapf/gfp/ppp: control frame interruption for mac0-7 1: interrupt for all control frames to the host for each mac 0: no interrupt 0x1eb0c 0 rxlapf_interrupt 0x0000 rx lapf: global interruption 1: interrupt for all lapf alarms for all macs 0: no interrupt 0x1eb0e 0 rxlaps_interrupt 0x0000 rx laps: global interruption 1: interrupt for all laps alarms for all macs 0: no interrupt 0x1eb10 0 rxgfp_interrupt 0x0000 rx gfp: global interruption 1: interrupt for all gfp alarms for all macs 0: no interrupt 0x1eb12 0 rxgfpcid_interrupt 0x0000 rx gfp: global cid interruption 1: interrupt for all cid alarms for all macs 0: no interrupt 0x1eb14 0 rxppp_interrupt 0x0000 rx ppp: global interruption 1: interrupt for all ppp alarms for all macs 0: no interrupt 0x1eb16 0 rctlrx_interrupt 0x0000 rx laps/lapf/gfp/ppp: global host frame interruption 1: interrupt for all frames to the host for all macs 0: no interrupt 0x1eb18 0 count_interrupt 0x0000 rx global latched count status bit interruption 0x1eb1a 0 decap_100m_interrupt 0x0000 rx decapsulation interruption 1: interrupt for all decapsulation blocks 0: no interrupt 0x1eb1c 0 decap_global_interrupt 0x0000 rx global decapsulation masked interruption 1: interrupt after mask for all decapsulation blocks 0: no interrupt table 60: decapsulation block - performance counters address bit hw symbol init description 0x1e800 0x11880 0x11c80 0x12080 0x12480 0x12880 0x12c80 0x13080 15-0 rpcrmaxerx 0x0000 rx lapf/laps/gfp/ppp: payload max length violation counter for mac0-7 table 59: decapsulation block - interrupts (ro) address bit hw symbol init description - 260 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1e802 0x11882 0x11c82 0x12082 0x12482 0x12882 0x12c82 0x13082 15-0 rpcrminerx 0x0000 rx lapf/laps/ppp: payload min length violation counter for mac0-7 0x1e804 0x11884 0x11c84 0x12084 0x12484 0x12884 0x12c84 0x13084 15-0 rpcrfcserx 0x0000 rx lapf/laps/gfp/ppp: fcs error counter for mac0-7 for laps/ppp/lapf, this register counts all laps/ppp/lapf frames received (including control frames destined for the host) with a fcs error. for gfp, this register counts all gfp frames received (not including control frames destined for the host) with a fcs error (when payload fcs check is enabled). 0x1e806 0x11886 0x11c86 0x12086 0x12486 0x12886 0x12c86 0x13086 15-0 rpcrframex_lsb 0x0000 rx lapf/laps/gfp/ppp: frame payloads counter for mac0-7 - lsb this counter does not include the frame count of received laps/gfp/lapf/ppp control frames that are destined for the host. 0x1e808 0x11888 0x11c88 0x12088 0x12488 0x12888 0x12c88 0x13088 15-0 rpcrframex_msb 0x0000 rx lapf/laps/gfp/ppp: frame payloads counter for mac0-7 - msb this counter does not include the frame count of received laps/gfp/lapf/ppp control frames that are destined for the host. 0x1e80a 0x1188a 0x11c8a 0x1208a 0x1248a 0x1288a 0x12c8a 0x1308a 15-0 rpcrbytex_lsb 0x0000 rx lapf/laps/gfp/ppp: payload byte counter for mac0-7 - lsb counts all bytes sent from the decapsulation block to the mac to be transmitted out the ethernet port (does not include any encapsulation frame header bytes). this counter does not include the byte count of received laps/gfp/lapf/ppp control frames that are destined for the host. 0x1e80c 0x1188c 0x11c8c 0x1208c 0x1248c 0x1288c 0x12c8c 0x1308c 15-0 rpcrbytex_msb 0x0000 rx lapf/laps/gfp/ppp: payload byte counter for mac0-7 - msb counts all bytes sent from the decapsulation block to the mac to be transmitted out the ethernet port (does not include any encapsulation frame header bytes). this counter does not include the byte count of received laps/gfp/lapf/ppp control frames that are destined for the host. 0x1e80e 0x1188e 0x11c8e 0x1208e 0x1248e 0x1288e 0x12c8e 0x1308e 15-0 rpcrlspppadderx 0x0000 rx laps/ppp: address field mismatch counter for mac0-7 table 60: decapsulation block - performance counters address bit hw symbol init description - 261 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1e810 0x11890 0x11c90 0x12090 0x12490 0x12890 0x12c90 0x13090 15-0 rpcrlspppcnterx 0x0000 rx laps/ppp: control field mismatch counter for mac0-7 0x1e812 0x11892 0x11c92 0x12092 0x12492 0x12892 0x12c92 0x13092 15-0 rpcrlspppdstuferx 0x0000 rx laps/ppp: byte de-stuffing violations counter for mac0-7 this counter includes all received laps/ppp control frames detected with byte de-stuffing violations. 0x1e814 0x11894 0x11c94 0x12094 0x12494 0x12894 0x12c94 0x13094 15-0 rpcrlfabtdx 0x0000 rx lapf: aborted frame counter for mac0-7 0x1e816 0x11896 0x11c96 0x12096 0x12496 0x12896 0x12c96 0x13096 15-0 rpcrlfadderx 0x0000 rx lapf: address field mismatch counter for mac0-7 0x1e818 0x11898 0x11c98 0x12098 0x12498 0x12898 0x12c98 0x13098 15-0 rpcrlfbadx 0x0000 rx lapf: invalid frame counter for mac0-7 this counter includes all received lapf lmi frames detected as invalid. 0x1e81a 0x1189a 0x11c9a 0x1209a 0x1249a 0x1289a 0x12c9a 0x1309a 15-0 rpcrlfcnterx 0x0000 rx lapf: control field mismatch counter for mac0-7 0x1e81c 0x1189c 0x11c9c 0x1209c 0x1249c 0x1289c 0x12c9c 0x1309c 15-0 rpcrlfdlcierx 0x0000 rx lapf: dlci field mismatch counter for mac0-7 table 60: decapsulation block - performance counters address bit hw symbol init description - 262 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1e81e 0x1189e 0x11c9e 0x1209e 0x1249e 0x1289e 0x12c9e 0x1309e 15-0 rpcrlfdstuferx 0x0000 rx lapf: bit de-stuffing violations counter for mac0-7 this counter includes all received lapf lmi frames detected with bit de-stuffing violations. 0x1e820 0x118a0 0x11ca0 0x120a0 0x124a0 0x128a0 0x12ca0 0x130a0 15-0 rpcrlfflagerx 0x0000 rx lapf: flag error counter for mac0-7 this counter includes all received lapf lmi frames detected with flag errors. 0x1e822 0x118a2 0x11ca2 0x120a2 0x124a2 0x128a2 0x12ca2 0x130a2 15-0 rpcrlflmix 0x0000 rx lapf: lmi frame counter for mac0-7 0x1e824 0x118a4 0x11ca4 0x120a4 0x124a4 0x128a4 0x12ca4 0x130a4 15-0 rpcrlfnlpiderx 0x0000 rx lapf: nlpid field mismatch counter for mac0-7 0x1e826 0x118a6 0x11ca6 0x120a6 0x124a6 0x128a6 0x12ca6 0x130a6 15-0 rpcrlfouierx 0x0000 rx lapf: oui field mismatch counter for mac0-7 0x1e828 0x118a8 0x11ca8 0x120a8 0x124a8 0x128a8 0x12ca8 0x130a8 15-0 rpcrlfpiderx 0x0000 rx lapf: pid field mismatch counter for mac0-7 0x1e82a 0x118aa 0x11caa 0x120aa 0x124aa 0x128aa 0x12caa 0x130aa 15-0 rpcrlpsabtdx 0x0000 rx laps: aborted frame counter for mac0-7 table 60: decapsulation block - performance counters address bit hw symbol init description - 263 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1e82c 0x118ac 0x11cac 0x120ac 0x124ac 0x128ac 0x12cac 0x130ac 15-0 rpcrlpsbadx 0x0000 rx laps: invalid frame counter for mac0-7 this counter includes all received laps control frames detected as invalid. 0x1e82e 0x118ae 0x11cae 0x120ae 0x124ae 0x128ae 0x12cae 0x130ae 15-0 rpcrlpsflagerx 0x0000 rx laps: flag error counter for mac0-7 this counter includes all received laps control frames detected with flag errors. 0x1e830 0x118b0 0x11cb0 0x120b0 0x124b0 0x128b0 0x12cb0 0x130b0 15-0 rpcrlpssapierx 0x0000 rx laps: sapi field mismatch counter for mac0-7 0x1e832 0x118b2 0x11cb2 0x120b2 0x124b2 0x128b2 0x12cb2 0x130b2 15-0 rpcrlpshostx 0x0000 rx laps: laps control frame payload counter for mac0-7 0x1e834 0x118b4 0x11cb4 0x120b4 0x124b4 0x128b4 0x12cb4 0x130b4 15-0 rpcrpausex 0x0000 rx decapsulation: receive pause frame counter for mac0-7 in the sonet/sdh-to-ethernet direction, this register counts the number of pause frames received destined for the mac0-7 (after the decapsulation pro- cess). 0x1e836 0x118b6 0x11cb6 0x120b6 0x124b6 0x128b6 0x12cb6 0x130b6 15-0 rpcrgfpchecerx 0x0000 rx gfp: chec error counter for mac0-7 counts the number of gfp frames received that are detected with a single-bit error within the core header (i.e., chec field) only. 0x1e838 0x118b8 0x11cb8 0x120b8 0x124b8 0x128b8 0x12cb8 0x130b8 15-0 rpcrgfpciderx 0x0000 rx gfp: cid mismatch counter for mac0-7 counts the number of gfp frames received that are detected with a cid mis- match/unsupported value in the cid field only. table 60: decapsulation block - performance counters address bit hw symbol init description - 264 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1e83a 0x118ba 0x11cba 0x120ba 0x124ba 0x128ba 0x12cba 0x130ba 15-0 rpcrgfpdatax_lsb 0x0000 rx gfp: gfp client data frame counter for mac0-7 - lsb counts the number of gfp client data frames received that are detected with a valid/supported gfp client data frame type. 0x1e83c 0x118bc 0x11cbc 0x120bc 0x124bc 0x128bc 0x12cbc 0x130bc 15-0 rpcrgfpdatax_msb 0x0000 rx gfp: gfp client data frame counter for mac0-7 - msb counts the number of gfp client data frames received that are detected with a valid/supported gfp client data frame type. 0x1e83e 0x118be 0x11cbe 0x120be 0x124be 0x128be 0x12cbe 0x130be 15-0 rpcrgfpehecerx 0x0000 rx gfp: ehec single-bit error counter for mac0-7 counts the number of gfp frames received that are detected with a single-bit error within the extension header (i.e., ehec field) only. 0x1e840 0x118c0 0x11cc0 0x120c0 0x124c0 0x128c0 0x12cc0 0x130c0 15-0 rpcrgfpehecmerx 0x0000 rx gfp: ehec multi-bit error counter for mac0-7 counts the number of gfp frames received that are detected with multi-bit errors within the extension header (i.e., ehec field) only. 0x1e842 0x118c2 0x11cc2 0x120c2 0x124c2 0x128c2 0x12cc2 0x130c2 15-0 rpcrgfpexierx 0x0000 rx gfp: gfp exi field mismatch counter for mac0-7 counts all gfp frames received that are detected with a mismatch on the exi field contents (i.e., value of exi is not equal to null or linear). 0x1e844 0x118c4 0x11cc4 0x120c4 0x124c4 0x128c4 0x12cc4 0x130c4 15-0 rpcrgfpidlerx 0x0000 rx gfp: gfp idle frame error counter for mac0-7 counts all gfp idle frames received that are detected with an error. 0x1e846 0x118c6 0x11cc6 0x120c6 0x124c6 0x128c6 0x12cc6 0x130c6 15-0 rpcrgfpmgtx 0x0000 rx gfp: gfp client management frame counter for mac0-7 counts the number of gfp client management frames received that are detected with a valid/supported gfp client management frame type (i.e., presently only csf indication type is supported). table 60: decapsulation block - performance counters address bit hw symbol init description - 265 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1e848 0x118c8 0x11cc8 0x120c8 0x124c8 0x128c8 0x12cc8 0x130c8 15-0 rpcrgfpptierx 0x0000 rx gfp: gfp pti field mismatch counter for mac0-7 counts all gfp frames received that are detected with a mismatch on the pti field contents (i.e., value of pti is not equal to client data or management frame). 0x1e84a 0x118ca 0x11cca 0x120ca 0x124ca 0x128ca 0x12cca 0x130ca 15-0 rpcrgfpthecerx 0x0000 rx gfp: thec single-bit error counter for mac0-7 counts the number of gfp frames received (not destined for the host, i.e., gfp client management frames) that are detected with a single-bit error within the type header (i.e., thec field) only. 0x1e84c 0x118cc 0x11ccc 0x120cc 0x124cc 0x128cc 0x12ccc 0x130cc 15-0 rpcrgfpthecmerx 0x0000 rx gfp: thec multi-bit error counter for mac0-7 counts the number of gfp frames received (not destined for the host, i.e., gfp client management frames) that are detected with multi-bit errors within the type header (i.e., thec field) only. 0x1e84e 0x118ce 0x11cce 0x120ce 0x124ce 0x128ce 0x12cce 0x130ce 15-0 rpcrgfpupierx 0x0000 rx gfp: gfp upi field mismatch counter for mac0-7 counts all gfp frames received that are detected with a mismatch on the upi field contents (value of upi field is not equal to rrpmacfdx register). 0x1e850 0x118d0 0x11cd0 0x120d0 0x124d0 0x128d0 0x12cd0 0x130d0 15-0 rpcrpppflagerx 0x0000 rx ppp: flag error counter for mac0-7 this counter includes all received ppp lcp/ncp-bcp frames detected with flag errors. 0x1e852 0x118d2 0x11cd2 0x120d2 0x124d2 0x128d2 0x12cd2 0x130d2 15-0 rpcrpppproterx 0x0000 rx ppp: protocol field mismatch counter for mac0-7 0x1e854 0x118d4 0x11cd4 0x120d4 0x124d4 0x128d4 0x12cd4 0x130d4 15-0 rpcrpppmactyperx 0x0000 rx ppp: bcp type field mismatch counter for mac0-7 table 60: decapsulation block - performance counters address bit hw symbol init description - 266 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1e856 0x118d6 0x11cd6 0x120d6 0x124d6 0x128d6 0x12cd6 0x130d6 15-0 rpcrppplcpx 0x0000 rx ppp: lcp frame counter for mac0-7 0x1e858 0x118d8 0x11cd8 0x120d8 0x124d8 0x128d8 0x12cd8 0x130d8 15-0 rpcrpppncpx 0x0000 rx ppp: ncp-lcp frame counter for mac0-7 0x1e85a 0x118da 0x11cda 0x120da 0x124da 0x128da 0x12cda 0x130da 15-0 rpcrpppbadx 0x0000 rx ppp: invalid frame counter for mac0-7 this counter includes all received ppp lcp/ncp-bcp frames detected as invalid. 0x1e85c 0x118dc 0x11cdc 0x120dc 0x124dc 0x128dc 0x12cdc 0x130dc 15-0 rpcrpppabtdx 0x0000 rx ppp: aborted frame counter for mac0-7 table 61: decapsulation block - status (rr) address bit hw symbol init description 0x1eb80 0x119e0 0x11de0 0x121e0 0x125e0 0x129e0 0x12de0 0x131e0 0 srmaxerx 0x0000 rx lapf/laps/gfp/ppp: status for payload max length violation counter for mac0-7 1 srminerx rx lapf/laps/ppp: status for payload min length violation counter for mac0-7 2 srfcserx rx lapf/laps/gfp/ppp: status for fcs error counter for mac0-7 3 srlspppadderx rx laps/ppp: status for address field mismatch counter for mac0-7 4 srlspppcnterx rx laps/ppp: status for control field mismatch counter for mac0-7 5 srlspppdstuferx rx laps/ppp: status for byte destuffing violations counter for mac0-7 0x1eb82 0x119e2 0x11de2 0x121e2 0x125e2 0x129e2 0x12de2 0x131e2 0 srlpsabtdx 0x0000 rx laps: status for aborted frame counter for mac0-7 1 srlpsbadx rx laps: status for invalid frame counter for mac0-7 2 srlpsflagerx rx laps: status for flag error counter for mac0-7 3 srlpssapierx rx laps: status for sapi field mismatch counter for mac0-7 4 srlpshostx rx laps: status for laps control frame counter for mac0-7 table 60: decapsulation block - performance counters address bit hw symbol init description - 267 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1eb84 0x119e4 0x11de4 0x121e4 0x125e4 0x129e4 0x12de4 0x131e4 0 srlfabtdx 0x0000 rx lapf: status for aborted frame counter for mac0-7 1 srlfadderx rx lapf: status for address field mismatch counter for mac0-7 2 srlfbadx rx lapf: status for invalid frame counter for mac0-7 3 srlfcnterx rx lapf: status for control field mismatch counter for mac0-7 4 srlfdlcierx rx lapf: status for dlci field mismatch counter for mac0-7 5 srlfdstuferx rx lapf: status for bit destuffing violations counter for mac0-7 6 srlfflagerx rx lapf: status for flag error counter for mac0-7 7 srlflmix rx lapf: status for lmi frame counter for mac0-7 8 srlfnlpiderx rx lapf: status for nlpid field mismatch counter for mac0-7 9 srlfouierx rx lapf: status for oui field mismatch counter for mac0-7 10 srlfpiderx rx lapf: status for pid field mismatch counter for mac0-7 0x1eb86 0x119e6 0x11de6 0x121e6 0x125e6 0x129e6 0x12de6 0x131e6 0 srgfpchecerx 0x0000 rx gfp: status for chec single bit error counter for mac0-7 1 srgfpciderx rx gfp: status for cid mismatch counter for mac0-7 2 srgfpehecerx rx gfp: status for ehec single bit error counter for mac0-7 3 srgfpehecmerx rx gfp: status for ehec multibit error counter for mac0-7 4 srgfpexierx rx gfp: status for exi mismatch counter for mac0-7 5 srgfpidlerx rx gfp: status for idle frame error counter for mac0-7 6 srgfpmgtx rx gfp: status for valid client management frame counter for mac0-7 7 srgfpptierx rx gfp: status for pti mismatch counter for mac0-7 8 srgfpthecerx rx gfp: status for thec single bit error counter for mac0-7 9 srgfpthecmerx rx gfp: status for thec multi-bit error counter for mac0-7 10 srgfpupierx rx gfp: status for upi mismatch counter for mac0-7 0x1eb88 0x119e8 0x11de8 0x121e8 0x125e8 0x129e8 0x12de8 0x131e8 0 srpppflagerx 0x0000 rx ppp: flag error status for mac0-7 1 srpppproterx rx ppp: protocol field mismatch status for mac0-7 2 srpppmactyperx rx ppp: bcp mac type field mismatch status for mac0-7 3 srppplcpx rx ppp: lcp frame status for mac0-7 4 srpppncpx rx ppp: ncp-lcp frame status for mac0-7 5 srpppbadx rx ppp: invalid frame status for mac0-7 6 srpppabtdx rx ppp: abort frame status for mac0-7 0x1eb8a 0x119ea 0x11dea 0x121ea 0x125ea 0x129ea 0x12dea 0x131ea 0 macx_laps_status_lvl3 0x0000 rx laps: merge all the laps performance status for mac0-7 1 macx_lapf_status_lvl3 rx lapf: merge all the lapf performance status for mac0-7 2 macx_ppp_status_lvl3 rx ppp: merge all the ppp performance status for mac0-7 3 macx_gfp_status_lvl3 rx gfp: merge all the gfp performance status for mac0-7 4 macx_cmnperf_status_lvl3 rx: merge all the common performance status for mac0-7 5 sholdropovfx rx: status for dropped frame in case of overflow for channel x 6 srpausex rx: status for total number of receive pause frame for channel x 0x1eb8c 7-0 mac0-7_perfcnt_status_lvl2 0x0000 rx: merge all the level 2 performance status for mac0-7 table 61: decapsulation block - status (rr) address bit hw symbol init description - 268 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers sdram control registers table 62 - sdram control and sdram interface configuration table 62: sdram control - general configuration (rw) address bit hw symbol init description 0x1d600 0 sdraminit 0x00b8 sdram initialization start bit 0: no action 1: restart the initialization of the sdram. must be cleared at the end of the initialization. 2-1 sdram_cfg sdram configuration 8mb/16mb/32mb 00: 8mb 01: 16 mb 10: 32 mb 11: reserved 5-3 sdram_trfc sdram ctrl: trfc timing, auto refresh period range 0 to 7 (unit = number of periods at 10 ns +1) default value = 7 (means 8 periods at 10 ns) 7-6 sdram_trp sdram ctrl: trp timing. precharge command period range 0 to 3 (unit = number of periods at 10 ns +1). this control bit must be left at the default value = 2 (means 3 periods at 10 ns). 0x1d602 10-0 mbr_value 0x0031 sdram ctrl: mode register default value. default must be 0 and 000 and 011 and 0 and 001 which means cas latency 3, burst length = 2 and sequential burst access. 0x1d604 15-0 sdrarp 0x009b sdram ctrl: sdram auto refresh period in 8 sysclk period. default is 155 (24 s/row). must be set to 78 (decimal) for 12 s/row. 0x1d606 7-0 sdrinit_ar_mbr 0x0008 sdram ctrl: number of auto-refresh cycle performed during initialization. default value = 8. note: a configured value of 'n' will provide 'n+1' auto refresh cycles during the initialization period. 0x1d608 15-0 sdrtinit 0x0064 sdram ctrl: power up initialization delay in unit of 200 cycles of clock to the sdram i.e., in unit of 100 cycles of sysclk. default is 100. 0x1d60a 15-0 ramc_mb_windows_etrc 0x0007 sdram ctrl: sdram arbitration windows for ethernet input client. this register must be written with 0x0009 for gmii mode. the default value of 0x0007 is used for smii mode. 0x1d60c 15-0 ramc_mb_windows_shtc 0x0003 sdram ctrl: sdram arbitration windows for sonet transmit client. this register must be written with 0x0001 for gmii mode. the default value of 0x0003 is used for smii mode. 0x1d60e 15-0 ramc_mb_windows_ettc 0x0001 sdram ctrl: sdram arbitration windows for ethernet output client. 0x1d610 15-0 ramc_mb_windows_shrc 0x0001 sdram ctrl: sdram arbitration windows for sonet receive client. this register must be written with 0x0002 for sts-3c/vc-4 mode or gmii mode. the default value of 0x0001 is used for all other modes. 0x1d612 15-0 ramc_mb_windows_dfrc 0x0001 sdram ctrl: sdram arbitration windows for hol input client. 0x1d614 15-0 ramc_mb_windows_dftc 0x0002 sdram ctrl: sdram arbitration windows for hol output client. this register must be written with 0x0001 for gmii mode. the default value of 0x0002 is used for smii mode. note: follow procedure defined in ? configuration changes/initialization ? on page 184 to change any register in table 62 . - 269 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 63 and 64 - microprocessor access to the sdram (indirect access) table 63: sdram - access control registers (rw) address bit hw symbol init description 0x1d630 15-0 up_addr2rdlsb 0x0000 sdram ctrl: lsb address for microprocessor rd access to the sdram 0x1d632 6-0 up_addr2rdmsb 0x0000 sdram ctrl: msb address for microprocessor rd access to the sdram 0x1d634 15-0 up_addr2wrlsb 0x0000 sdram ctrl: lsb address for microprocessor wr access to the sdram 0x1d636 6-0 up_addr2wrmsb 0x0000 sdram ctrl: msb address for microprocessor wr access to the sdram 0x1d638 15-0 up_data2wrlsb 0x0000 sdram ctrl: lsb data from the microprocessor to be written to sdram 0x1d63a 15-0 up_data2wrmsb 0x0000 sdram ctrl: msb data from the microprocessor to be written to sdram 0x1d63c 0 up_wraddr2rd 0x0000 sdram ctrl: read address field is ready 0x1d63e 0 up_wraddr2wr 0x0000 sdram ctrl: write address field is ready table 64: sdram - access results registers (ro) address bit hw symbol init description 0x1d620 15-0 up_datardlsb 0x0000 sdram ctrl: lsb read data by microprocessor access to the sdram 0x1d622 15-0 up_datardmsb 0x0000 sdram ctrl: msb read data by microprocessor access to the sdram - 270 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tx virtual concatenation registers tables 65 through 75 - configuration, status and alarms of the transmit (ethernet to sonet) virtual concatenation block table 65: tx virtual concatenation block - general configuration (rw) address bit hw symbol init description 0x1ec80 0 csntsdh 0x0000 tx vcat: sonet/sdh configuration 0: sonet (default) 1: sdh 0x1ec82 1-0 cthovc3_3 0x0000 tx vcat: sts-1/vc-3 #3 configuration csntsdh = ? 0 ? 00: sts-1/tug-3 #3 is used in low order to carry selected vt1.5/vc-11 01: au-3 c is used to carry vt1.5/vc-11 10: reserved 11: sts-1/tug-3 #3 (with its sts-1spe / vc-3) is used in high order csntsdh = ? 1 ? 00: sts-1/tug-3 #3 is used in low order to carry vt-2/vc-12 01: au-3 c is used to carry vt-2/vc-12 10: reserved 11: sts-1/tug-3 #3 (with its tu-3/vc-3) is used in high order 3-2 cthovc3_2 tx vcat: sts-1/vc-3 #2 configuration csntsdh = ? 0 ? 00: sts-1/tug-3 #2 is used in low order to carry selected vt1.5/vc-11 01: au-3 b is used to carry vt1.5/vc-11 10: reserved 11: sts-1/tug-3 #2 (with its sts-1spe / vc-3) is used in high order csntsdh = ? 1 ? 00: sts-1/tug-3 #2 is used in low order to carry vt-2/vc-12 01: au-3 b is used to carry vt-2/vc-12 10: reserved 11: sts-1/tug-3 #2 (with its tu-3/vc-3) is used in high order 5-4 cthovc3_1 tx vcat: sts-1/vc-3 #1 configuration csntsdh = ? 0 ? 00: sts-1/tug-3 #1 is used in low order to carry selected vt1.5/vc-11 01: au-3 a is used to carry vt1.5/vc-11 10: reserved 11: sts-1/tug-3 #1 (with its sts-1spe / vc-3) is used in high order csntsdh = ? 1 ? 00: sts-1/tug-3 #1 is used in low order to carry vt-2/vc-12 01: au-3 a is used to carry vt-2/vc-12 10: reserved 11: sts-1/tug-3 #1 (with its tu-3/vc-3) is used in high order 6 cthovc4 tx vcat: vc-4/sts-3c configuration 0: configured for non vc-4/sts-3c mode (i.e., when using sub-structured contain- ers/tributaries) 1: configured for vc-4/sts-3c mode 0x1ec84 7-0 ctvc4mac 0x0000 tx vcat: 10/100 port to be mapped into vc-4/sts3c bit mapped register to indicate the mac associated to the vc-4/sts-3c in case of configuration in vc-4/sts-3c. bit 0 is associated to port 1 bit 7 is associated to port 8 only a single bit of this register may be set to 1. - 271 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1ec86 ? 0x1ec94 1-0 ctvcg_x 0x0000 tx vcat: configuration for vcg0-7 00: vcg used in itu/ansi low order virtual concatenation 01: vcg used in non standard itu/ansi low order virtual concatenation and in non lcas 10: reserved 11: vcg used in itu/ansi high order virtual concatenation 2 ctlcas_x tx vcat: lcas configuration for vcg0-7 0: vcg in non lcas mode 1: vcg in lcas mode 9-3 ctmst_vt_x tx vcat: lcas tributary selection configuration for vcg0-7. number of tributary which carries the mst and rs_ack per vcg. for non-lcas, set bits 9,8 to 0b11. note: if the vcg is not used, set bits 9-8 to 0b11. 0x1ec96 7-0 ctfcrstx 0x00ff tx vcat: frame count reset for vcg0-7 0: in low order, frame count is increasing normally / in high order mfi1/mfi2 are increasing normally 1: frame count (low order) or mfi2 set to 0. mfi1 is not affected. 0x1ec98 7-0 ctvcg_srstx 0x0000 tx vcat: lcas vcg0-7 soft reset (only used in lcas mode). when set to 1, the lcas state machine corresponding to the vcg is reset. if any members are assigned to the corresponding vcg, they must be configured back to the global pool before releasing the reset. the member control bits are ctlopool_x and cthopool_x. 0x1ec9a 1-0 cinrt_grptx20m 0x0001 alarm latching configuration for tables 47 and 69 criteria used to create latched alarms from the raw (unlatched) alarms. 00: positive level 01: rising edge (default) 10: falling edge 11: rising or falling edge table 65: tx virtual concatenation block - general configuration (rw) address bit hw symbol init description bits assignment 9-8 au-3 7-5 tug-2 4-3 tu-1 - 272 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 66: tx virtual concatenation block - lcas alarms (ro) address bit hw symbol init description 0x1ed00 ? 0x1eda6 0 atlcprd1_x 0x0000 lo: tx lcas add period1 alarm for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: alarm on expiry of timeout counter. 0: no alarm see table 67 for per vt/vc address offsets. 1 atlcasadded_x lo: tx lcas add successful alarm for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: when the member has been added and its state machine goes to norm state 0: no alarm see table 67 for per vt/vc address offsets. 2 atlcasrem_x lo: tx lcas remove successful alarm for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: when the member has been removed and its state machine goes from norm to idle state. 0: no alarm see table 67 for per vt/vc address offsets. 3 atlcasdnu_x lo: tx lcas dnu alarm for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: when mst = fail for the member while in norm/eos state. 0: no alarm see table 67 for per vt/vc address offsets. 4 atlcasdnuok_x lo: tx lcas dnu ok alarm for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: when mst = ok to change member from dnu to norm/eos state. 0: no alarm see table 67 for per vt/vc address offsets. 0x1eda8 ? 0x1edac 0 atlcprd1_x 0x0000 ho: tx lcas add period1 alarm for the sts-1/vc-3 1_3 1: alarm on expiry of timeout counter. 0: no alarm 1 atlcasadded_x ho: tx lcas add successful alarm for the sts-1/vc-3 1_3 1: when the member has been added and its state machine goes to norm state 0: no alarm 2 atlcasrem_x ho: tx lcas re move successful alarm for the sts-1/vc-3 1_3 1: when the member has been removed and its state machine goes from norm to idle state. 0: no alarm 3 atlcasdnu_x ho: tx lcas dnu alarm for the sts-1/vc-3 1_3 1: when mst = fail for the member while in norm/eos state. 0: no alarm 4 atlcasdnuok_x ho: tx lcas dnu ok successful alarm for the sts-1/vc-3 1_3 1: when mst = ok to change member from dnu to norm/eos state. 0: no alarm 0x1edae 7-0 atloprd2_x 0x0000 tx lcas add period2 alarm for the vcg 0_7 1: alarm on expiry of timeout counter. 0: no alarm 0x1edb0 7-0 athoprd2_x 0x0000 tx lcas add period2 alarm for the vcg 0_7 1: alarm on expiry of timeout counter. 0: no alarm 0x1edb2 7-0 atloprd3_x 0x0000 tx lo remove period3 alarm for the vcg 0_7 1: alarm on expiry of timeout counter. 0: no alarm 0x1edb4 7-0 athoprd3_x 0x0000 tx ho remove period3 alarm for the vcg0-7 1: alarm on expiry of timeout counter. 0: no alarm - 273 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 67: vt/vc address offsets au-3 # tug-2 # tu-1 # vt/vc # (vt1.5/vc-11) vt/vc # (vt2/vc-12) address offset (hex) 111 0 0 00 112 1 1 02 113 2 2 04 114 3not used 06 121 4 3 08 122 5 4 0a 123 6 5 0c 124 7not used 0e 131 8 6 10 132 9 7 12 133 10 8 14 1 3 4 11 not used 16 141 12 9 18 1 4 2 13 10 1a 1 4 3 14 11 1c 1 4 4 15 not used 1e 1 5 1 16 12 20 1 5 2 17 13 22 1 5 3 18 14 24 1 5 4 19 not used 26 1 6 1 20 15 28 1 6 2 21 16 2a 1 6 3 22 17 2c 1 6 4 23 not used 2e 1 7 1 24 18 30 1 7 2 25 19 32 1 7 3 26 20 34 1 7 4 27 not used 36 2 1 1 28 21 38 2 1 2 29 22 3a 2 1 3 30 23 3c 2 1 4 31 not used 3e 2 2 1 32 24 40 2 2 2 33 25 42 2 2 3 34 26 44 2 2 4 35 not used 46 2 3 1 36 27 48 2 3 2 37 28 4a 2 3 3 38 29 4c 2 3 4 39 not used 4e 2 4 1 40 30 50 2 4 2 41 31 52 2 4 3 42 32 54 2 4 4 43 not used 56 2 5 1 44 33 58 2 5 2 45 34 5a 2 5 3 46 35 5c 2 5 4 47 not used 5e - 274 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 2 6 1 48 36 60 2 6 2 49 37 62 2 6 3 50 38 64 2 6 4 51 not used 66 2 7 1 52 39 68 2 7 2 53 40 6a 2 7 3 54 41 6c 2 7 4 55 not used 6e 3 1 1 56 42 70 3 1 2 57 43 72 3 1 3 58 44 74 3 1 4 59 not used 76 3 2 1 60 45 78 3 2 2 61 46 7a 3 2 3 62 47 7c 3 2 4 63 not used 7e 3 3 1 64 48 80 3 3 2 65 49 82 3 3 3 66 50 84 3 3 4 67 not used 86 3 4 1 68 51 88 3 4 2 69 52 8a 3 4 3 70 53 8c 3 4 4 71 not used 8e 3 5 1 72 54 90 3 5 2 73 55 92 3 5 3 74 56 94 3 5 4 75 not used 96 3 6 1 76 57 98 3 6 2 77 58 9a 3 6 3 78 59 9c 3 6 4 79 not used 9e 3 7 1 80 60 a0 3 7 2 81 61 a2 3 7 3 82 62 a4 3 7 4 83 not used a6 table 67: vt/vc address offsets au-3 # tug-2 # tu-1 # vt/vc # (vt1.5/vc-11) vt/vc # (vt2/vc-12) address offset (hex) - 275 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 68: tx virtual concatenation block - lcas alarm and interrupt masks (rw) address bit hw symbol init description 0x1ef00 ? 0x1efa6 0 matlcprd1_x 0x001f lo: tx lcas add period1 alarm mask for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: alarm is masked (default) 0: alarm is not masked see table 67 for per vt/vc address offsets. 1 matlcasadded_x lo: tx lcas add successful alarm mask for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: alarm is masked (default) 0: alarm is not masked see table 67 for per vt/vc address offsets. 2 matlcasrem_x lo: tx lcas remove successful alarm mask for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: alarm is masked (default) 0: alarm is not masked see table 67 for per vt/vc address offsets. 3 matlcasdnu_x lo: tx lcas dnu alarm mask for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: alarm is masked (default) 0: alarm is not masked see table 67 for per vt/vc address offsets. 4 matlcasdnuok_x lo: tx lcas dnu ok alarm mask for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: alarm is masked (default) 0: alarm is not masked see table 67 for per vt/vc address offsets. 0x1efa8 ? 0x1efac 0 matlcprd1_x 0x001f ho: tx lcas add period1 alarm mask for the sts-1/vc-3 1_3 1: alarm is masked (default) 0: alarm is not masked 1 matlcasadded_x ho: tx lcas add successful alarm mask for the sts-1/vc-3 1_3 1: alarm is masked (default) 0: alarm is not masked 2 matlcasrem_x ho: tx lcas remove successful alarm mask for the sts-1/vc-3 1_3 1: alarm is masked (default) 0: alarm is not masked 3 matlcasdnu_x ho: tx lcas dnu alarm mask for the sts-1/vc-3 1_3 1: alarm is masked (default) 0: alarm is not masked 4 matlcasdnuok_x ho: tx lcas dnu ok alarm mask for the sts-1/vc-3 1_3 1: alarm is masked (default) 0: alarm is not masked 0x1efae 7-0 matloprd2_x 0x00ff tx lo add period2 alarm mask for the vcg0-7 1: alarm is masked (default) 0: alarm is not masked 0x1efb0 7-0 mathoprd2_x 0x00ff tx ho add period2 alarm mask for the vcg0-7 1: alarm is masked (default) 0: alarm is not masked 0x1efb2 7-0 matloprd3_x 0x00ff tx lo remove period3 alarm mask for the vcg0-7 1: alarm is masked (default) 0: alarm is not masked 0x1efb4 7-0 mathoprd3_x 0x00ff tx ho remove period3 alarm mask for the vcg0-7 1: alarm is masked (default) 0: alarm is not masked - 276 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1efb6 0 mavct_loprd1_interrupt 0x001f lo: interrupt mask - tx lcas add period1 alarm 1: interrupt is masked for all tx lcas add period1 alarms (all members) (default) 0: interrupt is not masked 1 mavct_loadded_interrupt lo: interrupt mask - tx lcas add successful alarm 1: interrupt is masked for all tx lcas add alarms (all members) (default) 0: interrupt is not masked 2 mavct_lorem_interrupt lo: interrupt mask - tx lcas remove successful alarm 1: interrupt is masked for all tx lcas remove alarms (all members) (default) 0: interrupt is not masked 3 mavct_lodnu_interrupt lo: interrupt mask -tx lcas dnu alarm 1: interrupt is masked for all tx lcas dnu alarms (all members) (default) 0: interrupt is not masked 4 mavct_lodnuok_interrupt lo: interrupt mask -tx lcas dnu ok alarm 1: interrupt is masked for all tx lcas dnu ok alarms (all members) (default) 0: interrupt is not masked 0x1efb8 0 mavct_hoprd1_interrupt 0x001f ho: interrupt mask -tx lcas add period1 alarm 1: interrupt is masked for all tx lcas add period1 alarms (all members) (default) 0: interrupt is not masked 1 mavct_hoadded_interrupt ho: interrupt mask -tx lcas add successful alarm 1: interrupt is masked for all tx lcas add alarms (all members) (default) 0: interrupt is not masked 2 mavct_horem_interrupt ho: interrupt mask -tx lcas remove successful alarm 1: interrupt is masked for all tx lcas remove alarms (all members) (default) 0: interrupt is not masked 3 mavct_hodnu_interrupt ho: interrupt mask -tx lcas dnu alarm 1: interrupt is masked for all tx lcas dnu alarm (all members) (default) 0: interrupt is not masked 4 mavct_hodnuok_interrupt ho: interrupt mask -tx lcas dnu ok alarm 1: interrupt is masked for all tx lcas dnu ok alarm (all members) (default) 0: interrupt is not masked table 68: tx virtual concatenation block - lcas alarm and interrupt masks (rw) address bit hw symbol init description - 277 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 69: tx virtual concatenation block - lcas latched alarms (rr) address bit hw symbol init description 0x1ee00 ? 0x1eea6 0 l1atlcprd1_x 0x0000 lo: tx lcas add period1 latched alarm for the sts-1/vc-3 1_3, tug-2 1_7 and tu- 1 1_4 1: alarm is latched (clear on read) for each member 0: no alarm is latched see table 67 for per vt/vc address offsets. 1 l1atlcasadded_x lo: tx lcas add successful latched alarm for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: alarm is latched (clear on read) for each member 0: no alarm is latched see table 67 for per vt/vc address offsets. 2 l1atlcasrem_x lo: tx lcas remove successful latched alarm for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: alarm is latched (clear on read) for each member 0: no alarm is latched see table 67 for per vt/vc address offsets. 3 l1atlcasdnu_x lo: tx lcas dnu latched alarm for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: alarm is latched (clear on read) for each member 0: no alarm is latched see table 67 for per vt/vc address offsets. 4 l1atlcasdnuok_x lo: tx lcas dnu ok latched alarm for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: alarm is latched (clear on read) for each member 0: no alarm is latched see table 67 for per vt/vc address offsets. 0x1eea8 ? 0x1eeac 0 l1atlcprd1_x 0x0000 ho: tx lcas add period1 latched alarm for the sts-1/vc-3 1_3 1: alarm is latched (clear on read) for each member 0: no alarm is latched 1 l1atlcasadded_x ho: tx lcas add successful latched alarm for the sts-1/vc-3 1_3 1: alarm is latched (clear on read) for each member 0: no alarm is latched 2 l1atlcasrem_x ho: tx lcas remove successful latched alarm for the sts-1/vc-3 1_3 1: alarm is latched (clear on read) for each member 0: no alarm is latched 3 l1atlcasdnu_x ho: tx lcas dnu latched alarm for the sts-1/vc-3 1_3 1: alarm is latched (clear on read) for each member 0: no alarm is latched 4 l1atlcasdnuok_x ho: tx lcas dnu ok latched alarm for the sts-1/vc-3 1_3 1: alarm is latched (clear on read) for each member 0: no alarm is latched 0x1eeae 7-0 l1atloprd2_x 0x0000 tx lo add period2 latched alarm for the vcg0-7 1: alarm is latched (clear on read) for each member 0: no alarm is latched 0x1eeb0 7-0 l1athoprd2_x 0x0000 tx ho add period2 latched alarm for the vcg0-7 1: alarm is latched (clear on read) for each member 0: no alarm is latched 0x1eeb2 7-0 l1atloprd3_x 0x0000 tx lo remove period3 latched alarm for the vcg0-7 1: alarm is latched (clear on read) for each member 0: no alarm is latched 0x1eeb4 7-0 l1athoprd3_x 0x0000 tx ho remove period3 latched alarm for the vcg0-7 1: alarm is latched (clear on read) for each member 0: no alarm is latched - 278 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 70: tx virtual concatenation block - lcas interrupts (ro) address bit hw symbol init description 0x1ec00 0 vct_loprd1_interrupt 0x0000 lo: tx lcas add period1 alarm interrupt 1: interrupt for all tx lcas add period1 alarm (all members) 0: no interrupt 1 vct_loadded_interrupt lo: tx lcas add successful alarm interrupt 1: interrupt for all tx lcas add successful alarm (all members) 0: no interrupt 2 vct_lorem_interrupt lo: tx lcas remove successful alarm interrupt 1: interrupt for all tx lcas remove successful alarm (all members) 0: no interrupt 3 vct_lodnu_interrupt lo: tx lcas dnu alarm interrupt 1: interrupt for all tx lcas dnu alarm (all members) 0: no interrupt 4 vct_lodnuok_interrupt lo: tx lcas dnu ok alarm interrupt 1: interrupt for all tx lcas dnu ok alarm (all members) 0: no interrupt 5 vct_txlcaslo_interrupt lo: tx lcas alarm interrupt 1: interrupt for all tx lcas alarm (all members) 0: no interrupt 0x1ec02 0 vct_hoprd1_interrupt 0x0000 ho: tx lcas add period1 alarm interrupt 1: interrupt for all tx lcas add period1 alarm (all members) 0: no interrupt 1 vct_hoadded_interrupt ho: tx lcas add successful alarm interrupt 1: interrupt for all tx lcas add successful alarm (all members) 0: no interrupt 2 vct_horem_interrupt ho: tx lcas remove successful alarm interrupt 1: interrupt for all tx lcas remove successful alarm (all members) 0: no interrupt 3 vct_hodnu_interrupt ho: tx lcas dnu alarm interrupt 1: interrupt for all tx lcas dnu alarm (all members) 0: no interrupt 4 vct_hodnuok_interrupt ho: tx lcas dnu ok alarm interrupt 1: interrupt for all tx lcas dnu ok alarm (all members) 0: no interrupt 5 vct_txlcasho_interrupt ho: tx lcas alarm interrupt 1: interrupt for all tx lcas alarm (all members) 0: no interrupt 0x1ec04 0 vct_txloprd2vcg_interrupt 0x0000 tx lo period2 alarm interrupt 1: interrupt for all tx lo period2 alarm (all members) 0: no interrupt 1 vct_txhoprd2vcg_interrupt tx ho period2 alarm interrupt 1: interrupt for all tx ho period2 alarm (all members) 0: no interrupt 0x1ec06 0 vct_txloprd3vcg_interrupt 0x0000 tx lo remove period3 alarm interrupt 1: interrupt for all tx lo remove period3 alarm (all members) 0: no interrupt 1 vct_txhoprd3vcg_interrupt tx ho remove period3 alarm interrupt 1: interrupt for all tx ho remove period3 alarm (all members) 0: no interrupt - 279 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 71: tx virtual concatenation block - low order tributary configuration (rw) address bit hw symbol init description 0x13500 ? 0x135a6 1-0 ctlopool_x 0x07e0 00: this low order tributary is assigned to a global pool of resources. (default) 01: this low order tributary is assigned to a non-lcas pool of resources. 10: this low order tributary is assigned to a lcas idle pool of resources. 11: this low order tributary is assigned to a lcas active pool of resources. see table 67 for per vt/vc address offsets. 4-2 ctlovcg_x 0x07e0 these 3 bits determine the vcg to which the select low order tributary has been assigned. eight vcgs are available. (default = 000). see table 67 for per vt/vc address offsets. 10-5 ctlosq_x 0x07e0 when in low order virtual concatenation, these 6 bits are used to configure/assign a sequence indicator value (i.e., sq field) for the select low order tributary per vcg to be inserted in the extended overhead multiframe. in lcas mode, these bits are configured only by the lcas state machine. in non-lcas mode, these bits are configured only by the host. (default = 111111). see ta b l e 6 7 for per vt/vc address offsets. table 72: tx virtual concatenation block - high order tributary configuration (rw) address bit hw symbol init description 0x13400 ? 0x13404 1-0 cthopool_x 0x1fe0 00: this high order tributary is assigned to a global pool of resource. (default) 01: this high order tributary is assigned to a non-lcas pool of resources. 10: this high order tributary is assigned to a lcas idle pool of resources. 11: this high order tributary is assigned to a lcas active pool of resources. 4-2 cthovcg_x these 3 bits determine the vcg to which the select high order tributary has been assigned. eight vcgs are available. (default=000) 12-5 cthosq_x when in high order virtual concatenation, these 8 bits are used to configure/assign a sequence indicator value (i.e., sq field) for the select high order tributary per vcg to be inserted in the extended overhead multiframe. in lcas mode, these bits are accessed only by the lcas state machine. in non-lcas mode, these bits are accessed only by the host. (default = 11111111) table 73: tx virtual concatenation block - lcas configuration (rw) address bit hw symbol init description 0x18800 ? 0x188a6 0 ctlok4vcen_x 0x0000 tx lo: k4/z7 bit 2 enable in lcas mode for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 see table 74 for per vt/vc address offsets. 1 ctlocrcerr_x tx lo: crc initialization in lcas mode for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4. a zero initializes the register to 0 for normal operation. a one initializes the register to 1 and causes crc errors to be generated. see table 74 for per vt/vc address offsets. 0x188a8 ? 0x188ac 0 cthoh4vcen_x 0x0000 tx ho: h4 byte enable in lcas mode for the sts-1/vc-3 1_3 1 cthocrcerr_x tx ho: crc initialization in lcas mode for the sts-1/vc-3 1_3. a zero initializes the regis- ter to 0 for normal operation. a one initializes the register to 1 and causes crc errors to be generated. 0x18a00 ? 0x18aa6 9-0 ctlolcprd1_x 0x03ff tx lo lcas: terminal count of timeout counter when adding a member for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 (time unit = ms) see table 67 for per vt/vc address offsets. 0x18aa8 ? 0x18aac 9-0 ctholcprd1_x 0x03ff tx ho lcas: terminal count of timeout counter when adding a member for sts-1/vc-3 1_3 (time unit = ms) 0x1d7e0 ? 0x1d7ee 9-0 ctlcprd2_x 0x03ff tx lcas: terminal count of timeout counter used for detection of rs_ack after add for vcg0-7 (time unit = ms) - 280 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1d200 ? 0x1d20e 9-0 ctlcprd3_x 0x03ff tx lcas: terminal count of timeout counter used for detection of rs_ack after rem for vcg0-7 (time unit = ms) table 74: vt/vc address offsets (ctlok4vcen_x and ctlocrcerr_x only) au-3 # tug-2 # tu-1 # vt/vc # (vt1.5/vc-11) vt/vc # (vt2/vc-12) address offset (hex) 111 0 0 00 112 1 1 2a 113 2 2 54 1 1 4 3 not used 7e 121 4 3 06 122 5 4 30 123 6 5 5a 1 2 4 7 not used 84 131 8 6 0c 132 9 7 36 133 10 8 60 1 3 4 11 not used 8a 141 12 9 12 1 4 2 13 10 3c 1 4 3 14 11 66 1 4 4 15 not used 90 1 5 1 16 12 18 1 5 2 17 13 42 1 5 3 18 14 6c 1 5 4 19 not used 96 1 6 1 20 15 1e 1 6 2 21 16 48 1 6 3 22 17 72 1 6 4 23 not used 9c 1 7 1 24 18 24 1 7 2 25 19 4e 1 7 3 26 20 78 1 7 4 27 not used a2 2 1 1 28 21 02 2 1 2 29 22 2c 2 1 3 30 23 56 2 1 4 31 not used 80 2 2 1 32 24 08 2 2 2 33 25 32 2 2 3 34 26 5c 2 2 4 35 not used 86 2 3 1 36 27 0e 2 3 2 37 28 38 2 3 3 38 29 62 2 3 4 39 not used 8c 2 4 1 40 30 14 2 4 2 41 31 3e 2 4 3 42 32 68 2 4 4 43 not used 92 2 5 1 44 33 1a 2 5 2 45 34 44 2 5 3 46 35 6e 2 5 4 47 not used 98 table 73: tx virtual concatenation block - lcas configuration (rw) address bit hw symbol init description - 281 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 2 6 1 48 36 20 2 6 2 49 37 4a 2 6 3 50 38 74 2 6 4 51 not used 9e 2 7 1 52 39 26 2 7 2 53 40 50 2 7 3 54 41 7a 2 7 4 55 not used a4 3 1 1 56 42 04 3 1 2 57 43 2e 3 1 3 58 44 58 3 1 4 59 not used 82 3 2 1 60 45 0a 3 2 2 61 46 34 3 2 3 62 47 5e 3 2 4 63 not used 88 3 3 1 64 48 10 3 3 2 65 49 3a 3 3 3 66 50 64 3 3 4 67 not used 8e 3 4 1 68 51 16 3 4 2 69 52 40 3 4 3 70 53 6a 3 4 4 71 not used 94 3 5 1 72 54 1c 3 5 2 73 55 46 3 5 3 74 56 70 3 5 4 75 not used 9a 3 6 1 76 57 22 3 6 2 77 58 4c 3 6 3 78 59 76 3 6 4 79 not used a0 3 7 1 80 60 28 3 7 2 81 61 52 3 7 3 82 62 7c 3 7 4 83 not used a6 table 74: vt/vc address offsets (ctlok4vcen_x and ctlocrcerr_x only) au-3 # tug-2 # tu-1 # vt/vc # (vt1.5/vc-11) vt/vc # (vt2/vc-12) address offset (hex) - 282 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 75: tx virtual concatenation block - status (ro) address bit hw symbol init description 0x18c00 ? 0x18ca6 1-0 stlopool_x not applicable 00: indicates low order tributary is assigned to the global pool of resources. 01: indicates low order tributary is assigned to the non-lcas pool of resources. 10: indicates low order tributary is assigned to the lcas idle pool of resources. 11: indicates low order tributary is assigned to the lcas active pool of resources. see table 67 for per vt/vc address offsets. 4-2 stlovcg_x when in low order virtual concatenation, indicates to which vcg the low order tributary has been assigned. only eight vcgs are available. see table 67 for per vt/vc address offsets. 8-5 stloctrl_x when in low order virtual concatenation, indicates the status of tributary state (i.e., the ctrl field transmitted) in both lcas and non-lcas modes. see table 67 for per vt/vc address offsets. 14-9 stlosq_x when in low order virtual concatenation, indicates the status of the assigned sequence indicator value for the select low order tributary per vcg. see table 67 for per vt/vc address offsets. 0x18ca8 0x18cac 0x18cb0 7-0 sthosq_x 0x0000 when in high order virtual concatenation, indicates the assigned sequence indica- tor (sq) value for the select high order tributary per vcg. 0x18caa 0x18cae 0x18cb2 1-0 sthopool_x 0x0000 00: indicates high order tributary is assigned to a global pool of resources. 01: indicates high order tributary is assigned to a non-lcas pool of resources. 10: indicates high order tributary is assigned to a lcas idle pool of resources. 11: indicated high order tributary is assigned to a lcas active pool of resources. 4-2 sthovcg_x when in high order virtual concatenation, indicates to which vcg the high order tributary has been assigned. only eight vcgs are available. 8-5 sthoctrl_x when in high order virtual concatenation, indicates the status of tributary state (i.e., the ctrl field transmitted) in both lcas and non-lcas modes. - 283 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers rx virtual concatenation registers tables 76 through 85 - configuration, status and alarm of the receive (sonet to ethernet) virtual concatenation block table 76: rx virtual concatenation block - general configuration registers (rw) address bit hw symbol init description 0x1f000 1-0 cinrt_grprx20m 0x0001 alarm latching configuration for receive lcas alarm group ( table 79 ) criteria used to create latched alarms from the raw (unlatched) alarms. 00: positive level 01: rising edge (default) 10: falling edge 11: rising or falling edge 0x1f002 0 hinten 0x0000 enable of the interrupt signal 0: general interrupt signal is disabled 1: general interrupt is enabled 0x1f004 1-0 crhovc3_3 0x0000 rx vcat: sts-1/vc-3 #3 configuration csntsdh = ? 0 ? 00: sts-1/tug-3 #3 is used in low order to carry selected vt1.5/vc-11 01: au-3 c is used to carry vt1.5/vc-11 10: reserved 11: sts-1/tug-3 #3 (with its sts-1spe / vc-3) is used in high order csntsdh = ? 1 ? 00: sts-1/tug-3 #3 is used in low order to carry vt-2/vc-12 01: au-3 c is used to carry vt2/vc-12 10: reserved 11: sts-1/tug-3 #3 (with its tu-3/vc-3) is used in high order 3-2 crhovc3_2 rx vcat: sts-1/vc-3 #2 configuration csntsdh = ? 0 ? 00: sts-1/tug-3 #2 is used in low order to carry selected vt1.5/vc-11 01: au-3 b is used to carry vt1.5/vc-11 10: reserved 11: sts-1/tug-3 #2 (with its sts-1spe / vc-3) is used in high order csntsdh = ? 1 ? 00: sts-1/tug-3 #2 is used in low order to carry vt-2/vc-12 01: au-3 b is used to carry vt2/vc-12 10: reserved 11: sts-1/tug-3 #2 (with its tu-3/vc-3) is used in high order 5-4 crhovc3_1 rx vcat: sts-1/vc-3 #3 configuration csntsdh = ? 0 ? 00: sts-1/tug-3 #1 is used in low order to carry selected vt1.5/vc-11 01: au-3 a is used to carry vt1.5/vc-11 10: reserved 11: sts-1/tug-3 #1 (with its sts-1spe / vc-3) is used in high order csntsdh = ? 1 ? 00: sts-1/tug-3 #1 is used in low order to carry vt-2/vc-12 01: au-3 a is used to carry vt2/vc-12 10: reserved 11: sts-1/tug-3 #1 (with its tu-3/vc-3) is used in high order 6 crhovc4 rx vcat: sts3c/vc-4 configuration 0: configured for non vc-4/sts-3c mode (i.e., when using sub-structured contain- ers/tributaries) 1: configured for vc-4/sts-3c mode - 284 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1f006 7-0 crvc4mac 0x0000 rx vcat: 10/100 port to extract data from vc-4/sts3c bit mapped register to indicate the mac associated to the vc-4/sts-3c in case of configuration in vc-4/sts-3c. bit 0 is associated to port 1 bit 7 is associated to port 8 only a single bit of this register may be set to 1. 0x1f008 ? 0x1f016 1-0 crvcg_x 0x0000 rx: vcg0-7 configuration 00: vcg used in itu/ansi low order virtual concatenation 01: vcg used in non standard itu/ansi low order virtual concatenation and in non lcas 10: reserved 11: vcg used in itu/ansi high order virtual concatenation 2 crlcas_x rx: lcas/non lcas configuration for the vcg0-7 0: vcg in non lcas mode 1: vcg in lcas mode 5-3 tx_vcg_x rx: vcg0-7 to carry the mst_ok used in lcas mode only number of vcg which carry the mst 6 crlccrcrst_x lcas crc reset value for vcg0-7 0x1f018 ? 0x1f026 9-0 rmaxdelvcg_x 0x0200 maximum differential delay value for the vcg0-7 in low order: 3 msb bits represent the max allowed value of differential delay by step of 16 ms 000: 0 ms 001: 16 ms 010: 32 ms (default) 011: 48 ms in high order all 10 bits are used to represent the max allowed value of differential delay by step of 125 s. 0x0000: 0 ms 0x0001: 125 s ... 0x0180: 48 ms 0x1f028 0 crfreezemfi 0x0000 freeze the multiframe-count registers to their current value. 0: multiframe-count status registers are continuously updated with the value received in the multiframe. 1: multiframe-count status registers are not internally updated. table 76: rx virtual concatenation block - general configuration registers (rw) address bit hw symbol init description - 285 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 77: rx virtual concatenation block - alarms (ro) address bit hw symbol init description 0x1f100 ? 0x1f1a6 0 alosqm_x 0x0000 rx lo: loss of sequence indicator for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: the received debounced sequence indicator (rloacsqx) does not match the expected sq value (crlosq register) in non lcas mode. if the n incoming tributar- ies have sequence indicators ordered from 0 to n-1, the decapsulation block will still pass traffic even if this alarm is asserted. cleared on matching sq value. 0: no alarm see table 67 for per vt/vc address offsets. 1 arlolcscrce_x rx lo: lcas crc error for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: the received frame has error in crc in lcas mode only. cleared on matching crc value. 0: no alarm see table 67 for per vt/vc address offsets. 2 arlolcasadded_x rx lo: lcas add successful for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: a member was successfully added to the ok state. 0: no alarm see table 67 for per vt/vc address offsets. 3 arlolcasfail_x rx lo: lcas fail alarm for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: a defect condition occurred and the member goes from ok to fail. 0: no alarm see table 67 for per vt/vc address offsets. 4 arlolcasrem_x rx lo: lcas remove successful for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 see table 67 for per vt/vc address offsets. 0x1f1a8 ? 0x1f1ac 0 ahosqm_x 0x0000 rx ho: loss of sequence indicator for the sts-1/vc-3 1_3 1: the received debounced sq (rhoacsqx) does not match with the expected sq value (crhosq register) in non lcas mode. cleared on matching sq value. 0: no alarm 1 arholcscrce_x rx ho: lcas crc error for the sts-1/vc-3 1_3 1: the received frame has error in crc in lcas mode only. cleared on matching crc value. 0: no alarm 2 arholcasadded_x rx ho: lcas add successful for the sts-1/vc-3 1_3 1: a member was successfully added to the ok state. 0: no alarm 3 arholcasfail_x rx ho: lcas fail alarm for the sts-1/vc-3 1_3 1: a defect condition occurred and the member goes from ok to fail. 0: no alarm 4 arholcasrem_x rx ho: lcas remove successful for the sts-1/vc-3 1_3 1: a member is successfully removed and goes to the idle state. 0: no alarm 0x1f1ae even bits aholoa_x 0x0000 rx ho: group loss of alignment for vcg0 (bit 0) through vcg7 (bit 14) 1: differential delay calculated over received members of vcgx exceeds rmaxdelvcgx. 0: differential delay calculated over received members of vcgx does not exceed rmaxdelvcgx. odd bits aholoa_allvt_x rx ho: global loa for vcg0 (bit 1) through vcg7 (bit 15) 1: differential delay calculated over all received containers exceeds rmaxdelvcgx. 0: differential delay calculated over all received containers does not exceed rmaxdelvcgx. - 286 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1f1b0 even bits aloloa_x 0x0000 rx lo: group loss of alignment for vcg0 (bit 0) through vcg7 (bit 14) indicates if payload carrying members of a vcg (ctrl is norm or eos) have differ- ential delay larger than the limit configured by rmaxdelvcg. 1: differential delay for vcgx exceeds limit. 0: differential delay for vcgx does not exceed limit. odd bits aloloa_allvt_x rx lo: global loa for vcg0 (bit 1) through vcg7 (bit 15) indicates if all members associated with a vcg (including members carrying add, dnu or idle) have differential delay larger than the limit configured by rmaxdelvcg. 1: differential delay for vcgx exceeds limit. 0: differential delay for vcgx does not exceed limit. 0x1f1b2 7-0 arxfifo_x 0x0000 rx fifo overflow for the vcg0-7 1: the sdram fifo is in overflow state (not in vc-4 mode). 0: no overflow (not in vc-4 mode) 0x1f1b4 7-0 arholcasgidm_x 0x0000 rx ho: gid mismatch alarm for vcg0-7 0x1f1b6 7-0 arlolcasgidm_x 0x0000 rx lo: gid mismatch alarm for vcg0-7 table 78: rx virtual concatenation block - alarm and interrupt masks (rw) address bit hw symbol init description 0x1f300 ? 0x1f3a6 0 malosqm_x 0x001f rx lo: loss of sequence indicator alarm mask for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: alarm is masked (default) 0: alarm is not masked see table 67 for per vt/vc address offsets. 1 marlolcscrce_x rx lo: lcas crc error alarm mask for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: alarm is masked (default) 0: alarm is not masked see table 67 for per vt/vc address offsets. 2 marlolcasadded_x rx lo: lcas add successful alarm mask for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: alarm is masked (default) 0: alarm is not masked see table 67 for per vt/vc address offsets. 3 marlolcasfail_x rx lo: lcas fail alarm mask for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: alarm is masked (default) 0: alarm is not masked see table 67 for per vt/vc address offsets. 4 marlolcasrem_x rx lo: lcas remove successful alarm mask for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: alarm is masked (default) 0: alarm is not masked see table 67 for per vt/vc address offsets. table 77: rx virtual concatenation block - alarms (ro) address bit hw symbol init description - 287 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1f3a8 ? 0x1f3ac 0 mahosqm_x 0x001f rx ho: loss of sequence indicator alarm mask for the sts-1/vc-3 1_3 1: alarm is masked (default) 0: alarm is not masked 1 marholcscrce_x rx ho: lcas crc error alarm mask for the sts-1/vc-3 1_3 1: alarm is masked (default) 0: alarm is not masked 2 marholcasadded_x rx ho: lcas add successful alarm mask for the sts-1/vc-3 1_3 1: alarm is masked (default) 0: alarm is not masked 3 marholcasfail_x rx ho: lcas fail alarm mask for the sts-1/vc-3 1_3 1: alarm is masked (default) 0: alarm is not masked 4 marholcasrem_x rx ho: lcas remove successful alarm mask for the sts-1/vc-3 1_3 1: alarm is masked (default) 0: alarm is not masked 0x1f3ae even bits maholoa_x 0xffff rx ho: group loa alarm mask for vcg0 (bit 0) - vcg7 (bit 14) 1: alarm is masked (default) 0: alarm is not masked odd bits maholoa_allvt_x rx ho: global loa alarm mask for vcg0 (bit 1) - vcg7 (bit 15) 1: alarm is masked (default) 0: alarm is not masked 0x1f3b0 even bits maloloa_x 0xffff rx lo: group loa alarm mask for vcg0 (bit 0) - vcg7 (bit 14) 1: alarm is masked (default) 0: alarm is not masked odd bits maloloa_allvt_x rx lo: global loa alarm mask for vcg0 (bit 1) - vcg7 (bit 15) 1: alarm is masked (default) 0: alarm is not masked 0x1f3b2 7-0 marxfifo_x 0x00ff rx fifo overflow alarm mask for the vcg 0_7 1: alarm is masked (default) 0: alarm is not masked 0x1f3b4 7-0 marholcasgidm_x 0x00ff rx ho: gid mismatch alarm mask for the vcg 0_7 0x1f3b6 7-0 marlolcasgidm_x 0x00ff rx lo: gid mismatch alarm mask for the vcg 0_7 table 78: rx virtual concatenation block - alarm and interrupt masks (rw) address bit hw symbol init description - 288 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1f3b8 0 mavcr_losqm_interrupt 0x00ff rx lo loss of sequence indicator alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 1 mavcr_locrce_interrupt rx lo: lcas crc error alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 2 mavcr_loadded_interrupt rx lo: lcas add successful alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 3 mavcr_lofail_interrupt rx lo: lcas fail alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 4 mavcr_lorem_interrupt rx lo: lcas remove successful alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 5 mavcr_rxlcaslo_interrupt rx lo lcas alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 6 mavct_txlcaslo_interrupt tx lo lcas alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 7 marxtxlcaslo_interrupt rx/tx lo lcas alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 0x1f3ba 0 mavcr_hosqm_interrupt 0x00ff rx ho loss of sequence indicator alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 1 mavcr_hocrce_interrupt rx ho: lcas crc error alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 2 mavcr_hoadded_interrupt rx ho: lcas add successful alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 3 mavcr_hofail_interrupt rx ho: lcas fail alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 4 mavcr_horem_interrupt rx ho: lcas remove successful alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 5 mavcr_rxlcasho_interrupt rx ho lcas alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 6 mavct_txlcasho_interrupt tx ho lcas alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 7 marxtxlcasho_interrupt rx/tx ho lcas alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked table 78: rx virtual concatenation block - alarm and interrupt masks (rw) address bit hw symbol init description - 289 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1f3bc 0 mavcr_loloa_interrupt 0x001f rx lo loss of alignment alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 1 mavcr_lolcasgidm_interrupt rx lo gid mismatch alarm interrupt mask 2 mavct_txloprd2vcg_interrupt tx lo prd2 vcg alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 3 mavct_txloprd3vcg_interrupt tx lo prd3 vcg alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 4 mavcr_lovcg_interrupt rx/tx lo vcg alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 0x1f3be 0 mavcr_holoa_interrupt 0x001f rx ho loss of alignment alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 1 mavcr_holcasgidm_interrupt rx ho gid mismatch alarm interrupt mask 2 mavct_txhoprd2vcg_interrupt tx ho prd2 vcg alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 3 mavct_txhoprd3vcg_interrupt tx ho prd3 vcg alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 4 mavcr_hovcg_interrupt rx/tx ho vcg alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 0x1f3c0 0 mavcr_rxfifo_interrupt 0x0001 rx fifo overflow alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 0x1f3c2 0 marxtxlo_interrupt 0x0001 rx/tx lo alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 0x1f3c4 0 marxtxho_interrupt 0x0001 rx/tx ho alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked 0x1f3c6 0 marxtxholo_interrupt 0x0001 rx/tx ho/lo alarm interrupt mask 1: interrupt is masked (default) 0: interrupt is not masked table 78: rx virtual concatenation block - alarm and interrupt masks (rw) address bit hw symbol init description - 290 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 79: rx virtual concatenation block - latched alarms (rr) address bit hw symbol init description 0x1f200 ? 0x1f2a6 0 l1alosqm_x 0x0000 rx lo: loss of sequence indicator latched alarm for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: alarm is latched (clear on read) for each member 0: no alarm is latched see table 67 for per vt/vc address offsets. 1 l1arlolcscrce_x rx lo: lcas crc error latched alarm for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: alarm is latched (clear on read) for each member 0: no alarm is latched see table 67 for per vt/vc address offsets. 2 l1arlolcasadded_x rx lo: lcas add successful latched alarm for the sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 1: alarm is latched (clear on read) for each member 0: no alarm is latched see table 67 for per vt/vc address offsets. 3 l1arlolcasfail_x rx lo: lcas fail latched alarm for the sts-1/vc-3 1_3, tug-2 1_7 and tu- 1 1_4 1: alarm is latched (clear on read) for each member 0: no alarm is latched see table 67 for per vt/vc address offsets. 4 l1arlolcasrem_x rx lo: lcas remove successful latched alarm for the sts-1/vc-3 1_3, tug- 2 1_7 and tu-1 1_4 1: alarm is latched (clear on read) for each member 0: no alarm is latched see table 67 for per vt/vc address offsets. 0x1f2a8 ? 0x1f2ac 0 l1ahosqm_x 0x0000 rx ho: loss of sequence indicator latched alarm for the sts-1/vc-3 1_3, tug-2 8 and tu-1 5 1: alarm is latched (clear on read) for each member 0: no alarm is latched 1 l1arholcscrce_x rx ho: lcas crc error latched alarm for the sts-1/vc-3 1_3 1: alarm is latched (clear on read) for each member 0: no alarm is latched 2 l1arholcasadded_x rx ho: lcas add successful latched alarm for the sts-1/vc-3 1_3 1: alarm is latched (clear on read) for each member 0: no alarm is latched 3 l1arholcasfail_x rx ho: lcas fail latched alarm for the sts-1/vc-3 1_3 1: alarm is latched (clear on read) for each member 0: no alarm is latched 4 l1arholcasrem_x rx ho: lcas remove successful latched alarm for the sts-1/vc-3 1_3 1: alarm is latched (clear on read) for each member 0: no alarm is latched 0x1f2ae even bits l1aholoa_x 0x0000 rx ho group loss of alignment latched alarm for vcg0 (bit 0) - vcg7 (bit 14) 1: alarm is latched (clear on read) for each vcg 0: no alarm is latched odd bits l1aholoa_allvt_x rx ho global loss of alignment latched alarm for vcg0 (bit 1) - vcg7 (bit 15) 1: alarm is latched (clear on read) for each vcg 0: no alarm is latched 0x1f2b0 even bits l1aloloa_x 0x0000 rx lo group loss of alignment latched alarm for vcg0 (bit 0) - vcg7 (bit 14) 1: alarm is latched (clear on read) for each vcg 0: no alarm is latched odd bits l1aloloa_allvt_x rx lo global loss of alignment latched alarm for vcg0 (bit 1) - vcg7 (bit 15) 1: alarm is latched (clear on read) for each vcg 0: no alarm is latched - 291 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1f2b2 7-0 l1arxfifo_x 0x00ff rx fifo overflow latched alarm for the vcg0-7 (not in vc-4 mode) 1: alarm is latched (clear on read) for each vcg 0: no alarm is latched 0x1f2b4 7-0 l1arholcasgidm_x 0x0000 rx ho: gid mismatch latched alarm for the vcg0-7 0x1f2b6 7-0 l1arlolcasgidm_x 0x0000 rx lo: gid mismatch latched alarm for the vcg0-7 table 80: rx virtual concatenation block - interrupts (ro) address bit hw symbol init description 0x1f080 0 vcr_losqm_interrupt 0x0000 rx lo loss of sequence indicator alarm interrupt 1: interrupt for all members 0: no interrupt 1 vcr_locrce_interrupt rx lo lcas crc error alarm interrupt 1: interrupt for all members 0: no interrupt 2 vcr_loadded_interrupt rx lo lcas add successful alarm interrupt 1: interrupt for all members 0: no interrupt 3 vcr_lofail_interrupt rx lo lcas fail alarm interrupt 1: interrupt for all members 0: no interrupt 4 vcr_lorem_interrupt rx lo lcas remove successful alarm interrupt 1: interrupt for all members 0: no interrupt 5 vcr_rxlcaslo_interrupt rx lcas lo alarm interrupt 1: interrupt for all alarms in low order in rx and for all members 0: no interrupt 6 rxtxlcaslo_interrupt rx/tx lcas lo alarm interrupt 1: interrupt for all alarms in low order in rx and tx and for all members 0: no interrupt 0x1f082 0 vcr_hosqm_interrupt 0x0000 rx ho loss of sequence indicator alarm interrupt 1 vcr_hocrce_interrupt rx ho lcas crc error alarm interrupt 1: interrupt for all members 0: no interrupt 2 vcr_hoadded_interrupt rx ho lcas add successful alarm interrupt 1: interrupt for all members 0: no interrupt 3 vcr_hofail_interrupt rx ho lcas fail alarm interrupt 1: interrupt for all members 0: no interrupt 4 vcr_horem_interrupt rx ho lcas remove successful alarm interrupt 1: interrupt for all members 0: no interrupt 5 vcr_rxlcasho_interrupt rx ho lcas alarm interrupt 1: interrupt for all members 0: no interrupt 6 rxtxlcasho_interrupt rx/tx lcas ho alarm interrupt 1: interrupt for all members 0: no interrupt table 79: rx virtual concatenation block - latched alarms (rr) address bit hw symbol init description - 292 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x1f084 0 vcr_loloa_interrupt 0x0000 rx lo loss of alignment alarm interrupt 1: interrupt for all members 0: no interrupt 1 vcr_holoa_interrupt rx ho loss of alignment alarm interrupt 1: interrupt for all members 0: no interrupt 2 vcr_lolcasgidm_interrupt rx lo gid mismatch alarm interrupt 3 vcr_holcasgidm_interrupt rx ho gid mismatch alarm interrupt 4 vcr_lovcg_interrupt rx lo vcg alarm interrupt 1: interrupt for all vcg 0: no interrupt 5 vcr_hovcg_interrupt rx ho vcg alarm interrupt 1: interrupt for all vcg 0: no interrupt 0x1f086 0 vcr_rxfifo_interrupt 0x0000 rx fifo overflow alarm interrupt 1: interrupt for all rx fifo overflow alarms (not in vc-4 mode) 0: no interrupt 0x1f088 0 rxtxho_interrupt 0x0000 rx/tx lcas ho alarm interrupt 1: interrupt for all rx and tx lcas high order alarms 0: no interrupt 0x1f08a 0 rxtxlo_interrupt 0x0000 rx/tx lo alarm interrupt 1: interrupt for all rx/tx lcas low order alarms 0: no interrupt 0x1f08c 0 rxtxholo_interrupt 0x0000 rx/tx lo/ho alarm interrupt 1: interrupt for all rx and tx lcas high order and low order alarms 0: no interrupt 0x1f08e 0 rxtxconc_interrupt 0x0000 rx/tx virtual concatenation alarm interrupt 1: interrupt for all alarms in virtual concatenation rx and tx 0: no interrupt table 81: rx virtual concatenation block - low order tributary configuration (rw) address bit hw symbol init description 0x13900 ? 0x139a6 1-0 crlopool_x 0x07e0 00: this low order tributary is assigned to a global pool of resources. (default) 01: this low order tributary is assigned to a non-lcas pool of resources. 10: this low order tributary is assigned to a lcas idle pool of resources. 11: this low order tributary is assigned to a lcas active pool of resources. see table 67 for per vt/vc address offsets. 4-2 crlovcg_x 0x07e0 these 3 bits determine the vcg to which the select low order tributary has been assigned. only eight vcgs are available. (default = 000). see table 67 for per vt/vc address offsets. 10-5 crlosq_x 0x07e0 when in low order virtual concatenation, these 6 bits are used to configure/assign a sequence indicator value for the select low order tributary per vcg. in lcas mode, these bits are accessed only by the lcas state machine. in non-lcas mode, these bits are accessed only by the host. (default = 111111). see ta b l e 6 7 for per vt/vc address offsets. 11 crlofmstfail_x 0x07e0 rx lo configuration for the rx sts-1/vc-3 1, tug-2 1 and tu-1 1: lcas mst force fail option. see table 67 for per vt/vc address offsets. table 80: rx virtual concatenation block - interrupts (ro) address bit hw symbol init description - 293 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 82: rx virtual concatenation block - high order tributary configuration (rw) address bit hw symbol init description 0x13800 0x13802 0x13804 1-0 crhopool_x 0x1fe0 00: this high order tributary is assigned to a global pool of resources. (default) 01: this high order tributary is assigned to a non-lcas pool of resources. 10: this high order tributary is assigned to a lcas idle pool of resources. 11: this high order tributary is assigned to a lcas active pool of resources. 4-2 crhovcg_x these 3 bits determine the vcg to which the select high order tributary has been assigned. only eight vcgs are available. (default=000) 12-5 crhosq_x rx ho configuration per sts-1/vc-3 1: sequence indicator configuration 13 crhofmstfail_x rx ho configuration per sts-1/vc-3 1: lcas mst force fail option table 83: rx virtual concatenation block - status (ro) address bit hw symbol init description 0x18e00 ? 0x18ea6 1-0 srlopool_x 0x0000 00: indicates low order tributary is assigned to the global pool of resources. 01: indicates low order tributary is assigned to the non-lcas pool of resources. 10: indicates low order tributary is assigned to the lcas idle pool of resources. 11: indicates low order tributary is assigned to the lcas active pool of resources. see table 67 for per vt/vc address offsets. 4-2 srlovcg_x when in low order virtual concatenation, indicates to which vcg the low order tribu- tary has been assigned. only eight vcgs are available. see table 67 for per vt/vc address offsets. 8-5 srloctrl_x when in low order virtual concatenation, indicates the state of received control word (i.e., ctrl field), for the member, in both lcas and non-lcas modes extracted from the extended overhead multiframe. if member is not provisioned or during a sonet fail event, this register field is not updated. see table 67 for per vt/vc address offsets. 14-9 srlosq_x when in low order virtual concatenation, indicates the state of the received sequence indicator value (i.e., sq field) for the member and extracted from the extended over- head multiframe. if member is not provisioned or during a sonet fail event, this register field is not updated see table 67 for per vt/vc address offsets. 0x18ea8 0x18eac 0x18eb0 7-0 srhosq_x 0x0000 when in high order virtual concatenation, indicates the assigned sequence indica- tor (sq) value for the select high order tributary per vcg. during a sonet/sdh fail event, this register field is not updated. 0x18eaa 0x18eae 0x18eb2 1-0 srhopool_x 0x0000 00: indicates high order tributary is assigned to a global pool of resources. 01: indicates high order tributary is assigned to a non-lcas pool of resources. 10: indicates high order tributary is assigned to a lcas idle pool of resources. 11: indicated high order tributary is assigned to a lcas active pool of resources. 4-2 srhovcg_x when in high order virtual concatenation, indicates to which vcg the high order tribu- tary has been assigned. only eight vcgs are available. 8-5 srhoctrl_x when in high order virtual concatenation, indicates the state of received control word (i.e., ctrl field), for the member, in both lcas and non-lcas modes. if member is not provisioned or during a sonet fail event, this register field is not updated. - 294 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 84: rx virtual concatenation block - frame counter status (ro) address bit hw symbol init description 0x19000 ? 0x190a6 4-0 srlomfi_x 0x0000 rx lo status of the mfi for sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 in low order (range 0 to 31) see table 67 for per vt/vc address offsets. 9-5 srlofc_x rx lo status of the frame count for sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 in low order (range 0 to 31) see table 67 for per vt/vc address offsets. 0x190a8 ? 0x190ac 3-0 srhomfi1_x 0x0000 rx ho status of the mfi1 field for sts-1/vc-3 1_3 (range 0 to 15) 11-4 srhomfi2_x rx ho status of the mfi2 field for sts-1/vc-3 1_3 (range 0 to 255) table 85: rx virtual concatenation block - differential delay status (ro) address bit hw symbol init description 0x19200 ? 0x192a6 5-0 rrloacsq_x 0x0000 rx lo recovered sequence indicator value for sts-1/vc-3 1_3, tug-2 1_7 and tu-1 1_4 value of the sq indicator after debounce filter, to be compared with the expected sq value see table 67 for per vt/vc address offsets. 0x192a8 ? 0x192ac 7-0 rrhoacsq_x 0x0000 rx ho recovered sequence indicator value for sts-1/vc-3 1_3 value of the sq indicator after debounce filter, to be compared with the expected sq value 0x192ae ? 0x192bc 11-0 rdifdelvcg_x 0x0000 rx differential delay for the vcg 0_7 value of the calculated differential delay per vcg until 128 ms in lo and ho. low order 4 lsb bits from 0000 to 1000, by step of 16 ms 0000: 0 ms 0001: 16 ms ... 0111: 112 ms 1000: 128 ms high order 11 lsb bits (from 0x000 to 0x400) are used by step of 125 s but with a maximum value of 128 ms. - 295 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ethernet to sonet handling registers tables 86 through 90 - configuration and status of the ethernet frame format block (output of the ethernet mac) table 86: ethernet frame format block - general configuration (rw) address bit hw symbol init description 0x1d6a0 7-0 ctfcmode 0x0000 full duplex mode: pause frame filtering in the ethernet-to-sonet direction for macs 0-7. regardless of whether received pause frames are used to stop outgoing ethernet traffic, this bit determines if pause frames are passed on to sonet/sdh. 1: pause frames are passed on to sonet 0: pause frames are dropped after the mac block (not encapsulated) 0x1d6a2 1-0 cinrt_grp125m 0x0001 alarm latching configuration for the physical block 125mhz 0x1d6a4 ? 0x1d6b2 0 crxtmodex (0-7) 0x0000 rx encapsulation discard frame enable for the mac(0-7) table 87: ethernet frame format block - alarms (ro) address bit hw symbol init description 0x1d698 7-0 atetherrx 0x0000 transmit errored ethernet frame alarm for mac0-7 0: no alarm 1: an errored ethernet frame is detected by the mac. cleared on the next valid frame. table 88: ethernet frame format block - alarm and interrupt masks (rw) address bit hw symbol init description 0x1d680 7-0 matetherrx 0x00ff transmit errored ethernet frame alarm mask for mac0-7 1: alarm is masked (default) 0: alarm is not masked 0x1d682 0 maesa_global_interrupt 0x0001 global interrupt mask for all the tetherr alarm of all the mac 1: interrupt is masked (default) 0: interrupt is not masked table 89: ethernet frame format block - latched alarms (rr) address bit hw symbol init description 0x1d69c 7-0 l1atetherrx 0x0000 transmit errored ethernet frame latched alarm for mac0-7 0: no alarm is latched 1: alarm is latched. clear on read table 90: ethernet frame format block - interrupts (ro) address bit hw symbol init description 0x1d688 0 esa_tetherr_interrupt 0x0000 transmit errored ethernet frame alarm interrupt 1: interrupt before mask 0: no interrupt 0x1d68a 0 esa_global_interrupt 0x0000 esa global alarm interrupt 1: global interrupt for all the l1atetherr latched alarms 0: no global interrupt - 296 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 91 through 103 - ethernet buffering and flow control in transmit (ethernet to sonet) and receive (sonet to ethernet) paths note: 1. the allowed ranges for the high/low hol watermark registers depends on the sdram configuration (sdram_cfg bit) and the selection of gmii/smii mode, as shown in the table below: table 91: sonet to ethernet - general configuration and watermarks (rw) address bit hw symbol init description 0x19680 7-0 choltxmaccrc 0x00ff ethernet fcs discard for the 8 macs. for each mac, if '1' is selected, the lan crc of the incoming packets is kept; if '0' is selected, the lan crc is discarded. 0x19682 0 choltrstram 0x0000 sdram reset mode in case of hol fifo overflow. this bit affects all 8 mac channels. 1: after an hol fifo (ethernet packet buffering before the output) overflow, the fifo is reset to empty. 0: after overflow, enough recent packets are discarded to bring the hol fifo fill level below the high watermark. 0x19686 0x1968e 0x19696 0x1969e 0x196a6 0x196ae 0x196b6 0x196be 7-0 rholhwtmk_msb_x 0x00ff hol flow control: high watermark msb for the mac0-7 (see note 1). 0x19688 0x19690 0x19698 0x196a0 0x196a8 0x196b0 0x196b8 0x196c0 15-0 rholhwtmk_lsb_x 0xffff hol flow control: high watermark lsb for the mac0-7 (see note 1). 0x1968a 0x19692 0x1969a 0x196a2 0x196aa 0x196b2 0x196ba 0x196c2 7-0 rhollwtmk_msb_x 0x00ff hol flow control: low watermark msb for the mac0-7 (see note 1). 0x1968c 0x19694 0x1969c 0x196a4 0x196ac 0x196b4 0x196bc 0x196c4 15-0 rhollwtmk_lsb_x 0xffff hol flow control: low watermark lsb for the mac0-7 (see note 1). - 297 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers allowed range for high/low hol watermark registers comments: 1. in the watermark registers, one step of 1 hex corresponds to four bytes in the hol fifo. for example, if you lower the hol watermark by a hex value of "1", the hol fifo threshold will be lowered by four bytes. 2. for the high hol watermark, the maximum allowed value corresponds to the whole allocated fifo space minus one 32 bit word (4 bytes). mode memory allocated to each fifo minimum value for rhollwtmk_msb_x, rhollwtmk_lsb_x maximum value for rholhwtmk_msb_x, rholhwtmk_lsb_x recommended default value sdram 8mb, smii 256 kb 0000 0020 0000 ffff 0000 7fff sdram 8mb, gmii 2mb 0000 0020 0007 ffff 0003 ffff sdram 16mb, smii 512 kb 0000 0020 0001 ffff 0000 ffff sdram 16mb, gmii 4mb 0000 0020 000f ffff 0007 ffff sdram 32mb, smii 1 mb 0000 0020 0003 7fff 0001 ffff sdram 32mb, gmii 8 mb 0000 0020 001f ffff 000f ffff table 92: sonet to ethernet - sdram alarms (ro) address bit hw symbol init description 0x19640 7-0 aholfifox 0x0000 sdram overflow alarm for mac0-7. if this overflow occurs, the number of dropped frames is determined by the difference between the decap- sulation frame counter and the mac frame counter. 0x19642 7-0 aholptrramerrx 0x0000 sdram pointer error alarm for mac0-7 0x19644 0 count_dftc_100m 0x0000 count status bit for the dftc block table 93: sonet to ethernet - sdram alarm and interrupt masks (rw) address bit hw symbol init description 0x19600 7-0 maholfifox 0x00ff sdram overflow alarm mask for the mac0-7 0x19602 7-0 maholptrramerrx 0x00ff sdram pointer error alarm mask for the mac0-7 0x19604 0 mcount_dftc_100m 0x0001 mask of the count status bit for the dftc block 0x19606 0 madftc_holptrramerr_interrupt 0x0001 sdram pointer error alarm mask interrupt 0x19608 0 madftc_holfifo_interrupt 0x0001 sdram overflow alarm mask interrupt 0x1960a 0 madftc_100m_interrupt 0x0001 sdram controller block alarm mask interrupt table 94: sonet to ethernet - sdram latched alarms rr) address bit hw symbol init description 0x19650 7-0 l1aholfifox 0x0000 sdram overflow latched alarm for the mac0-7 0x19652 7-0 l1aholptrramerrx 0x0000 sdram pointer error latched alarm for the mac0-7 0x19654 0 lcount_dftc_100m 0x0000 latched count status bit for the dftc block - 298 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 95: sonet to ethernet - sdram interrupts (ro) address bit hw symbol init description 0x19660 0 dftc_holfifo_interrupt 0x0000 sdram interrupt 0x19662 0 dftc_holptrramerr_interrupt 0x0000 sdram pointer error interrupt 0x19664 0 dftc_100m_interrupt 0x0000 sdram controller block interrupt 0x19666 0 dftc_global_interrupt 0x0000 dftc global interrupt table 96: sonet to ethernet - sdram performance counters (rr) address bit hw symbol init description 0x19620 0x19622 0x19624 0x19626 0x19628 0x1962a 0x1962c 0x1962e 15-0 rpcrstholramx 0x0000 reset mac0-7 sdram part performance counter (overflow) table 97: sonet to ethernet - sdram fifo status (ro) address bit hw symbol init description 0x19678 7-0 hol_hwtmk_detectx 0x0000 high watermark status for hol sdram part 0x1967a 7-0 hol_lwtmk_detectx 0x0000 low watermark status for hol sdram part table 98: ethernet to sonet - flow control configuration (rw) address bit hw symbol init description 0x19800 0x19808 0x19810 0x19818 0x19820 0x19828 0x19830 0x19838 7-0 rhwtmk_msb_x 0x00ff flow control: high watermark msb for the mac0-7 value by step of 32 bit word mac 0 to 7 in smii (recommended value is 0x0000) sdram 8mb: range for all the watermark from 0x000020 to 0x001fff sdram 16mb: range for all the watermark from 0x000020 to 0x003fff sdram 32mb: range for all the watermark from 0x000020 to 0x007fff mac 0 in gmii (recommended value is 0x0000) sdram 8mb: range for all the watermark from 0x000020 to 0x00ffff sdram 16mb: range for all the watermark from 0x000020 to 0x01ffff sdram 32mb: range for all the watermark from 0x000020 to 0x03ffff 0x19802 0x1980a 0x19812 0x1981a 0x19822 0x1982a 0x19832 0x1983a 15-0 rhwtmk_lsb_x 0xffff flow control: high watermark lsb for the mac0-7 value by step of 32 bit word mac 0 to 7 in smii (recommended value is 0x186a) sdram 8mb: range for all the watermark from 0x000020 to 0x001fff sdram 16mb: range for all the watermark from 0x000020 to 0x003fff sdram 32mb: range for all the watermark from 0x000020 to 0x007fff mac 0 in gmii (recommended value is 0xc350) sdram 8mb: range for all the watermark from 0x000020 to 0x00ffff sdram 16mb: range for all the watermark from 0x000020 to 0x01ffff sdram 32mb: range for all the watermark from 0x000020 to 0x03ffff - 299 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x19804 0x1980c 0x19814 0x1981c 0x19824 0x1982c 0x19834 0x1983c 7-0 rlwtmk_msb_x 0x00ff flow control: low watermark msb for the mac0-7 value by step of 32 bit word mac 0 to 7 in smii sdram 8mb: range for all the watermark from 0x000020 to 0x001fff sdram 16mb: range for all the watermark from 0x000020 to 0x003fff sdram 32mb: range for all the watermark from 0x000020 to 0x007fff mac 0 in gmii sdram 8mb: range for all the watermark from 0x000020 to 0x00ffff sdram 16mb: range for all the watermark from 0x000020 to 0x01ffff sdram 32mb: range for all the watermark from 0x000020 to 0x03ffff 0x19806 0x1980e 0x19816 0x1981e 0x19826 0x1982e 0x19836 0x1983e 15-0 rlwtmk_lsb_x 0xffff flow control: low watermark lsb for the mac0-7 value by step of 32 bit word mac 0 to 7 in smii sdram 8mb: range for all the watermark from 0x000020 to 0x001fff sdram 16mb: range for all the watermark from 0x000020 to 0x003fff sdram 32mb: range for all the watermark from 0x000020 to 0x007fff mac 0 in gmii sdram 8mb: range for all the watermark from 0x000020 to 0x00ffff sdram 16mb: range for all the watermark from 0x000020 to 0x01ffff sdram 32mb: range for all the watermark from 0x000020 to 0x03ffff 0x19840 7-0 ctxmaccrc 0x00ff ethernet fcs discard for all the 8 mac 0: lan fcs is discarded before encapsulation 1: lan fcs is kept during encapsulation one bit per mac (lsb for mac0, msb for mac7) 0x19842 1-0 cinrt_grp100m 0x0001 alarm latching configuration for the sdram alarm group ( table 101 ) criteria used to create latched alarms from the raw (unlatched) alarms. 00: positive level 01: rising edge (default) 10: falling edge 11: rising or falling edge 0x19844 0 ctrstram 0x0000 txfifo reset mode after overflow. this bit affects all 8 mac channels. 1: after a txfifo overflow, the fifo is reset to empty. 0: after txfifo overflow, enough recent packets are discarded to bring the txfifo fill level below the high watermark. table 99: sdram controller alarm (tx and rx) (ro) address bit hw symbol init description 0x198c0 7-0 atxfifox 0x0000 tx fifo overflow alarm for the mac0-7 0: no alarm 1: tx fifo overflow is detected. if the fifo resets to empty (ctrstram bit is 1) then this alarm clears after 10 clock cycles, otherwise it clears after the fifo depth falls below the high watermark. if this overflow occurs, the number of dropped frames is determined by the dif- ference between the mac frame counter and encapsulation frame counter. 0x198c2 7-0 aptrramerrx 0x0000 sdram integrity alarm for the tx fifo. corruption at this interface could cause the tx fifo to incorrectly determine it is above its high watermark, causing pause frames to continuously be sent. if this alarm is detected, a per channel soft reset should be considered. 0x198c4 0 arxfifovc4 0x0000 rx fifo overflow alarm in vc-4 mode 0: no alarm 1: rxfifo overflow is detected. cleared on the rxfifo reset 0x198c6 0 alossdclk 0x0000 loss of drop clock alarm 0: no alarm 1: detection of the loss of dclk input. cleared on the recovery of the dclk table 98: ethernet to sonet - flow control configuration (rw) address bit hw symbol init description - 300 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x198c8 0 count_shtc_100m 0x0000 count status bit for the sdram controller 0: no rpcrstsdramx is overflowed 1: count status bit when one of the rpcrstsdramx is overflowed table 100: sdram controller (tx and rx direction) (rw) address bit hw symbol init description 0x198e0 7-0 matxfifox 0x00ff tx fifo overflow alarm mask for the mac0-7 1: alarm is masked (default) 0: alarm is not masked 0x198e2 7-0 maptrramerrx 0x00ff tx ram pointer error alarm mask for the mac0-7 0x198e4 0 mcount_shtc_100m 0x0001 mask of the count status bit for the 100mhz block 1: alarm is masked (default) 0: alarm is not masked 0x198e6 0 marxfifovc4 0x0001 rx fifo overflow alarm mask 1: alarm is masked (default) 0: alarm is not masked 0x198e8 0 malossdclk 0x0001 loss of drop clock alarm mask 1: alarm is masked (default) 0: alarm is not masked 0x198ea 0 mashtc_ptrramerr_interrupt 0x0001 tx ram pointer error alarm mask interrupt 0x198ec 0 mashtc_txfifo_interrupt 0x0001 tx fifo overflow alarm mask interrupt 1: interrupt for all the mac is masked (default) 0: interrupt is not masked 0x198ee 0 mashtc_100m_interrupt 0x0001 sdram controller block alarm mask interrupt 1: general interrupt for all the alarms of table 101 are masked (default) 0: general interrupt for all the alarms of table 101 are not masked table 101: sdram controller (tx and rx directions) (rr) address bit hw symbol init description 0x198d0 7-0 l1atxfifox 0x0000 tx fifo overflow latched alarm for the mac0-7 1: alarm is latched. cleared on read 0: no alarm is latched 0x198d2 7-0 l1aptrramerrx 0x0000 tx ram pointer error latched alarm for the mac0-7 1: alarm is latched. cleared on read 0: no alarm is latched corruption at the sdram interface could cause the txfifo to incorrectly determine it is above its high watermark, causing pause frames to continuously be sent. if this alarm is detected, a per channel soft reset should be considered (tx_resetsx). 0x198d4 0 lcount_shtc_100m 0x0000 latched count status bit for the sdram controller 0x198d6 0 l1arxfifovc4 0x0000 rx fifo overflow latched alarm (vc-4 mode only) 1: alarm is latched. cleared on read 0: no alarm is latched 0x198d8 0 l1alossdclk 0x0000 loss of drop clock latched alarm 1: alarm is latched. cleared on read 0: no alarm is latched table 99: sdram controller alarm (tx and rx) (ro) address bit hw symbol init description - 301 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 102: ethernet to sonet, sdram output - interrupts (ro) address bit hw symbol init description 0x198f8 0 shtc_txfifo_interrupt 0x0000 tx fifo interrupt 1: interrupt is active for all the txfifo 0: no interrupt 0x198fa 0 shtc_ptrramerr_interrupt 0x0000 reserved 0x198fc 0 shtc_100m_interrupt 0x0000 sdram controller block interrupt before the mask mashtc_100m_interrupt 1: interrupt is active for the physical block 100m 0: no interrupt 0x198fe 0 shtc_global_interrupt 0x0000 shtcl global interrupt after the mask mashtc_100m_interrupt 1: interrupt is active for the physical block 100m 0: no interrupt table 103: ethernet to sonet, sdram output - performance counters address bit hw symbol init description 0x19880 ? 0x1988e 15-0 rpcrstsdramx 0x0000 in the ethernet-to-sonet/sdh direction, this register counts the number of times the sdram txfifo area (for channel 0-7) is reset when the txfifo is in overflow condition. (rr when the perf counters are in saturating mode and not rr when the perf counters are in roll over mode) - 302 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tx mapper block registers tables 104 through 107 - configuration, status and interrupt handling of the transmit mapper block tables 108 through 118 - configuration of the transmit mapper block table 104: mapper block - reset (rw) address bit hw symbol init description 0x1d288 0 vtmd_conf_resetcounters 0x0000 vtmapper: reset counters 0: no reset state 1: reset counters in the transmit path table 105: mapper block - interrupt configuration (ro) address bit hw symbol init description 0x1d28a 0 vtmd_global_interrupt 0x0000 global interrupt of the vtmapper 1: interrupt (sonet/sdh side) is active 0: no interrupt table 106: mapper block - interrupt mask (rw) address bit hw symbol init description 0x1d28c 0 mavtmd_interrupt 0x0001 vtmapper interrupt mask 1: vtmapper interrupt is masked. 0: vtmapper interrupt is not masked table 107: mapper and demapper block - status (ro) address bit hw symbol init description 0x1d28e 0 vtmd_conf_deviceinitialized 0x0000 status of the end of initialization of the design 0: design is not initialized (need end_init_micro asserted after the 1: design is initialized table 108: mapper block - timing configuration (rw) address bit hw symbol init description 0x13c40 11-0 pulsedelay 0x0000 defines the pulse delay that is needed to let a frame arrive in the tx combus interface one frame after the request from the combus is received. set to 0x2c0. 0x13c42 0 au_mode 0x0001 defines the au mode: au-3 (0) or au-4 (1) 0x13c44 0 au4_ho_vc4_payload 0x0000 defines what is in a vc-4 in au-4 mode (true is a c4 container, false is substructured) 0x13c46 1-0 vc3_xconnect_0 0x0024 anticipate the timing of the l3 xconnect 3-2 vc3_xconnect_1 5-4 vc3_xconnect_2 - 303 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 109: mapper block - tug-3/vc-3 configuration (rw) address bit hw symbol index init description 0x13c00 0x13c02 0x13c04 0 au4_tug3_mode 0 1 2 0x0000 defines what is in a tug-3: tu-3 (0) or tug-2 (1) 1 vc3_payloadtype defines what is in a vc-3: tug-2 (0) or c3 (1) table 110: mapper block - tug-2 configuration (rw) address bit hw symbol index init description 0x13c80 0x13c82 ... 0x13ca8 0 tug2_is_tu12 0 1 ... 20 0x0000 defines if a tug-2 contains 4 tu-11 ? s (0) or 3 tu-12 ? s (1) table 111: mapper block - pointer configuration (rw) address bit hw symbol index init description 0x13d00 0x13d02 ... 0x13da6 0 pointervaluezero 0 1 ... 83 0x0001 select the value of the tu-11/tu-12 pointers: zero (1), or to 78/105 (0). table 112: mapper block - general configuration, low order (rw) address bit hw symbol init description 0x1a400 0 au_mode 0x0006 selects au-3 (0) or au-4 (1) mode when in low order mode. 1 usedefaultmapping use default mapping for the tx lo cross connect (ignore lomp_mapram when set). 2 uppermapramvalid select tx lo cross connect bank read by hardware. software can only write to the inactive bank. 3 readuppermaprambank select tx lo cross connect bank accessed by software. table 113: mapper block - tug-2 configuration (rw) address bit hw symbol index init description 0x1a500 0x1a502 ... 0x1a528 0istu12 0 1 ... 20 0x0000 sets if a tug-2 contains 4 tu-11 ? s (0) or 3 tu-12 ? s (1) table 114: mapper block - poh configuration (rw) address bit hw symbol index init description 0x1a800 0x1a808 ... 0x1aa98 0 bip2_error 0 1 ... 83 0x004a test: bip-2 error insertion 1 pointerzerovalue flags if v1/v2 pointer value is 0 or 78/105 2 sendvtais force vt/tu ais 3 senduneq force unequipped 4 uneqselect select normal (0) or supervisory (1) unequipped 5 sendunidirectional sets an unidirectional signal vc 6 singlerdi single (1) or three (0) bit rdi selection - 304 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers see below for detailed offsets. the index of the vt/tu (0..83) in these arrays is according to the klm numbering (see trans- mit low order path termination section of data sheet) index = (k-1)*28 + (l-1)*4 + (m-1). 0x1a802 0x1a80a ... 0x1aa9a 7-0 ext_signallabel 0 1 ... 83 0x0000 the value of the transmitted extended signal label 0x1a804 0x1a80c ... 0x1aa9c 1-0 rei_source 0 1 ... 83 0x000a select rei source, poh ram (00), poh port (01), or alarm indication port (10=default) 3-2 rdi_source select rdi source, poh ram (00), poh port (01), or alarm indication port (10=default) 5-4 ext_tsl_source select extended signal label source, poh ram (00), or poh port (01) 7-6 lo_vc_source select lo virtual concatenation control packet, poh ram (00=default), poh port (01), or pass through (11) 9-8 aps_source select aps source, poh ram (00=default), or poh port (01) 11-10 dl_source select data link source, poh ram (00=default), or poh port (01) 0x1a806 0x1a80e ... 0x1aa9e 1-0 j2_source 0 1 ... 83 0x0000 select j2 source, poh ram (00=default), or poh port (01) 3-2 n2_source select n2/z6 source, poh ram (00=default), or poh port (01) table 115: mapper block - cross connect configuration (rw) address bit hw symbol index init description 0x1a600 0x1a602 ... 0x1a6a6 6-0 mapram_data 0 1 ... 83 0x0000 transmit low order cross connect map. disabled if usedefaultmapping is true. table 116: mapper block - v4 configuration (rw) address bit hw symbol index init description 0x1a000 0x1a002 ... 0x1a0a6 7-0 v4_bytevalue 0 1 ... 83 0x0000 value of the v4 byte table 117: mapper block - poh byte values (rw) address bit hw symbol index init description 0x1b000 0x1b002 ... 0x1bd1e 7-0 poh_bytevalue 0 1 ... 1679 0x0000 value of the poh byte offset index description offset index description 0x000 0 j2 message byte 0 0xa80 0 v5 byte 0x002 j2 message byte 1 0xa82 n2/z6 byte ... ... 0xa84 k4/z7 byte 0x01e j2 message byte 15 0xa86 not used table 114: mapper block - poh configuration (rw) address bit hw symbol index init description - 305 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x020 1 j2 message byte 0 0xa88 1 v5 byte 0x022 j2 message byte 1 0xa8a n2/z6 byte ... ... 0xa8c k4/z7 byte 0x03e j2 message byte 15 0xa8e not used ... ... 0xa60 83 j2 message byte 0 0xd18 83 v5 byte 0xa62 j2 message byte 1 0xd1a n2/z6 byte ... ... 0xd1c k4/z7 byte 0xa7e j2 message byte 15 0xd1e not used table 118: mapper block - bypass control (rw) address bit hw symbol index init description 0x1a440 0x1a442 0x1a444 0bypass 0 1 2 0x0000 enables the poh processing bypass for an au-3 0x1a480 0x1a482 0x1a484 0bypass 0 1 2 0x0000 enables the pointer processing bypass for an au-3 0x1a4c0 0x1a4c2 0x1a4c4 0bypass 0 1 2 0x0000 enables the cross connect bypass for an au-3 offset index description offset index description - 306 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers rx demapper block registers tables 119 through 131 - configuration, status and alarms for the receive demapper block table 119: demapper block - general configuration (rw) address bit hw symbol index init description 0x1c670 0 check_ss 0x0001 activate ss bit checking 0x1c672 0 reserved 0x0006 reserved: this bit must be 0 for correct operation. 1 usedefaultmapping use default mapping for the rx lo cross connect (ignore lodmp_mapram when set). 2 active_mapram_bank_id select rx lo cross connect bank read by hardware. software can only write to the inactive bank. 0x1c674 0 bank_id_mapram 0x0000 select rx lo cross connect bank accessed by software. 0x1c400 0x1c402 ... 0x1c4a6 6-0 mapram_data 0 1 ... 83 0x0000 receive low order cross connect map. disabled if usedefaultmapping is true. table 120: demapper block - bypass control (rw) address bit hw symbol index init description 0x1c600 0x1c602 0x1c604 0bypass 0 1 2 0x0000 enables the cross connect bypass 0x1c620 0x1c622 0x1c624 0bypass 0 1 2 0x0000 enables the pointer processing bypass table 121: demapper block - tug-2 configuration (rw) address bit hw symbol index init description 0x1c680 0x1c682 ... 0x1c6a8 0istu12 0 1 ... 20 0x0000 tug-2 contains tu-12 ? s table 122: demapper block - performance counters shadow registers (ro) address bit hw symbol index init description 0x1c800 0x1c804 ... 0x1c94c 4-0 posjustcounter 0 1 ... 83 0x0000 number of positive justifications 0x1c802 0x1c806 ... 0x1c94e 4-0 negjustcounter 0 1 ... 83 0x0000 number of negative justifications - 307 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 123: demapper block - alarm control (rw) address bit hw symbol init description 0x1c660 0 tsf_inhibits_ais 0x003f trail signal failure inhibits ais alarms 1 tsf_inhibits_lop trail signal failure inhibits lop alarms 2 plm_inhibits_ais payload mismatch inhibits ais alarms 3 plm_inhibits_lop payload mismatch inhibits lop alarms 4 lom_inhibits_ais loss of multiframe inhibits ais alarms 5 lom_inhibits_lop loss of multiframe inhibits lop alarms 0x1c662 0 reserved 0x0002 reserved: this bit must be 0 for correct operation. 2-1 inteventcontrol controls latching on raising and falling edges. default value: int_rising_edge. possible values: int_level (00), int_rising_edge (01), int_falling_edge (10), int_both_edges (11) 4-3 pm_eventcontrol controls latching on raising and falling edges 00: pm disabled 01: rising edge 10: falling edge 11: both edges table 124: demapper block - interrupts (ro) address bit hw symbol init description 0x1c640 0 interrupt 0x0000 interrupt generated by ptr processor latched alarms 0x1c642 0 pm 0x0000 summary for performance monitoring 0x1c644 0 fm 0x0000 summary for fault monitoring table 125: demapper block - alarms (ro) address bit hw symbol index init description 0x1c700 0x1c702 ... 0x1c7a6 0 ais_detected 0 1 ... 83 0x0000 low order pointer processor ais defect 1 lossofpointer low order pointer processor lop defect table 126: demapper block - latched alarms (r/cow-1) address bit hw symbol index init description 0x1ca00 0x1ca02 ... 0x1caa6 0 ais_detected 0 1 ... 83 0x0000 low order pointer processor ais defect 1 lossofpointer low order pointer processor lop defect table 127: demapper block - alarm masks (rw) address bit hw symbol index init description 0x1cb00 0x1cb02 ... 0x1cba6 0 ais_detected 0 1 ... 83 0x0003 mask for the low order pointer processor ais defect 1 lossofpointer mask for the low order pointer processor lop defect - 308 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tables 132 through 154 - configuration, status and alarms of the low order poh monitor table 128: lodmp_ptr_defectcorrelations_lp (r/cow-0) address bit hw symbol index init description 0x1cc00 0x1cc02 ... 0x1cca6 0 ais_detected 0 1 ... 83 0x0000 low order pointer processor ais defect 1 lossofpointer low order pointer processor lop defect table 129: lodmp_ptr_defectcorrelations_pm (ro) address bit hw symbol index init description 0x1cd00 0x1cd02 ... 0x1cda6 0 ais_detected 0 1 ... 83 0x0000 low order pointer processor ais defect 1 lossofpointer low order pointer processor lop defect table 130: lodmp_ptr_defectcorrelations_fm (ro) address bit hw symbol index init description 0x1ce00 0x1ce02 ... 0x1cea6 0 ais_detected 0 1 ... 83 0x0000 low order pointer processor ais defect 1 lossofpointer low order pointer processor lop defect table 131: demapper block - poh byte monitors (ro) address bit hw symbol index init description 0x1cf00 0x1cf02 ... 0x1cfa6 7-0 data 0 1 ... 83 0x0000 tu-11/vt1.5 or tu-12/vt2 v1 pointer byte 0x1c000 0x1c002 ... 0x1c0a6 7-0 data 0 1 ... 83 0x0000 tu-11/vt1.5 or tu-12/vt2 v2 pointer byte 0x1c200 0x1c202 ... 0x1c2a6 7-0 data 0 1 ... 83 0x0000 tu-11/vt1.5 or tu-12/vt2 v4 byte table 132: lo poh monitor - bypass control (rw) address bit hw symbol index init description 0x148e0 0x148e2 0x148e4 0bypass 0 1 2 0x0000 activate poh processor bypass - 309 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 133: lo poh monitor - j2 trace message handling address bit hw symbol index init description 0x14900 0x14902 ... 0x1491e 7-0 j2_byte 0 1 ... 15 0x0000 received tti message byte (ro) 0x14980 0x14982 ... 0x1499e 7-0 j2_byte 0 1 ... 15 0x0000 accepted tti message byte (ro) 0x16000 0x16002 ... 0x16a7e 7-0 j2_byte 0 1 ... 1343 0x0000 expected tti message bytes (rw) table 134: lo poh monitor - poh byte monitors (ro) address bit hw symbol index init description 0x17800 0x17808 ... 0x17a98 7-0 v5 0 1 ... 83 0x0000 v5 poh byte 0x17802 0x1780a ... 0x17a9a 7-0 j2 0 1 ... 83 0x0000 j2 poh byte 0x17804 0x1780c ... 0x17a9c 7-0 n2 0 1 ... 83 0x0000 n2/z6 poh byte 0x17806 0x1780e ... 0x17a9e 7-0 k4 0 1 ... 83 0x0000 k4/z7 poh byte table 135: lo poh monitor - accepted values (ro) address bit hw symbol index init description 0x14000 0x14004 ... 0x1414c 2-0 tsl_accepted 0 1 ... 83 0x0000 accepted tsl (v5) bits 0x14002 0x14006 ... 0x1414e 7-0 etsl_accepted 0 1 ... 83 0x0000 accepted e-tsl (k4/z7) byte table 136: lo poh monitor - expected values (rw) address bit hw symbol index init description 0x14400 0x14404 ... 0x1454c 2-0 tsl_expected 0 1 ... 83 0x0000 expected tsl (v5) bits - 310 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x14402 0x14406 ... 0x1454e 7-0 etsl_expected 0 1 ... 83 0x0000 expected e-tsl (k4/z7) byte table 137: lo poh monitor - general configuration (rw) address bit hw symbol init description 0x148d0 7-0 resetcounters 0x0000 reset performance counters when writing 0x91 (write only) 0x14880 0 reserved 0x0004 reserved: this field must be false (0) for correct operation. 1 shadowregister_enable enable performance monitor shadow registers 3-2 inteventcontrol mode to latch defects for interrupt. default value: int_rising_edge. pos- sible values: int_level (00), int_rising_edge (01), int_falling_edge (10), int_both_edges (11) 5-4 pm_eventcontrol mode to latch defects for fault/performance monitoring 00: pm disabled 01: rising edge 10: falling edge 11: both edges 0x14800 0 vc4hasc4 0x19a8 high order vc-4 frame contains c-4 data 2-1 rdi_nrofintervals specify number of intervals before accepting rdi bit: 3 (00), 5 (01) or 10 (10) 6-3 erdi_nrofintervals specify number of intervals before accepting e-rdi bits (5 to 10) 10-7 tsl_nrofintervals specify number of intervals before accepting tsl bits (3 to 10) 14-11 etsl_nrofintervals specify number of intervals before accepting e-tsl byte (3 to 10) 0x14802 3-0 j2_nrofframestosettim 0x0035 specify number of mismatching multiframes to set tim defect 7-4 j2_nrofframestoresettim specify number of matching multiframes to reset tim defect 8 j2_report_enable enable j2 reporting 15-9 j2_report_channel channel number for j2 reporting 0x14804 0 ais_ssf_disable 0x0000 disable ssf defect in generation of consequent action for ais 1 ais_incais_disable disable ais (v5) defect in generation of consequent action for ais 2 ais_uneq_disable disable uneq defect in generation of consequent action for ais 3 ais_tim_disable disable tim defect in generation of consequent action for ais 4 tsf_ssf_disable disable ssf defect in generation of consequent action for tsf 5 tsf_uneq_disable disable uneq defect in generation of consequent action for tsf 6 tsf_tim_disable disable tim defect in generation of consequent action for tsf 7 tsf_incais_disable disable ais (v5) defect in generation of consequent action for tsf 8 rdi_ssf_disable disable ssf defect in generation of consequent action for rdi 9 rdi_uneq_disable disable uneq defect in generation of consequent action for rdi 10 rdi_tim_disable disable tim defect in generation of consequent action for rdi 11 rdi_plm_disable disable plm defect in generation of consequent action for rdi 12 lom_lom_disable disable lom defect in generation of consequent action for lom 13 plm_plm_disable disable plm defect in generation of consequent action for plm bits in register 0x14804 disable consequent actions when they are set to one. see mapper/demapper consequent actions per block beginning on page 390 for more details. in general, consequent actions should always be enabled. specifically, if the ssf, uneq, ais, lom or plm actions are disabled (bits 0,1,2,4,5,7,12 or 13 set to one), it is possible to observe sink side traffic loss during lcas deprovisioning. table 136: lo poh monitor - expected values (rw) address bit hw symbol index init description - 311 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 138: lo poh monitor - channel configuration (rw) address bit hw symbol index init description 0x17c00 0x17c08 ... 0x17e98 0 unidirectional 0 1 ... 83 0x0000 enables the unidirectional option. if the unidirectional mode is active, the poh monitor reports farendblockerrorcounter = 0 and clears all received rdi defects. default value = false 1 insertais force ais insertion 2 erdi_disable disable k4/z7 e-rdi processing 0x17c02 0x17c0a ... 0x17e9a 0 j2_extimessage 0 1 ... 83 0x0000 j2 tti 16 byte message or repeating non-specific byte mode 1 j2_timenable enable j2 tim monitoring 0x17c04 0x17c0c ... 0x17e9c 10-0 bip2_deg_setthreshold 0 1 ... 83 0x1001 specify error threshold to set degraded interval 14-11 bip2_deg_setnrofintervals specify number of degraded intervals to set signal degrade defect 0x17c06 0x17c0e ... 0x17e9e 10-0 bip2_deg_clearthreshold 0 1 ... 83 0x1001 specify error threshold to clear degraded interval 14-11 bip2_deg_clearnrofintervals specify number of not-degraded intervals to clear signal degrade defect table 139: lo poh monitor - channel status (ro) address bit hw symbol index init description 0x14a00 0x14a02 ... 0x14aa6 0 pohramwriteinsecondbank 0 1 ... 83 0x0000 writing bytes to second poh ram register bank table 140: lo poh monitor - channel report (ro) address bit hw symbol init description 0x148c0 0 j2_stable_1 0x0000 stable j2 tti repeating non-specific byte 1 j2_stable_16 stable j2 tti 16-byte message table 141: lo poh monitor - channel defects (ro) address bit hw symbol index init description 0 x 1 4 c 0 0 0x14c02 ... 0x14ca6 0ci_ssf 0 1 ... 83 0x0000 server signal fail defect 1 v5_deg v5 signal degrade defect 2 v5_ais v5 alarm indication signal defect 3 v5_plm v5 payload mismatch defect 4 v5_uneq v5 unequipped signal defect 5 v5_rfi v5 remote failure indication defect 6 v5_rdi v5 remote defect indication defect 7 k4_erdi_c k4/z7 enhanced-rdi connectivity defect 8 k4_erdi_p k4/z7 enhanced-rdi payload defect 9 k4_erdi_s k4/z7 enhanced-rdi server defect 10 k4_lom k4/z7 loss of multiframe defect 11 j2_tim j2 trace identifier mismatch defect 12 j2_tti_zero j2 tti all-zero repeating byte defect - 312 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 142: lo poh monitor - defect correlations (ro) address bit hw symbol index init description 0x14e00 0x14e02 ... 0x14ea6 0ssf 0 1 ... 83 0x0000 server signal fail defect 1 deg degraded signal defect 2 ais alarm indication signal defect 3 plm payload mismatch defect 4 uneq unequipped signal defect 5 rfi remote failure indication defect 6 rdi remote defect indication defect 7 erdi_c enhanced-rdi connectivity defect 8 erdi_p enhanced-rdi payload defect 9 erdi_s enhanced-rdi server defect 10 lom loss of multiframe defect 11 tim trace identifier mismatch defect 12 tti_zero tti all-zero repeating byte defect table 143: lo poh monitor - latched defects (r/cow-1) address bit hw symbol index init description 0x15000 0x15002 ... 0x150a6 0ssf 0 1 ... 83 0x0000 server signal fail defect 1 deg degraded signal defect 2 ais alarm indication signal defect 3 plm payload mismatch defect 4 uneq unequipped signal defect 5 rfi remote failure indication defect 6 rdi remote defect indication defect 7 erdi_c enhanced-rdi connectivity defect 8 erdi_p enhanced-rdi payload defect 9 erdi_s enhanced-rdi server defect 10 lom loss of multiframe defect 11 tim trace identifier mismatch defect 12 tti_zero tti all-zero repeating byte defect - 313 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 144: lo poh monitor - defect correlations latched for pmfm (r/cow-0) address bit hw symbol index init description 0x15200 0x15202 ... 0x152a6 0ssf 0 1 ... 83 0x0000 server signal fail defect 1 deg degraded signal defect 2 ais alarm indication signal defect 3 plm payload mismatch defect 4 uneq unequipped signal defect 5 rfi remote failure indication defect 6 rdi remote defect indication defect 7 erdi_c enhanced-rdi connectivity defect 8 erdi_p enhanced-rdi payload defect 9 erdi_s enhanced-rdi server defect 10 lom loss of multiframe defect 11 tim trace identifier mismatch defect table 145: lo poh monitor - pm defect correlations monitor (ro) address bit hw symbol index init description 0x15400 0x15402 ... 0x154a6 0ssf 0 1 ... 83 0x0000 server signal fail defect 1 deg degraded signal defect 2 ais alarm indication signal defect 3 plm payload mismatch defect 4 uneq unequipped signal defect 5 rfi remote failure indication defect 6 rdi remote defect indication defect 7 erdi_c enhanced-rdi connectivity defect 8 erdi_p enhanced-rdi payload defect 9 erdi_s enhanced-rdi server defect 10 lom loss of multiframe defect 11 tim trace identifier mismatch defect table 146: lo poh monitor - fm defect correlations monitor (ro) address bit hw symbol index init description 0x15600 0x15602 ... 0x156a6 0ssf 0 1 ... 83 0x0000 server signal fail defect 1 deg degraded signal defect 2 ais alarm indication signal defect 3 plm payload mismatch defect 4 uneq unequipped signal defect 5 rfi remote failure indication defect 6 rdi remote defect indication defect 7 erdi_c enhanced-rdi connectivity defect 8 erdi_p enhanced-rdi payload defect 9 erdi_s enhanced-rdi server defect 10 lom loss of multiframe defect 11 tim trace identifier mismatch defect - 314 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 147: lo poh monitor - defect correlations mask (r/w) address bit hw symbol index init description 0x15800 0x15802 ... 0x158a6 0ssf 0 1 ... 83 0x1fff server signal fail mask 1 deg degraded signal defect mask 2 ais alarm indication signal mask 3 plm payload mismatch mask 4 uneq unequipped signal mask 5 rfi remote failure indication mask 6 rdi remote defect indication mask 7 erdi_c enhanced-rdi connectivity mask 8 erdi_p enhanced-rdi payload mask 9 erdi_s enhanced-rdi server mask 10 lom loss of multiframe mask 11 tim trace identifier mismatch mask 12 tti_zero tti all-zero repeating byte mask table 148: lo poh monitor - defect correlations configuration (rw) address bit hw symbol init description 0x148a0 0 uneq_ssf_inhibit_disable 0x0000 disable ssf defect in generation of defect correlation for uneq 1 uneq_tim_disable disable tim defect in generation of defect correlation for uneq 2 uneq_ttizero_disable disable ttizero defect in generation of defect correlation for uneq 3 tim_ssf_inhibit_disable disable ssf defect in generation of defect correlation for tim 4 tim_uneq_inhibit_disable disable uneq defect in generation of defect correlation for tim 5 tim_ttizero_inhibit_disable disable ttizero defect in generation of defect correlation for tim 6 deg_ssf_inhibit_disable disable ssf defect in generation of defect correlation for deg 7 deg_tim_inhibit_disable disable tim defect in generation of defect correlation for deg 8 rdi_ssf_inhibit_disable disable ssf defect in generation of defect correlation for rdi 9 rdi_uneq_inhibit_disable disable uneq defect in generation of defect correlation for rdi 10 rdi_tim_inhibit_disable disable tim defect in generation of defect correlation for rdi 11 rdi_ttizero_inhibit_disable disable ttizero defect in generation of defect correlation for rdi 12 rfi_ssf_inhibit_disable disable ssf defect in generation of defect correlation for rfi 13 rfi_uneq_inhibit_disable disable uneq defect in generation of defect correlation for rfi 14 rfi_tim_inhibit_disable disable tim defect in generation of defect correlation for rfi 15 rfi_ttizero_inhibit_disable disable ttizero defect in generation of defect correlation for rfi 0x148a2 0 ssf_incais_disable 0x0000 disable ais (v5) defect in generation of defect correlation for ssf 1 plm_tsf_inhibit_disable disable tsf defect in generation of defect correlation for plm 2 lom_tsf_inhibit_disable disable tsf defect in generation of defect correlation for lom 3 lom_plm_inhibit_disable disable plm defect in generation of defect correlation for lom 4 ttizero_ssf_inhibit_disable disable ssf defect in generation of defect correlation for ttizero - 315 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 149: lo poh monitor - defect correlations summary (ro) address bit hw symbol index init description 0x15a00 0x15a02 ... 0x15aa6 0 latchforint 0 1 ... 83 0x0000 defect correlations summary latched for interrupt per channel 1 pm defect correlations summary for performance monitoring per channel 2 fm defect correlations summary for fault monitoring per channel table 150: lo poh monitor - defect correlations summary mask (rw) address bit hw symbol index init description 0x15c00 0x15c02 ... 0x15ca6 0mask 0 1 ... 83 0x0001 defect correlations summary mask per channel table 151: lo poh monitor - defect correlations group summary (ro) address bit hw symbol init description 0x14840 0 interrupt 0x0000 defect correlations group summary for interrupt generation 0x14842 0 pm 0x0000 defect correlations group summary for performance monitoring 0x14844 0 fm 0x0000 defect correlations group summary for fault monitoring table 152: lo poh monitor - performance monitor one second latch (ro) address bit hw symbol index init description 0x15e00 0x15e02 ... 0x15ea6 0 nds 0 1 ... 83 0x0000 near-end defect second, tsf occurrence per one second interval 1 fds far-end defect second, rdi occurrence per one second interval table 153: lo poh monitor - performance counters (rw) address bit hw symbol index init description 0x17000 0x17008 ... 0x17298 10-0 bip2_nearendblockerrorcounter 0 1 ... 83 0x0000 bip-2 near-end block errors per one second interval 0x17002 0x1700a ... 0x1729a 11-0 bip2_errorcounter 0 1 ... 83 0x0000 bip-2 errors per one second interval 0x17004 0x1700c ... 0x1729c 10-0 rei_farendblockerrorcounter 0 1 ... 83 0x0000 rei far-end block errors per one second interval table 154: lo poh monitor - performance counter shadow registers (ro) address bit hw symbol index init description 0x17400 0x17408 ... 0x17698 10-0 bip2_nearendblockerrorcounter 0 1 ... 83 0x0000 bip-2 near-end block errors per one second interval - 316 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tables 155 through 162 - configuration, status and alarms of the low order tx alarm indication (ring) port 0x17402 0x1740a ... 0x1769a 11-0 bip2_errorcounter 0 1 ... 83 0x0000 bip-2 errors per one second interval 0x17404 0x1740c ... 0x1769c 10-0 rei_farendblockerrorcounter 0 1 ... 83 0x0000 rei far-end block errors per one second interval table 155: tx lo ring port - general configuration (rw) address bit hw symbol index init description 0x18100 0x18102 ... 0x181a6 0 selectinterface 0 1 ... 83 0x0000 select per low order path the internal (0) or external (1) interface. 1 resetchannel resets an entire channel 2 extend_rdi use extended 3-bit rdi 0x18060 0 clockedge 0x0000 sets the rising (0) or the falling (1) edge of the clock as active edge 1 disableap disables the entire alarm indication port 0x18070 7-0 resetcounters 0x0800 reset the event counters 8 reserved reserved: this field must be false (0) for correct operation. 9 saturatecounters sets counters to either saturating or wrap-around 10 shadowregister_enable enables the performance counter mode with shadow counters 12-11 inteventctrl chooses when to latch the events or defects for interrupt: 00 - level controlled 01 - rising edge 10 - falling edge 11 - both edges 14-13 pm_eventctrl chooses when to latch the defects for pm/fm (disable pm/fm (00), rising edge (01), falling edge (10), both edges (11)) table 156: tx lo ring port - event latch (cow-1) address bit hw symbol init description 0x18080 0 crc_error_internal_li 0x0000 latch for interrupt signals for crc_error of both interface 1 crc_error_external_li table 157: tx lo ring port - performance counters (rw) address bit hw symbol init description 0x18020 15-0 pcrc_error_internal 0x0000 performance counter for crc errors of the internal ring port 0x18022 15-0 pcrc_error_external 0x0000 performance counter for crc errors of the external ring port table 158: tx lo ring port - performance counter shadow registers (ro) address bit hw symbol init description 0x18040 15-0 pcrc_error_internal 0x0000 performance counter for crc errors of the internal ring port 0x18042 15-0 pcrc_error_external 0x0000 performance counter for crc errors of the external ring port table 154: lo poh monitor - performance counter shadow registers (ro) address bit hw symbol index init description - 317 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 163 - configuration of the low order rx alarm indication (ring) port table 159: tx lo ring port - defects address bit hw symbol init description 0x180c0 0 cloc_internal 0x0000 defect correlations for the loc defects (ro) 1 cloc_external 0x180c2 0 loc_internal_li 0x0000 latch for interrupt signals for the loc defects (cow-1) 1 loc_external_li 0x180c4 0 loc_internal_lp 0x0000 latch for pm/fm signals for the loc defects (cow-0) 1 loc_external_lp 0x180c6 0 loc_internal_pm 0x0000 performance monitoring signals for the loc defects (ro) 1 loc_external_pm 0x180c8 0 loc_internal_fm 0x0000 fault monitoring signals for the loc defects (ro) 1 loc_external_fm table 160: tx lo ring port - interrupt mask (rw) address bit hw symbol init description 0x18090 0 crc_error_internal_m 0x0003 interrupt masks for the crc error latch for interrupt signals 1 crc_error_external_m 0x180a0 0 loc_internal_m 0x0003 interrupt masks for the loc latch for interrupt signals 1 loc_external_m table 161: tx lo ring port - event interrupt (ro) address bit hw symbol init description 0x180b0 0 generalinterrupt 0x0001 general interrupt signal for the tx lo alarm indication port table 162: tx lo ring port - defect interrupt (ro) address bit hw symbol init description 0x18000 0 generalinterrupt 0x0001 general interrupt signal for the tx lo alarm indication port table 163: rx lo ring port - configuration (rw) address bit hw symbol init description 0x1d7c0 0 insertcrcerror 0x0000 insert a crc error when a crc4 is calculated 0x1d7c2 0 clockedge 0x0000 sets the rising (0) or falling (1) edge as active edge - 318 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tables 164 through 166 - configuration and status of the general low order interrupt controller table 167 - configuration of the high order rx alarm indication (ring) port tables 168 through 176 - configuration, status and alarms of the high order tx alarm indication (ring) port table 164: lo interrupt controller - interrupts (ro) address bit hw symbol init description 0x1d2c4 0 txap_corrdefect_interrupt not applicable interrupt of the per channel defects coming from the tx alarm indi- cation port. default value: true 1 txap_event_interrupt interrupt of the per channel events coming from the tx alarm indica- tion port. default value: true 2 lodmp_poh_corrdefect_interrupt interrupt coming from the poh monitor of the lo demapper. default value: true 3 lodmp_ptr_corrdefect_interrupt interrupt coming from the ptr processor of the lo demapper. default value: true table 165: lo interrupt controller - interrupt masks (rw) address bit hw symbol init description 0x1d2c6 0 txap_corrdefect_interrupt 0x000f interrupt of the per channel defects coming from the tx alarm indica- tion port. default value: true 1 txap_event_interrupt interrupt of the per channel events coming from the tx alarm indica- tion port. default value: true 2 lodmp_poh_corrdefect_interrupt interrupt coming from the poh monitor of the lo demapper. default value: true 3 lodmp_ptr_corrdefect_interrupt interrupt coming from the ptr processor of the lo demapper. default value: true table 166: lo interrupt controller - summary (ro) address bit hw symbol init description 0x1d2c0 0 interrupt 0x0000 interrupt summary for the whole vtmapper block table 167: rx ho ring port - configuration (rw) address bit hw symbol init description 0x1d7d0 0 insertcrcerror 0x0000 insert a crc error when a crc4 is calculated 0x1d7d2 0 clockedge 0x0000 sets the rising (0) or falling (1) edge as active edge table 168: tx ho ring port - configuration (rw) address bit hw symbol index init description 0x19a00 0 clockedge 0x0000 sets the rising (0) or the falling (1) edge of the clock as active edge 0x19a02 0 disableap 0x0000 disables the entire alarm indication port 0x19a80 0x19a88 ... 0x19af8 0 selectinterface 0 1 ... 15 0x0000 select per high order path the internal (0) or external (1) interface. - 319 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x19a82 0x19a8a ... 0x19afa 0 resetchannel 0 1 ... 15 0x0000 resets an entire channel 0x19a84 0x19a8c ... 0x19afc 0 extend_rdi 0 1 ... 15 0x0000 use extended rdi table 169: tx ho ring port - counter configuration (rw) address bit hw symbol init description 0x19a30 7-0 resetcounters 0x0800 reset the event counters 8 reserved reserved: this field must be false (0) for correct operation. 9 saturatecounters sets counters to either saturating or wrap-around 10 shadowregister_enable enables the performance counter mode with shadow counters 12-11 inteventctrl chooses when to latch the events or defects for interrupt: 00 - level controlled 01 - rising edge 10 - falling edge 11 - both edges 14-13 pm_eventctrl chooses when to latch the defects for pm/fm (disable pm/fm (00), ris- ing edge (01), falling edge (10), both edges (11)) table 170: tx ho ring port - event latch (cow-1) address bit hw symbol init description 0x19a38 0 crc_error_internal_li 0x0000 latch for interrupt signals for crc_error of both interface 1 crc_error_external_li table 171: tx ho ring port - performance counters (rw) address bit hw symbol init description 0x19a10 15-0 pcrc_error_internal 0x0000 performance counter for crc errors of the internal ring port 0x19a12 15-0 pcrc_error_external 0x0000 performance counter for crc errors of the external ring port table 172: tx ho ring port - performance counter shadow registers (ro) address bit hw symbol init description 0x19a20 15-0 pcrc_error_internal 0x0000 performance counter for crc errors of the internal ring port 0x19a22 15-0 pcrc_error_external 0x0000 performance counter for crc errors of the external ring port table 173: tx ho ring port - defects address bit hw symbol init description 0x19a60 0 cloc_internal 0x0000 defect correlations for the loc defects (ro) 1 cloc_external 0x19a62 0 loc_internal_li 0x0000 latch for interrupt signals for the loc defects (cow-1) 1 loc_external_li table 168: tx ho ring port - configuration (rw) address bit hw symbol index init description - 320 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tables 177 through 209 - configuration, status and alarms of the high order poh monitor 0x19a64 0 loc_internal_lp 0x0000 latch for pm/fm signals for the loc defects (cow-0) 1 loc_external_lp 0x19a66 0 loc_internal_pm 0x0000 performance monitoring signals for the loc defects (ro) 1 loc_external_pm 0x19a68 0 loc_internal_fm 0x0000 fault monitoring signals for the loc defects (ro) 1 loc_external_fm table 174: tx ho ring port - interrupt mask (rw) address bit hw symbol init description 0x19a40 0 crc_error_internal_m 0x0003 interrupt masks for the crc error latch for interrupt signals 1 crc_error_external_m 0x19a48 0 loc_internal_m 0x0003 interrupt masks for the loc latch for interrupt signals 1 loc_external_m table 175: tx ho ring port - general interrupt (ro) address bit hw symbol init description 0x19a50 0 generalinterrupt 0x0001 general interrupt signal for the tx lo alarm indication port table 176: tx ho ring port - defect interrupt (ro) address bit hw symbol init description 0x19a58 0 generalinterrupt 0x0001 general interrupt signal for the tx lo alarm indication port table 177: ho poh monitor - received-64 byte trace message (ro) offset bit hw symbol index init description 0x00-0x7e (increments by 0x02) 7-0 bytevalue 0-63 0x0000 ram byte vc-4/sts-3c vc-3/sts-1 base address 0x1f780 0x1da00 table 173: tx ho ring port - defects address bit hw symbol init description - 321 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 178: ho poh monitor - received 16-byte trace message (ro) offset bit hw symbol index init description 0x00-0x1e (increments by 0x02) 7-0 bytevalue 0-15 0x0000 ram byte vc-4/sts-3c vc-3/sts-1 base address 0x1f6c0 0x1dc00 table 179: ho poh monitor - accepted bytes (ro) offset bit hw symbol index init description 0x00-0x7e (increments by 0x02) 7-0 bytevalue 0-63 0x0000 ram byte vc-4/sts-3c vc-3/sts-1 base address 0x1f400 0x1db00 table 180: ho poh monitor - expected j1 bytes (rw) offset bit hw symbol index init description 0x00-0x7e (increments by 0x02) 7-0 bytevalue 0-63 0x0000 ram byte vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f500 0x1de00 0x1de80 0x1df00 table 181: ho poh monitor - expected c2 bytes (rw) offset bit hw symbol init description 0 7-0 bytevalue 0x0000 ram byte vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f750 0x1dcb0 0x1dcb2 0x1dcb4 table 182: ho poh monitor - received poh bytes (ro) offset bit hw symbol init description 0 7-0 j1 0x0000 j1 byte of the previously received vc 2 7-0 b3 0x0000 b3 byte of the previously received vc 4 7-0 c2 0x0000 c2 byte of the previously received vc 6 7-0 g1 0x0000 g1 byte of the previously received vc - 322 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 8 7-0 f2 0x0000 f2 byte of the previously received vc a 7-0 h4 0x0000 h4 byte of the previously received vc c 7-0 f3 0x0000 f3/z3 byte of the previously received vc e 7-0 k3 0x0000 k3/z4 byte of the previously received vc 10 7-0 n1 0x0000 n1/z5 byte of the previously received vc vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f640 0x1d800 0x1d820 0x1d840 table 183: ho poh monitor - accepted poh bytes (ro) offset bit hw symbol init description 0 7-0 c2 0x0000 accepted c2 byte (debounced value) 2 7-0 k3 0x0000 accepted k3/z4 byte (debounced value) vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f738 0x1dc60 0x1dc64 0x1dc68 table 184: ho poh monitor - configuration (rw) offset bit hw symbol init description 0 2-0 pohmon_mode 0x0000 this field must be 0x0000 for correct vc-3 operation, and 0x0006 for correct vc-4 operation. 2 0 j1_report_enable 0x0000 enable j1 tti message reporting 2-1 j1_report_channel vc that is used for reporting j1. numbering starts at 00. example: for the first vc-3 you write '00' to bit 1 and 2 (and '1' to bit 0) vc-4/sts-3c vc-3/sts-1 base address 0x1f740 0x1dc40 table 185: ho poh monitor - loopback control (rw) address bit hw symbol init description 0x1f754 0 loopbackactive 0x0000 controls ethernet/local side loopback from add to drop telecom bus. default value: disabled (0). table 186: ho poh monitor - channel configuration (rw) offset bit hw symbol init description 0 0 unidirectional 0x0000 enables the unidirectional option. if the uni-directional option is active, the poh monitor reports farendblockerrorcounter = 0 and clear all received rdi defects. default value: false 1 bypass bypasses the channel. no action is done on the data flow. default value: false table 182: ho poh monitor - received poh bytes (ro) offset bit hw symbol init description - 323 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 2 0 j1_extimessage 0x01a8 selects between repeating non-specific byte (value: false) and other message formats (value: true). default value: false 1 j1_exti64 selects between 64-byte trace message (value: true) and 16-byte trace mes- sage (value: false). default value: false 2 j1_timenable enable tim detection. default value: false 6-3 j1_nrofframestosettim number of consecutive mismatched multiframes to set tim. default value: 5 10-7 j1_nrofframestoresettim number of consecutive matched multiframes to clear tim. default value: 3 4 6-0 j1_crc_seed 0x0000 crc seed value for the j1 crc check. default value: 0x0 7 j1_crcenable enables crc check. default value: false 63-0 j1_nrofframestosetstable64 0x0043 number of consecutive matched multiframes to set stable64. default value: 3 7-4 j1_nrofframestosetstable16 number of consecutive matched multiframes to set stable16. default value: 4 8 12-0 b3_setthreshold 0x0001 number of errored blocks that may occur in an interval to be considered as a bad interval. default value: 1 a 12-0 b3_clearthreshold 0x0001 number of errored blocks that may occur in an interval to be considered as a good interval. default value: 1 c 3-0 b3_setnrofintervals 0x0022 number of consecutive bad intervals to declare a degraded signal defect. default value: 2 7-4 b3_clearnrofintervals number of consecutive good intervals to clear the degraded signal defect. default value: 2 e 3-0 g1_acceptnrofintervals 0x0005 number of consecutive frames to debounce g1. default value: 5 10 1-0 h4_multiframetype 0x0014 type of h4_multiframe that the h4 finite state machine (fsm) looks for. default value: h4_mf_none (00). possible values: h4_mf_none (00), h4_mf_lo (01), h4_mf_vc (10) 5-2 h4_mstosetlom number of ms that the oom (oom1 or oom2) state must persist tot declare the lom defect. default value: 5 12 0 ais_ssf_disable 0x0000 disables ais insertion on ssf. default value: false 1 ais_tim_disable disables ais insertion due to the tim defect. default value: false 2 ais_incais_disable disables ais insertion due to incoming ais defect. default value: false 3 ais_uneq_disable disables ais insertion due to uneq defect. default value: false 4 tsf_tim_disable disables tsf action due to tim defect. default: false 5 tsf_incais_disable disables tsf action due to incoming ais defect. default value: false 6 tsf_uneq_disable disables tsf action due to uneq defect. default value: false 7 plm_plm_disable disables plm action due to plm defect. default value: false 8 rdi_ssf_disable disables rdi action due to ssf defect. default value: false 9 rdi_uneq_disable disables rdi action due to uneq defect. default value: false 10 rdi_tim_disable disables rdi action due to tim defect. default value: false 11 rdi_plm_disable disables rdi action due to plm defect. default value: false 12 lom_lom_disable disables lom action due to lom defect. default value: false 13 insertais software forced ais insertion. default value: false bits in register 0x14804 disable consequent actions when they are set to one. see mapper/demapper consequent actions per block beginning on page 390 for more details. in general, consequent actions should always be enabled. specifically, if the ssf, uneq, ais, lom or plm actions are disabled (bits 0,2,3,5,6,7 or 12 set to one), it is possible to obs erve sink side traffic loss during lcas deprovisioning. vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f680 0x1d900 0x1d920 0x1d940 table 186: ho poh monitor - channel configuration (rw) offset bit hw symbol init description - 324 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 187: ho poh monitor - channel status (ro) offset bit hw symbol init description 0 0 pohramwriteinsecondbank 0x0000 indicates if the received poh bytes are written into the second ram bank vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f758 0x1dcc0 0x1dcc2 0x1dcc4 table 188: ho poh monitor - channel defects (ro) offset bit hw symbol init description 0 0 ci_ssf 0x0000 incoming ssf defect 1 j1_tim tim defect 2 j1_ttizero ttizero defect 3 j1_crc crc defect 4 b3_deg degraded signal defect 5 c2_plm plm defect 6 c2_uneq uneq defect 7 c2_vc_ais incoming ais defect 8 g1_rdi incoming rdi defect 9 g1_rdi_s incoming server rdi defect 10 g1_rdi_c incoming connectivity rdi defect 11 g1_rdi_p incoming payload rdi defect 12 h4_lom lom defect vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f75c 0x1dcd0 0x1dcd2 0x1dcd4 table 189: ho poh monitor - j1 message status (ro) offset bit hw symbol init description 0 0 j1_stable_1 0x0000 indication that the j1 trail message contains a stable1 message 1 j1_stable_16 indication that the j1 trail message contains a stable16 message 2 j1_stable_64 indication that the j1 trail message contains a stable64 message vc-4/sts-3c vc-3/sts-1 base address 0x1f760 0x1dc50 - 325 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 190: ho poh monitor - defects (ro) offset bit hw symbol init description 0 0 ssf 0x0000 ssf correlated defect 1 tim tim correlated defect 2 ttizero ttizero correlated defect 3 crc crc correlated defect. 4 deg deg correlated defect. 5 plm plm correlated defect. 6 uneq uneq correlated defect. 7 incais incais correlated defect. 8 rdi rdi correlated defect. 9 rdi_s rdi_s correlated defect. 10 rdi_c rdi_c correlated defect. 11 rdi_p rdi_p correlated defect. 12 lom lom correlated defect. vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f764 0x1dce0 0x1dce2 0x1dce4 table 191: ho poh monitor - latched defects (r/cow-1) offset bit hw symbol init description 0 0 ssf 0x0000 ssf correlated defect 1 tim tim correlated defect 2 ttizero ttizero correlated defect 3 crc crc correlated defect. 4 deg deg correlated defect. 5 plm plm correlated defect. 6 uneq uneq correlated defect. 7 incais incais correlated defect. 8 rdi rdi correlated defect. 9 rdi_s rdi_s correlated defect. 10 rdi_c rdi_c correlated defect. 11 rdi_p rdi_p correlated defect. 12 lom lom correlated defect. vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f768 0x1dcf0 0x1dcf2 0x1dcf4 - 326 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 192: ho poh monitor - defect masks (rw) offset bit hw symbol init description 0 0 ssf 0x1fff mask setting for the ssf correlated defect. default value: true 1 tim mask setting for the tim correlated defect. default value: true 2 ttizero mask setting for the ttizero correlated defect. default value: true 3 crc mask setting for the crc correlated defect. default value: true 4 deg mask setting for the deg correlated defect. default value: true 5 plm mask setting for the plm correlated defect. default value: true 6 uneq mask setting for the uneq correlated defect. default value: true 7 incais mask setting for the incais correlated defect. default value: true 8 rdi mask setting for the rdi correlated defect. default value: true 9 rdi_s mask setting for the rdi_s correlated defect. default value: true 10 rdi_c mask setting for the rdi_c correlated defect. default value: true 11 rdi_p mask setting for the rdi_p correlated defect. default value: true 12 lom mask setting for the lom correlated defect. default value: true vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f76c 0x1dd00 0x1dd02 0x1dd04 table 193: ho poh monitor - defects latched for pmfm (r/cow-0) offset bit hw symbol init description 0 0 ssf 0x0000 ssf correlated defect 1 tim tim correlated defect 2 ttizero ttizero correlated defect 3 crc crc correlated defect. 4 deg deg correlated defect. 5 plm plm correlated defect. 6 uneq uneq correlated defect. 7 incais incais correlated defect. 8 rdi rdi correlated defect. 9 rdi_s rdi_s correlated defect. 10 rdi_c rdi_c correlated defect. 11 rdi_p rdi_p correlated defect. 12 lom lom correlated defect. vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f770 0x1dd10 0x1dd12 0x1dd14 - 327 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 194: ho poh monitor - defects pm (ro) offset bit hw symbol init description 0 0 ssf 0x0000 ssf correlated defect 1 tim tim correlated defect 2 ttizero ttizero correlated defect 3 crc crc correlated defect. 4 deg deg correlated defect. 5 plm plm correlated defect. 6 uneq uneq correlated defect. 7 incais incais correlated defect. 8 rdi rdi correlated defect. 9 rdi_s rdi_s correlated defect. 10 rdi_c rdi_c correlated defect. 11 rdi_p rdi_p correlated defect. 12 lom lom correlated defect. vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f774 0x1dd20 0x1dd22 0x1dd24 table 195: ho poh monitor - defects fm (ro) offset bit hw symbol init description 0 0 ssf 0x0000 ssf correlated defect 1 tim tim correlated defect 2 ttizero ttizero correlated defect 3 crc crc correlated defect. 4 deg deg correlated defect. 5 plm plm correlated defect. 6 uneq uneq correlated defect. 7 incais incais correlated defect. 8 rdi rdi correlated defect. 9 rdi_s rdi_s correlated defect. 10 rdi_c rdi_c correlated defect. 11 rdi_p rdi_p correlated defect. 12 lom lom correlated defect. vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f778 0x1dd30 0x1dd32 0x1dd34 - 328 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 196: ho poh monitor - defect configuration (rw) offset bit hw symbol init description 0 0 ssf_incais_disable 0x0000 disables the contribution of dc2_vc_ais to cssf. default value: false 1 uneq_ssf_inhibit_disable disables the inhibition of dc2_uneq by ci_ssf. default value: false 2 uneq_tim_disable disables the inhibition of dc2_uneq by dj1_tim. default value: false 3 uneq_ttizero_disable disables the inhibition of dc2_uneq by dj1_ttizero. default value: false 4 tim_ssf_inhibit_disable disables the inhibition of dj1_tim by ci_ssf. default value: false 5 tim_uneq_inhibit_disable disables the inhibition of dj1_tim by dc2_uneq. default value: false 6 tim_ttizero_inhibit_disable disables the inhibition of dj1_tim by dj1_ttizero. default value: false 7 ttizero_ssf_inhibit_disable disables the inhibition of dj1_ttizero by ci_ssf. default value: false 8 crc_ssf_inhibit_disable disables the inhibition of dj1_crc by ci_ssf. default value: false 9 crc_uneq_inhibit_disable disables the inhibition of dj1_crc by dc2_uneq. default value: false 10 crc_ttizero_inhibit_disable disables the inhibition of dj1_crc by dj1_ttizero. default value: false 11 deg_ssf_inhibit_disable disables the inhibition of db3_deg by ci_ssf. default value: false 12 deg_tim_inhibit_disable disables the inhibition of db3_deg by dj1_tim. default value: false 13 plm_tsf_inhibit_disable disables the inhibition of dc2_plm by ai_tsf. default value: false 2 0 rdi_ssf_inhibit_disable 0x0000 disables the inhibition of dg1_rdi, dg1_rdi_s, dg1_rdi_p and dg1_rdi_c by ci_ssf. default value: false 1 rdi_uneq_inhibit_disable disables the inhibition of dg1_rdi, dg1_rdi_s, dg1_rdi_p and dg1_rdi_c by dc2_uneq. default value: false 2 rdi_tim_inhibit_disable disables the inhibition of dg1_rdi, dg1_rdi_s, dg1_rdi_p and dg1_rdi_c by ci_ssf. default value: false 3 rdi_ttizero_inhibit_disable disables the inhibition of dg1_rdi, dg1_rdi_s, dg1_rdi_p and dg1_rdi_c by ci_ssf default value: false 4 lom_tsf_inhibit_disable disables the inhibition of dh4_lom by ai_tsf. default value: false 5 lom_plm_inhibit_disable disables the inhibition of dh4_lom by dc2_plm. default value: false vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f748 0x1dc80 0x1dc84 0x1dc88 table 197: ho poh monitor - defect summary (ro) offset bit hw symbol init description 0 0 latchforint 0x0000 per channel latch bit for interrupt summary 1 pm per channel pm summary 2 fm per channel fm summary vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f77c 0x1dd40 0x1dd42 0x1dd44 - 329 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 198: ho poh monitor - defect summary mask (rw) offset bit hw symbol init description 0 0 mask 0x0001 mask bit for the latch bit for interrupt summary per channel. default value: true vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f600 0x1dd50 0x1dd52 0x1dd54 table 199: ho poh monitor - defect group summary (ro) offset bit hw symbol init description 0 0 interrupt 0x0000 latch for interrupt summary for the per channel defects 2 0 pm 0x0000 pm summary for the per channel defects 4 0 fm 0x0000 fm summary for the per channel defects vc-4/sts-3c vc-3/sts-1 base address 0x1f700 0x1dd60 table 200: ho poh monitor - aps event (ro) offset bit hw symbol init description 0 0 k3_aps 0x0000 k3_aps event detected vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f608 0x1dd70 0x1dd72 0x1dd74 table 201: ho poh monitor - latched aps event (r/cow-1) offset bit hw symbol init description 0 0 k3_aps 0x0000 k3_aps event detected (latched) vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f610 0x1dd80 0x1dd82 0x1dd84 table 202: ho poh monitor - aps event mask (rw) offset bit hw symbol init description 0 0 k3_aps 0x0001 k3_aps event mask vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f618 0x1dd90 0x1dd92 0x1dd94 - 330 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 203: ho poh monitor - aps interrupt (ro) offset bit hw symbol init description 0 0 interrupt 0x0000 interrupt summary of the k3_aps event of all channels vc-4/sts-3c vc-3/sts-1 base address 0x1f620 0x1dc58 table 204: ho poh monitor - performance counters (rw) offset bit hw symbol init description 0 12-0 b3_nearendblockerrorcounter 0x0000 near end block error counter 2 15-0 g1_farendblockerrorcounter 0x0000 far end block error counter 4 15-0 b3_bip_errorcounter 0x0000 near end bip error counter vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f710 0x1ddc0 0x1ddc8 0x1ddd0 table 205: ho poh monitor - performance counters one second latch (ro) offset bit hw symbol init description 0 0 nds 0x0000 tsf one second latch 1 fds rdi one second latch vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f628 0x1dda0 0x1dda2 0x1dda4 table 206: ho poh monitor - performance counter shadow registers (ro) offset bit hw symbol init description 0 12-0 b3_nearendblockerrorcounter 0x0000 near end block error counter 2 15-0 g1_farendblockerrorcounter 0x0000 far end block error counter 4 15-0 b3_bip_errorcounter 0x0000 near end bip error counter vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f720 0x1dde0 0x1dde8 0x1ddf0 - 331 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 207: ho poh monitor - performance counter configuration (rw) offset bit hw symbol init description 0 0 g1_countblockerrorsnotbiterrors 0x0001 enables counting of block errors for the far end block error counters bit errors. default value: true vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1f630 0x1ddb0 0x1ddb2 0x1ddb4 table 208: ho poh monitor - counter reset (wo) offset bit hw symbol init description 0 7-0 resetcounters 0x0000 reset all performance counters of the block when 0x91 is written to this address. default value: 0x0 vc-4/sts-3c vc-3/sts-1 base address 0x1f638 0x1dca0 table 209: ho poh monitor - pmfm configuration (rw) offset bit hw symbol init description 0 0 reserved 0x0006 reserved: this field must be false (0) for correct operation. 1 shadowregister_enable enables the shadowing of the performance counters. default value: true 3-2 inteventcontrol interrupt latch condition. default value: int_rising_edge. possible values: int_level (00), int_rising_edge (01), int_falling_edge (10), int_both_edges (11) 5-4 pm_eventcontrol pm,fm latch condition. default value: pm_disabled. possible values: pm_disabled (00), pm_rising_edge (01), pm_falling_edge (10), pm_both_edges (11) vc-4/sts-3c vc-3/sts-1 base address 0x1f730 0x1dca8 - 332 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tables 210 through 222 - configuration, status and alarms of the tu-3 ptr tracker table 210: tu-3 ptr tracker - general configuration (rw) address bit hw symbol init description 0x19c00 0 reserved 0x000a reserved: this field must be false (0) for correct operation. 2-1 inteventcontrol configure on which transitions the interrupt latching occurs. default value: int_rising_edge. possible values: int_level (00), int_rising_edge (01), int_falling_edge (10), int_both_edges (11) 4-3 pmfmeventcontrol configure on which transitions the pm/fm latching occurs 00: pm/fm disabled 01: rising edge 10: falling edge 11: both edges 0x19c02 7-0 resetperfcounters 0x0000 reset all performance counters by writing 0x91 to this register table 211: tu-3 ptr tracker - per channel configuration (rw) address bit hw symbol index init description 0x19c80 0x19c90 0x19ca0 0 aug1_format 0 1 2 0x0001 timeslot belongs to either au-3 (0) or au-4 (1) a a. see ta b l e 1 , ? tu-3 pointer tracker/retimer modes, ? on page 96 1 tug3_format in au-4 mode, tug-3 either contains tu-3 (0) or tug-2 (1) b b. see ta b l e 1 , ? tu-3 pointer tracker/retimer modes, ? on page 96 0x19c82 0x19c92 0x19ca2 1-0 ss_reference 0 1 2 0x000e pointer interpreter fsm will expect these bits as ss-bits 2 ss_check_enable if enabled, received ss-bits are also checked by the pointer inter- preter fsm against the ss_reference bits 3 ais2lop_enable if enabled, ais to lop transition is possible 0x19c84 0x19c94 0x19ca4 0 insertais_on_plm_disable 0 1 2 0x0000 if false, ais will be inserted when plm is detected 1 insertais_on_lop_disable if false, ais will be inserted when lop is detected 2 insertais_on_ais_disable if false, ais will be inserted when ais is detected 3 insertais_on_tsf_disable if false, ais will be inserted when tsf is detected 4 ssf_on_plm_disable if false, ssf will be asserted when plm is detected 5 ssf_on_lop_disable if false, ssf will be asserted when lop is detected 6 ssf_on_ais_disable if false, ssf will be asserted when ais is detected 7 ssf_on_tsf_disable if false, ssf will be asserted when tsf is detected 0x19c86 0x19c96 0x19ca6 0 tsf_inhibits_ais 0 1 2 0x0007 if true, tsf inhibits generation of correlated ais defect 1 plm_inhibits_ais if true, plm inhibits generation of correlated ais defect 2 plm_inhibits_lop if true, plm inhibits generation of correlated lop defect 0x19c88 0x19c98 0x19ca8 0sw_insertais 0 1 2 0x0000 force ais insertion through software; only valid in au-4/vc-4/tug- 3/tu-3 format table 212: tu-3 ptr tracker - defects (ro) address bit hw symbol index init description 0x19c10 0x19c12 0x19c14 0 lossofpointer 0 1 2 0x0000 lossofpointer correlated defect 1 ais_detected ais correlated defect - 333 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 213: tu-3 ptr tracker - defects latched for interrupt (r/cow-1) address bit hw symbol index init description 0x19c20 0x19c22 0x19c24 0 lossofpointer 0 1 2 0x0000 lossofpointer correlated defect 1 ais_detected ais correlated defect table 214: tu-3 ptr tracker - defects latched for pmfm (r/cow-0) address bit hw symbol index init description 0x19c30 0x19c32 0x19c34 0 lossofpointer 0 1 2 0x0000 lossofpointer correlated defect 1 ais_detected ais correlated defect table 215: tu-3 ptr tracker - defects pm (ro) address bit hw symbol index init description 0x19c40 0x19c42 0x19c44 0 lossofpointer 0 1 2 0x0000 lossofpointer correlated defect 1 ais_detected ais correlated defect table 216: tu-3 ptr tracker - defects fm (ro) address bit hw symbol index init description 0x19c50 0x19c52 0x19c54 0 lossofpointer 0 1 2 0x0000 lossofpointer correlated defect 1 ais_detected ais correlated defect table 217: tu-3 ptr tracker - defect masks (rw) address bit hw symbol index init description 0x19c60 0x19c62 0x19c64 0 lossofpointer 0 1 2 0x0000 lossofpointer correlated defect 1 ais_detected ais correlated defect table 218: tu-3 ptr tracker - defect summary (ro) address bit hw symbol init description 0x19c70 2-0 latchforint 0x0000 per channel latched for interrupt defect summary 0x19c72 2-0 pm 0x0000 per channel performance monitoring defect summary 0x19c74 2-0 fm 0x0000 per channel fault monitoring defect summary table 219: tu-3 ptr tracker - defect summary mask (rw) address bit hw symbol init description 0x19cc0 2-0 latchforint not applicable per channel latched for interrupt defect summary 0x19cc2 2-0 pm per channel performance monitoring defect summary 0x19cc4 2-0 fm per channel fault monitoring defect summary table 220: tu-3 ptr tracker - defect group summary (ro) address bit hw symbol init description 0x19cd0 0 interrupt 0x0000 latched for interrupt defect summary - 334 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tables 223 and 224 - configuration of tu-3 cross connect 0x19cd2 0 pm 0x0000 performance monitoring defect summary 0x19cd4 0 fm 0x0000 fault monitoring defect summary table 221: tu-3 ptr tracker - performance counters (rw) address bit hw symbol index init description 0x19ce0 0x19ce4 0x19ce8 7-0 negjustcount 0 1 2 0x0000 raw count of incoming tu-3 pointer negative justifications (decre- ments) 0x19ce2 0x19ce6 0x19cea 7-0 posjustcount 0 1 2 0x0000 raw count of incoming tu-3 pointer positive justifications (increments) table 222: tu-3 ptr tracker - performance counter shadow registers (ro) address bit hw symbol index init description 0x19cf0 0x19cf4 0x19cf8 7-0 negjustcount 0 1 2 0x0000 one second count of incoming tu-3 pointer negative justifications (decrements) 0x19cf2 0x19cf6 0x19cfa 7-0 posjustcount 0 1 2 0x0000 one second count of incoming tu-3 pointer positive justifications (increments) table 223: transmit vc-3/sts-1/tug-3 time slot interchange (rw) address bit hw symbol index init description 0x1d700 0x1d708 0x1d710 1-0 sourceslot 0 1 2 0x0000 selection of the source timeslot for this output timeslot. range: 0 to 2. default value: 0 0x1d702 0x1d70a 0x1d712 1-0 sourcebus 0 1 2 0x0000 selection of the source bus for this output timeslot. default value: 0 0x1d704 0x1d70c 0x1d714 0 forceuneq 0 1 2 0x0001 force unequipped on this output timeslot. default value: true 0x1d706 0x1d70e 0x1d716 0forceais 0 1 2 0x0000 force ais on this output timeslot. default value: false table 224: receive vc-3/sts-1/tug-3 time slot interchange (rw) address bit hw symbol index init description 0x1d720 0x1d728 0x1d730 1-0 sourceslot 0 1 2 0x0000 selection of the source timeslot for this output timeslot. range 0 to 2. default value: 0 0x1d722 0x1d72a 0x1d732 1-0 sourcebus 0 1 2 0x0000 selection of the source bus for this output timeslot: 0x0001 selects the bus from the level 3 retimer, 0x0002 selects the not substructured vc-4 bypass. table 220: tu-3 ptr tracker - defect group summary (ro) address bit hw symbol init description - 335 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tables 225 through 237 - configuration, status and alarms of the tu-3 ptr generator 0x1d724 0x1d72c 0x1d734 0 forceuneq 0 1 2 0x0001 force unequipped on this output timeslot. default value: true 0x1d726 0x1d72e 0x1d736 0forceais 0 1 2 0x0000 force ais on this output timeslot. default value: false table 225: tu-3 ptr generator - general configuration (rw) address bit hw symbol init description 0x19e40 0 reserved 0x000a reserved: this field must be false (0) for correct operation. 2-1 inteventcontrol configure on which transitions the interrupt latching occurs. default value: int_rising_edge. possible values: int_level (00), int_rising_edge (01), int_falling_edge (10), int_both_edges (11) 4-3 pmfmeventcontrol configure on which transitions the pm/fm latching occurs 00: pm/fm disabled 01: rising edge 10: falling edge 11: both edges 0x19e42 7-0 resetperfcounters 0x0000 reset all performance counters by writing 0x91 to this register 0x19e44 9-0 au4_fixedpointer 0x0000 set au-4 pointer used in au3_to_au4 mode table 226: tu-3 ptr generator - per channel configuration (rw) address bit hw symbol index init description 0x19ee0 0x19ee8 0x19ef0 2-0 conversiontype 0 0x0000 configure mapping per vc-3/sts-1/tug-3 time slot. a a. see ta b l e 2 , ? tu-3 pointer generator modes, ? on page 96 0x19ee2 0x19eea 0x19ef2 1-0 ss_reference 0 0x0002 use this reference to fill in ss bits in tu-3 pointer 0x19ee4 0x19eec 0x19ef4 0 insertais_on_fifoerror_disable 0 0x0000 disable ais insertion when fifo error is detected 1 insertais_on_ssf_disable disable ais insertion when incoming ssf is detected 0x19ee6 0x19eee 0x19ef6 0 sw_insertais 0 0x0000 force ais insertion through software table 227: tu-3 ptr generator - defects (ro) address bit hw symbol sw symbol index init description 0x19e50 0x19e52 0x19e54 0 fifoerror defects 0 1 2 0x0000 fifo over- or underflow has occurred table 224: receive vc-3/sts-1/tug-3 time slot interchange (rw) address bit hw symbol index init description - 336 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 228: tu-3 ptr generator - defects latched for interrupt (r/cow-1) address bit hw symbol index init description 0x19e60 0x19e62 0x19e64 0 fifoerror 0 1 2 0x0000 fifo over- or underflow has occurred table 229: tu-3 ptr generator - defects latched for pmfm (r/cow-0) address bit hw symbol index init description 0x19e70 0x19e72 0x19e74 0 fifoerror 0 1 2 0x0000 fifo over- or underflow has occurred table 230: tu-3 ptr generator - defects pm (ro) address bit hw symbol index init description 0x19e80 0x19e82 0x19e84 0 fifoerror 0 1 2 0x0000 fifo over- or underflow has occurred table 231: tu-3 ptr generator - defects fm (ro) address bit hw symbol index init description 0x19e90 0x19e92 0x19e94 0 fifoerror 0 1 2 0x0000 fifo over- or underflow has occurred table 232: tu-3 ptr generator - defect mask (rw) address bit hw symbol index init description 0x19ea0 0x19ea2 0x19ea4 0 fifoerror 0 1 2 0x0000 fifo over- or underflow has occurred table 233: tu-3 ptr generator - defect summary (ro) address bit hw symbol init description 0x19eb0 2-0 latchforint 0x0000 per channel latched for interrupt defect summary 0x19eb2 2-0 pm 0x0000 per channel performance monitoring defect summary 0x19eb4 2-0 fm 0x0000 per channel fault monitoring defect summary table 234: tu-3 ptr generator - defect summary mask (rw) address bit hw symbol init description 0x19ec0 2-0 latchforint not applicable per channel latched for interrupt defect summary 0x19ec2 2-0 pm per channel performance monitoring defect summary 0x19ec4 2-0 fm per channel fault monitoring defect summary table 235: tu-3 ptr generator - defect group summary (ro) address bit hw symbol init description 0x19ed0 0 interrupt 0x0000 latched for interrupt defect summary - 337 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tables 238 through 242 - configuration of high order (vc-3 and vc-4) poh generator 0x19ed2 0 pm 0x0000 performance monitoring defect summary 0x19ed4 0 fm 0x0000 fault monitoring defect summary table 236: tu-3 ptr generator - performance counters (rw) address bit hw symbol index init description 0x19e00 0x19e04 0x19e08 7-0 negjustcount 0 1 2 0x0000 count of outgoing tu-3 pointer negative justifications (decrements) 0x19e02 0x19e06 0x19e0a 7-0 posjustcount 0 1 2 0x0000 count of outgoing tu-3 pointer positive justifications (increments) table 237: tu-3 ptr generator - performance counter shadow registers (ro) address bit hw symbol index init description 0x19e20 0x19e24 0x19e28 7-0 negjustcount 0 1 2 0x0000 count of outgoing tu-3 pointer negative justifications (decrements) 0x19e22 0x19e26 0x19e2a 7-0 posjustcount 0 1 2 0x0000 count of outgoing tu-3 pointer positive justifications (increments) table 238: ho poh generator - channel control (rw) offset bit hw symbol init description 0 0 forceais 0x0000 forces insertion of ais in the corresponding channel 1 forceuneq forces insertion of unequipped in the corresponding channel 2 forcesupuneq forces insertion of supervisory unequipped in the corresponding channel 3 passpoh when set the incoming channel is passed untouched vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1d058 0x1f960 0x1f962 0x1f964 table 235: tu-3 ptr generator - defect group summary (ro) address bit hw symbol init description - 338 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 239: ho poh generator - configuration (rw) offset bit hw symbol init description 0 0 j1_length64 0x0000 when set the length of the tti message inserted in j1 is 64 bytes 1 b3_masking when set the b3 byte is masked with the value in the poh ram 2 g1_unidirectional when set the unidirectional option is activated 3 onebitrdi when set the rdi is encoded in 1 bit 5-4 g1_rei_control select the source of the g1 rei, poh ram (00=default), poh port (01) or alarm indica- tion port (10) 7-6 g1_rdi_control select the source of the g1 rdi, poh ram (00=default), poh port (01) or alarm indica- tion port (10) 8 g1_spare_control select the source of the g1 spare bit, poh ram (0=default) or poh port (1) 9 f2_control select the source of the f2 byte, poh ram (0=default) or poh port (1) 11-10 h4_control select the source of the h4 byte, poh ram (00=default), poh port (01), pass through (10), or generate (11). 12 f3_control select the source of the f3/z3 byte, poh ram (0=default) or poh port (1) 13 k3_control select the source of the k3/z4 byte, poh ram (0=default) or poh port (1) 14 n1_control select the source of the n1/z5 byte, poh ram (0=default) or poh port (1) vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1d040 0x1f900 0x1f902 0x1f904 table 240: ho poh generator - j1 message bytes (rw) offset bit hw symbol index init description 0x00-0x7e (increment by 0x02) 7-0 value 0-63 0x0000 tti-message byte for insertion in the j1 location vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1d080 0x1fa00 0x1fa80 0x1fb00 table 241: ho poh generator - poh insertion values (rw) offset bit hw symbol init description 0 7-0 b3 0x0000 mask used on the b3 byte if b3_masking is enabled. 2 7-0 c2 0x0000 signal label to be inserted. 4 7-0 g1 0x0000 value used when g1 is inserted out of ram 6 7-0 f2 0x0000 value used when f2 is inserted out of ram 8 7-0 h4 0x0000 value used when h4 is inserted out of ram a 7-0 f3 0x0000 value used when f3/z3 is inserted out of ram c 7-0 k3 0x0000 value used when k3/z4 is inserted out of ram e 7-0 n1 0x0000 value used when n1/z5 is inserted out of ram vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1d000 0x1f800 0x1f810 0x1f820 - 339 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tables 243 through 250 - configuration, status and alarms of the tu-3 retimer table 242: ho poh generator - poh port monitors (ro) offset bit hw symbol init description 0 7-0 g1 0x0000 value received from the poh port for insertion in g1 2 7-0 f2 0x0000 value received from the poh port for insertion in f2 4 7-0 h4 0x0000 value received from the poh port for insertion in h4 6 7-0 f3 0x0000 value received from the poh port for insertion in f3/z3 8 7-0 k3 0x0000 value received from the poh port for insertion in k3/z4 a 7-0 n1 0x0000 value received from the poh port for insertion in n1/z5 vc-4/sts-3c vc-3/sts-1 #1 vc-3/sts-1 #2 vc-3/sts-1 #3 base address 0x1d060 0x1f980 0x1f990 0x1f9a0 table 243: tu-3 retimer - general configuration (rw) address bit hw symbol init description 0x1e5a0 0 reserved 0x0002 reserved: this field must be false (0) for correct operation. 2-1 inteventcontrol configure on which transitions latching for interrupt occurs. default value: int_rising_edge. possible values: int_level (00), int_rising_edge (01), int_falling_edge (10), int_both_edges (11) 0x1e5a2 0 disablesequencer 0x0001 turn off sequencer (for instance when writing to program ram) 0x1e5a4 11-0 frameoffset 0x0000 configure offset of frame start to framerefpulse. set to 0x97d. table 244: tu-3 retimer - per channel configuration (rw) address bit hw symbol index init description 0x1e5c0 0x1e5c4 0x1e5c8 0 insertais_on_fifoerror_disable 0 1 2 0x0000 disable ais insertion when fifo error is detected 1 insertais_on_ssf_disable disable ais insertion when incoming ssf is detected 0x1e5c2 0x1e5c6 0x1e5ca 0sw_insertais 0 1 2 0x0000 force ais insertion through software table 245: tu-3 retimer - defects (ro) address bit hw symbol index init description 0x1e400 0x1e402 0x1e404 0 fifoerror 0 1 2 0x0000 fifo over- or underflow has occurred table 246: tu-3 retimer - defects latched for interrupt (r/cow-1) address bit hw symbol index init description 0x1e440 0x1e442 0x1e444 0 fifoerror 0 1 2 0x0000 fifo over- or underflow has occurred - 340 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 247: tu-3 retimer - defect masks (rw) address bit hw symbol index init description 0x1e480 0x1e482 0x1e484 0 fifoerror 0 1 2 0x0000 fifo over- or underflow has occurred table 248: tu-3 retimer - defect group summary (ro) address bit hw symbol init description 0x1e580 0 interrupt 0x0000 summary of defects table 249: tu-3 retimer - sequencer configuration (rw) address bit hw symbol index init description 0x1e500 0x1e504 ... 0x1e510 0 const(1) 0 1 ... 4 0x0000 constants which are used in sequencer calculations 0x1e502 0x1e506 ... 0x1e512 15-0 const(0) 0 1 ... 4 0x0000 constants which are used in sequencer calculations 0x1e4c0 0x1e4c4 0 const(1) 0 1 0x0000 constants which are used in sequencer calculations 0x1e4c2 0x1e4c6 15-0 const(0) 0 1 0x0000 constants which are used in sequencer calculations 0x1e4c0 0x1e4c4 0 const(1) 0 1 0x0000 constants which are used in sequencer calculations 0x1e4c2 0x1e4c6 15-0 const(0) 0 1 0x0000 constants which are used in sequencer calculations 0x1e600 0x1e602 ... 0x1e7fe 15-0 instructionword 0 1 ... 255 0x0000 instruction word for sequencer program ram table 250: tu-3 retimer - sequencer data (rw) address bit hw symbol index init description 0x1e000 0x1e004 ... 0x1e3fc 9-0 dataword_msb 0 1 ... 255 0x0000 msb of dataword from sequencer data ram 0x1e002 0x1e006 ... 0x1e3fe 15-0 dataword_lsb 0 1 ... 255 0x0000 lsb of dataword from sequencer data ram - 341 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tables 251 through 258 - configuration, status and alarms of the au-3/4 retimer table 251: au-3/4 retimer - general configuration (rw) address bit hw symbol init description 0x1d438 0 reserved 0x0002 reserved: this field must be false (0) for correct operation. 2-1 inteventcontrol configure on which transitions latching for interrupt occurs. default value: int_rising_edge. possible values: int_level (00), int_rising_edge (01), int_falling_edge (10), int_both_edges (11) 0x1d43a 11-0 frameoffset 0x0000 configure offset of frame start to framerefpulse. set to 0x97a. table 252: au-3/4 retimer - per channel configuration (rw) address bit hw symbol index init description 0x1d440 0x1d448 0x1d450 0 aug1_format 0 1 2 0x0001 timeslot belongs to either au-3 (0) or au-4 (1) 0x1d442 0x1d44a 0x1d452 0 insertais_on_fifoerror_disable 0 1 2 0x0000 disable ais insertion when fifo error is detected 1 insertais_on_ssf_disable disable ais insertion when incoming ssf is detected 0x1d444 0x1d44c 0x1d454 0sw_insertais 0 1 2 0x0000 force ais insertion through software 0x1d446 0x1d44e 0x1d456 0 justcountreset 0 1 2 0x0000 reset pos/negjustcount for this channel table 253: au-3/4 retimer - defects (ro) address bit hw symbol index init description 0x1d400 0x1d402 0x1d404 0 fifoerror 0 1 2 0x0000 fifo over- or underflow has occurred table 254: au-3/4 retimer - defects latched for interrupt (r/cow-1) address bit hw symbol index init description 0x1d410 0x1d412 0x1d414 0 fifoerror 0 1 2 0x0000 fifo over- or underflow has occurred table 255: au-3/4 retimer - defect masks (rw) address bit hw symbol index init description 0x1d420 0x1d422 0x1d424 0 fifoerror 0 1 2 0x0000 fifo over- or underflow has occurred table 256: au-3/4 retimer - defect group summary (ro) address bit hw symbol init description 0x1d430 0 interrupt 0x0000 latched for interrupt defect summary - 342 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tables 259 through 261 - configuration and status of the general high order interrupt controller table 257: au-3/4 retimer - ptr leak reset value (rw) address bit hw symbol index init description 0x1d460 0x1d464 0x1d468 15-0 slowleakresetvalue 0 1 2 0x0000 reset value of counter determining outgoing pointer movement spacing while the fifodepth is in the slow leak zone. a unit corresponds to two frames 0x1d462 0x1d466 0x1d46a 15-0 fastleakresetvalue 0 1 2 0x0000 reset value of counter determining outgoing pointer movement spacing while the fifodepth is in the fast leak zone. a unit corresponds to two frames table 258: au-3/4 retimer - performance counters (ro) address bit hw symbol index init description 0x1d470 0x1d474 0x1d478 15-0 posjustcount 0 1 2 0x0000 count of outgoing (generated) positive pointer movements (increments) 0x1d472 0x1d476 0x1d47a 15-0 negjustcount 0 1 2 0x0000 count of outgoing (generated) negative pointer movements (decrements) table 259: ho interrupt controller - interrupts (ro) address bit hw symbol init description 0x1d2e4 0 r4poh_event_interrupt not applicable interrupt of the per channel events coming from the rx_vc4_poh monitor. default value: true 1 r4poh_corrdefect_interrupt interrupt of the per channel defects coming from the rx_vc4_poh monitor. default value: true 2 r3poh_event_interrupt interrupt of the per channel events coming from the rx_vc3_poh monitor. default value: true 3 r3poh_corrdefect_interrupt interrupt of the per channel defects coming from the rx_vc3_poh monitor. default value: true 4 rtu3_corrdefect_interrupt interrupt of the per channel defects coming from the rx_tu3_ptr. default value: true 5 l3rtm_corrdefect_interrupt interrupt of the per channel defects coming from the l3rtm default value: true 6 txap_corrdefect_interrupt interrupt of the per channel defects coming from the tx alarm indication port default value: true 7 txap_event_interrupt interrupt of the per channel events coming from the tx alarm indication port default value: true 8 ttu3_corrdefect_interrupt interrupt of the per channel defects coming from the tx_tu3_ptr default value: true 9 aurtm_corrdefect_interrupt interrupt of the per channel defects coming from the au retimer default value: true - 343 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tables 262 through 280 - configuration, status and alarms of the rx combus interface table 260: ho interrupt controller - interrupt masks (rw) address bit hw symbol init description 0x1d2e6 0 r4poh_event_interrupt 0x03ff interrupt of the per channel events coming from the rx_vc4_poh monitor. default value: true 1 r4poh_corrdefect_interrupt interrupt of the per channel defects coming from the rx_vc4_poh monitor. default value: true 2 r3poh_event_interrupt interrupt of the per channel events coming from the rx_vc3_poh monitor. default value: true 3 r3poh_corrdefect_interrupt interrupt of the per channel defects coming from the rx_vc3_poh monitor. default value: true 4 rtu3_corrdefect_interrupt interrupt of the per channel defects coming from the rx_tu3_ptr. default value: true 5 l3rtm_corrdefect_interrupt interrupt of the per channel defects coming from the l3rtm default value: true 6 txap_corrdefect_interrupt interrupt of the per channel defects coming from the tx alarm indication port default value: true 7 txap_event_interrupt interrupt of the per channel events coming from the tx alarm indication port default value: true 8 ttu3_corrdefect_interrupt interrupt of the per channel defects coming from the tx_tu3_ptr default value: true 9 aurtm_corrdefect_interrupt interrupt of the per channel defects coming from the au retimer default value: true table 261: ho interrupt controller - interrupt group summary (ro) address bit hw symbol init description 0x1d2e0 0 interrupt 0x0000 interrupt summary for the whole c3_to_aug1 block table 262: rx combus interface - general configuration (rw) address bit hw symbol init description 0x1d578 0 reserved not applicable reserved: this field must be false (0) for correct operation. 2-1 inteventcontrol configure on which transitions latching for interrupt occurs. default value: int_rising_edge. possible values: int_level (00), int_rising_edge (01), int_falling_edge (10), int_both_edges (11) 4-3 pmfmeventcontrol configure on which transitions latching for pm/fm occurs 00: pm/fm disabled 01: rising edge 10: falling edge 11: both edges 5 activeedge select the edge on which data and timing from the combus are sampled: falling (1) or rising (0) edge. the rising edge is default. 9-6 timingdelay configure expected delay between timing and data on combus 0x1d57a 0 parityeven 0x0000 if true, parity is assumed to be even; else it is assumed to be odd 1 paritymode parity is calculated either over data only (0), or over data and timing (1) - 344 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 263: rx combus interface - per channel configuration (rw) address bit hw symbol index init description 0x1d510 0x1d514 0x1d518 0 au_mode 0 1 2 0x0000 select au-4 (1) or au-3 (0) format 0x1d512 0x1d516 0x1d51a 0 v1_pulsepresent 0 1 2 0x0001 indicates if v1-pulse is present on the combus table 264: rx combus interface - per channel status (ro) address bit hw symbol index init description 0x1d520 0x1d522 0x1d524 7-0 h1_byte 0 1 2 0x0000 received au-level h1 pointer byte 15-8 h2_byte received au-level h2 pointer byte table 265: rx combus interface - defects (ro) address bit hw symbol init description 0x1d57c 0 c1_lossofframe 0x0000 loss of frame in c1 locking fsm. recovery can take from 6 to 15 frames after any offending alarms clear. 1 parityerror parity error detected table 266: rx combus interface - defects latched for interrupt (r/cow-1) address bit hw symbol init description 0x1d57e 0 c1_lossofframe 0x0000 loss of frame in c1 locking fsm. recovery can take from 6 to 15 frames after any offending alarms clear. 1 parityerror parity error detected table 267: rx combus interface - defects latched for pmfm (r/cow-0) address bit hw symbol init description 0x1d500 0 c1_lossofframe 0x0000 loss of frame in c1 locking fsm. recovery can take from 6 to 15 frames after any offending alarms clear. 1 parityerror parity error detected table 268: rx combus interface - defects pm (ro) address bit hw symbol init description 0x1d504 0 c1_lossofframe 0x0000 loss of frame in c1 locking fsm. recovery can take from 6 to 15 frames after any offending alarms clear. 1 parityerror parity error detected table 269: rx combus interface - defects fm (ro) address bit hw symbol init description 0x1d508 0 c1_lossofframe 0x0000 loss of frame in c1 locking fsm. recovery can take from 6 to 15 frames after any offending alarms clear. 1 parityerror parity error detected - 345 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 270: rx combus interface - defect masks (rw) address bit hw symbol init description 0x1d50c 0 c1_lossofframe 0x0000 loss of frame in c1 locking fsm 1 parityerror parity error detected table 271: rx combus interface - defect group summary (ro) address bit hw symbol init description 0x1d528 0 interrupt 0x0000 latched for interrupt defect summary 0x1d52a 0 pm 0x0000 performance monitoring defect summary 0x1d52c 0 fm 0x0000 fault monitoring defect summary table 272: rx combus interface - per channel defects (ro) address bit hw symbol index init description 0x1d530 0x1d532 0x1d534 0 j1_lossofframe 0 1 2 0x0000 loss of frame in j1 locking fsm 1 v1_lossofframe loss of frame in v1 locking fsm 2 ais_detected ais detected through monitoring of au h1/h2 pointer bytes table 273: rx combus interface - per channel defects latched for interrupt (r/cow-1) address bit hw symbol index init description 0x1d538 0x1d53a 0x1d53c 0 j1_lossofframe 0 1 2 0x0000 loss of frame in j1 locking fsm 1 v1_lossofframe loss of frame in v1 locking fsm 2 ais_detected ais detected through monitoring of au h1/h2 pointer bytes table 274: rx combus interface - per channel defects latched for pmfm (r/cow-0) address bit hw symbol index init description 0x1d540 0x1d542 0x1d544 0 j1_lossofframe 0 1 2 0x0000 loss of frame in j1 locking fsm 1 v1_lossofframe loss of frame in v1 locking fsm 2 ais_detected ais detected through monitoring of au h1/h2 pointer bytes table 275: rx combus interface - per channel defects pm (ro) address bit hw symbol index init description 0x1d548 0x1d54a 0x1d54c 0 j1_lossofframe 0 1 2 0x0000 loss of frame in j1 locking fsm 1 v1_lossofframe loss of frame in v1 locking fsm 2 ais_detected ais detected through monitoring of au h1/h2 pointer bytes table 276: rx combus interface - per channel defects fm (ro) address bit hw symbol index init description 0x1d550 0x1d552 0x1d554 0 j1_lossofframe 0 1 2 0x0000 loss of frame in j1 locking fsm 1 v1_lossofframe loss of frame in v1 locking fsm 2 ais_detected ais detected through monitoring of au h1/h2 pointer bytes - 346 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 277: rx combus interface - per channel defect masks (rw) address bit hw symbol index init description 0x1d558 0x1d55a 0x1d55c 0 j1_lossofframe 0 1 2 0x0000 loss of frame in j1 locking fsm 1 v1_lossofframe loss of frame in v1 locking fsm 2 ais_detected ais detected through monitoring of au h1/h2 pointer bytes table 278: rx combus interface - per channel defect summary (ro) address bit hw symbol init description 0x1d560 2-0 latchforint 0x0000 per channel latched for interrupt defect summary 0x1d562 2-0 pm 0x0000 per channel performance monitoring defect summary 0x1d564 2-0 fm 0x0000 per channel fault monitoring defect summary table 279: rx combus interface - per channel defect summary masks (rw) address bit hw symbol init description 0x1d568 2-0 latchforint 0x0000 per channel latched for interrupt defect summary 0x1d56a 2-0 pm 0x0000 per channel performance monitoring defect summary 0x1d56c 2-0 fm 0x0000 per channel fault monitoring defect summary table 280: rx combus interface - per channel defect group summary (ro) address bit hw symbol init description 0x1d570 0 interrupt 0x0000 latched for interrupt defect summary 0x1d572 0 pm 0x0000 performance monitoring defect summary 0x1d574 0 fm 0x0000 fault monitoring defect summary - 347 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tables 281 through 302 - configuration, status and alarms of the tx combus interface table 281: tx combus interface - general configuration (rw) address bit hw symbol init description 0x184c8 0 reserved 0x48a2 reserved: this field must be false (0) for correct operation. 2-1 inteventcontrol interrupt latch condition. default value: int_rising_edge. possible values: int_level (00), int_rising_edge (01), int_falling_edge (10), int_both_edges (11) 4-3 pmfmeventcontrol pm/fm latch condition. default value: pm_disabled (00). possible values: pm_disabled (00), pm_rising_edge (01), pm_falling_edge (10), pm_both_edges (11) 5 activeedge select active edge of the timing on the combus: this control is used in: a) add bus timing slave. the inputs ac1j1v1 and aspe are sampled on the falling edge of aclk (bit set to '1') or rising edge (bit set to '0'). b) drop bus timing. the inputs dc1j1v1 and dspe are sampled on the falling edge of dclk (bit set to '1') or rising edge (bit set to '0'). the falling edge is default active. 6 loopbackactive controls sonet/sdh line side loopback from drop to add telecom bus. default value: disabled (0). 10-7 timingdelay timing delay: delay between timing and data on the combus. default value: 1. possible values: 0 .. 15 11 addind_actlow this bit must always be written with a 1. 12 paritymode parity mode of the calculated parity. the parity can be calculated over the data only (0) or in timing source mode over the data and the spe and c1j1v1 timing signals (1). default value is data only. 13 parityeven indication whether the calculated parity is even. default value: false 14 c1_lof_highz setting to enable tristating the bus during c1_lof. default value: true table 282: tx combus interface - aug1 configuration (rw) address bit hw symbol index init description 0x184cc 0 au_mode 0 0x0000 selects the au mode of this aug1 on the combus: au-3 (0) or au-4 (1). default value is au-3. table 283: tx combus interface - au-3 configuration (rw) address bit hw symbol index init description 0x184e8 0x184ea 0x184ec 0 j1_lof_highz 0 1 2 0x003f enable tristating the bus during j1_lof. for au-4, this must be set for every au-3. default value: true 1 v1_lof_highz enable tristating the bus during v1_lof. for au-4, this must be set for every au-3. default value: true 2 fifoerror_highz enable tristating the bus during fifoerror. for au-4, this must be set for every au-3. default value: true 3 highz_au3 tristate forcing of the au-3. for au-4, this must be set for every au-3. default value: true ( see ? telecom bus tributary activation/tri-state control ? on page 191 ) 4 highz_tug3 tristate forcing of the tug-3. default value: true ( see ? telecom bus tribu- tary activation/tri-state control ? on page 191 ) 5 v1_pulsepresent indicates if the v1 pulse is present on the combus - 348 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 284: tx combus interface - tug-2 configuration (rw) address bit hw symbol index init description 0x18480 0x18482 ... 0x184a8 0istu12 0 1 ... 20 0x0002 indication if the tug-2 contains tu-11 containers. default value: false. when true, the tug-2 contains tu-12 containers 1 highz tristate setting of the tug-2. default value: true ( see ? telecom bus trib- utary activation/tri-state control ? on page 191 ) table 285: tx combus interface - tu-11/tu-12 configuration (rw) address bit hw symbol index init description 0x18500 0x18502 ... 0x185a6 0 highz 0 1 ... 83 0x0001 tristate setting for the tu-11/tu-12. default value: true ( see ? te l e c o m bus tributary activation/tri-state control ? on page 191 ) table 286: tx combus interface - defects (ro) address bit hw symbol init description 0x184d0 0 c1_lossofframe not applicable c1_lossofframe alarm for the c1 locking fsm table 287: tx combus interface - defects latched for interrupt (r/cow-1) address bit hw symbol init description 0x184d4 0 c1_lossofframe not applicable c1_lossofframe alarm for the c1 locking fsm. recovery can occur 6 to 15 frames after any offending alarms are cleared up. table 288: tx combus interface - defect masks (rw) address bit hw symbol init description 0x184d8 0 c1_lossofframe not applicable c1_lossofframe alarm for the c1 locking fsm table 289: tx combus interface - defects latched for pmfm (r/cow-0) address bit hw symbol init description 0x184dc 0 c1_lossofframe 0x0000 c1_lossofframe alarm for the c1 locking fsm. recovery can occur 6 to 15 frames after any offending alarms are cleared up. table 290: tx combus interface - defects pm (ro) address bit hw symbol init description 0x184e0 0 c1_lossofframe see note c1_lossofframe alarm for the c1 locking fsm. recovery can occur 6 to 15 frames after any offending alarms are cleared up. note: if onesec is not present then the initial value is 0x0000. if onesec is present, then the initial value is 0x0001. table 291: tx combus interface - defects fm (ro) address bit hw symbol init description 0x184e4 0 c1_lossofframe see note c1_lossofframe alarm for the c1 locking fsm. recovery can occur 6 to 15 frames after any offending alarms are cleared up. note: if onesec is not present then the initial value is 0x0000. if onesec is present, then the initial value is 0x0001. - 349 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers table 292: tx combus interface - defect group summary (ro) address bit hw symbol init description 0x184f0 0 interrupt 0x0000 latch for interrupt summary for the global defects. 0x184f2 0 pm 0x0000 pm summary for the global defects 0x184f4 0 fm 0x0000 fm summary for the global defects table 293: tx combus interface - per channel defects (ro) address bit hw symbol index init description 0x184f8 0x184fa 0x184fc 0 j1_lossofframe 0 1 2 0x0000 j1 loss of frame for the j1 locking fsm 1 v1_lossofframe v1 loss of frame for the v1 locking fsm 2 fifoerror fifoerror table 294: tx combus interface - per channel defects latched for interrupt (r/cow-1) address bit hw symbol index init description 0x18400 0x18402 0x18404 0 j1_lossofframe 0 1 2 0x0000 j1 loss of frame for the j1 locking fsm 1 v1_lossofframe v1 loss of frame for the v1 locking fsm 2 fifoerror fifoerror table 295: tx combus interface - per channel defect masks (rw) address bit hw symbol index init description 0x18410 0x18412 0x18414 0 j1_lossofframe 0 1 2 0x0000 j1 loss of frame for the j1 locking fsm 1 v1_lossofframe v1 loss of frame for the v1 locking fsm 2 fifoerror fifoerror table 296: tx combus interface - per channel defects latched for pmfm (r/cow-0) address bit hw symbol index init description 0x18420 0x18422 0x18424 0 j1_lossofframe 0 1 2 0x0000 j1 loss of frame for the j1 locking fsm 1 v1_lossofframe v1 loss of frame for the v1 locking fsm 2 fifoerror fifoerror table 297: tx combus interface - per channel defects pm (ro) address bit hw symbol index init description 0x18430 0x18432 0x18434 0 j1_lossofframe 0 1 2 0x0000 j1 loss of frame for the j1 locking fsm 1 v1_lossofframe v1 loss of frame for the v1 locking fsm 2 fifoerror fifoerror table 298: tx combus interface - per channel defects fm (ro) address bit hw symbol index init description 0x18440 0x18442 0x18444 0 j1_lossofframe 0 1 2 0x0000 j1 loss of frame for the j1 locking fsm 1 v1_lossofframe v1 loss of frame for the v1 locking fsm 2 fifoerror fifoerror - 350 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tables 303 through 305 - configuration and status of the general combus interface interrupt controller table 299: tx combus interface - per channel defect summary (ro) address bit hw symbol init description 0x18450 2-0 latchforint 0x0000 per channel latch for interrupt summary 0x18452 2-0 pm 0x0000 per channel pm summary 0x18454 2-0 fm 0x0000 per channel fm summary table 300: tx combus interface - per channel defect summary masks (rw) address bit hw symbol init description 0x184c0 2-0 mask 0x0007 mask setting for every per channel latched bit for interrupt of the per channel summary. default: true (1) table 301: tx combus interface - per channel defect group summary (ro) address bit hw symbol init description 0x18460 0 interrupt 0x0000 latch for interrupt summary for the per channel defects 0x18462 0 pm 0x0000 pm summary for the per channel defects 0x18464 0 fm 0x0000 fm summary for the per channel defects table 302: tx combus interface - defect configuration (rw) address bit hw symbol index init description 0x18470 0x18472 0x18474 0 j1lof_c1lof_inhibit_disable 0 1 2 0x0000 disables the inhibition of j1_lossofframe by c1_lossofframe. default value: false 1 v1lof_c1lof_inhibit_disable disables the inhibition of v1_lossofframe by c1_lossofframe. default value: false 2 v1lof_j1lof_inhibit_disable disables the inhibition of v1_lossofframe by j1_lossofframe. default value: false table 303: combus interrupt controller - interrupts (ro) address bit hw symbol init description 0x1d784 0 rxcb_global_corrdefect_interrupt not applicable interrupt of the global defects coming from the rx combus. default value: true 1 rxcb_perchannel_corrdefect_interrupt interrupt of the per channel defects coming from the rx com- bus. default value: true 2 txcb_global_corrdefect_interrupt interrupt of the global defects coming from the tx combus. default value: true 3 txcb_perchannel_corrdefect_interrupt interrupt of the per channel defects coming from the tx combus. default value: true - 351 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tables 306 through 308 - configuration and status of the general vtmapper interrupt controller table 304: combus interrupt controller - interrupt masks (rw) address bit hw symbol init description 0x1d786 0 rxcb_global_corrdefect_interrupt 0x000f interrupt of the global defects coming from the rx combus. default value: true 1 rxcb_perchannel_corrdefect_interrupt interrupt of the per channel defects coming from the rx combus. default value: true 2 txcb_global_corrdefect_interrupt interrupt of the global defects coming from the tx combus. default value: true 3 txcb_perchannel_corrdefect_interrupt interrupt of the per channel defects coming from the tx combus. default value: true table 305: combus interrupt controller - interrupt group summary (ro) address bit hw symbol init description 0x1d780 0 interrupt 0x0000 interrupt summary for the whole combus block table 306: mapper interrupt controller - interrupts (ro) address bit hw symbol init description 0x1d7a4 0 combus_interrupt not applicable interrupt coming from the combus core. 1 c3_to_aug1_interrupt interrupt coming from the c3_to_aug1 core. 2 vtmp_interrupt interrupt coming from the vtmapper core. table 307: mapper interrupt controller - interrupt masks (rw) address bit hw symbol init description 0x1d7a6 0 combus_interrupt 0x0007 mask for the interrupt coming from the combus core. default value: true 1 c3_to_aug1_interrupt mask for the interrupt coming from the c3_to_aug1 core. default value: true 2 vtmp_interrupt mask for the interrupt coming from the vtmapper core. default value: true table 308: mapper interrupt controller - interrupt group summary (ro) address bit hw symbol init description 0x1d7a0 0 interrupt 0x0000 interrupt summary for the whole vtmapper_top core table 309: reserved registers address bit hw symbol init description 0x00006 15-0 reserved 0x0000 0x00012 15-0 reserved 0x0000 0x00014 15-0 reserved 0x20d7 0x00016 15-0 reserved 0x0108 0x00018 15-0 reserved 0x0000 0x0001a 15-0 reserved 0x0000 0x0001e 15-0 reserved 0x0000 0x00026 15-0 reserved 0x0000 - 352 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 0x0002a 15-0 reserved 0x0000 0x0002e 15-0 reserved 0x0000 0x00032 15-0 reserved 0x0000 0x00036 15-0 reserved 0x0000 0x00038 15-0 reserved 0x0000 must be set to 0x0000 0x0003a 15-0 reserved 0x0100 must be set to 0x0100 0x0003e 15-0 reserved 0x0000 0x00044 15-0 reserved 0x0000 0x11988 15-0 reserved 0x0000 0x11d88 15-0 reserved 0x0000 0x12188 15-0 reserved 0x0000 0x12588 15-0 reserved 0x0000 0x12988 15-0 reserved 0x0000 0x12d88 15-0 reserved 0x0000 0x13188 15-0 reserved 0x0000 0x19670 15-0 reserved 0x0000 0x19684 15-0 reserved 0x003c 0x19846 15-0 reserved 0x003c 0x198f0 15-0 reserved 0x0000 0x1d050 15-0 reserved 0x0000 must be set to 0x0006 0x1d240 15-0 reserved 0x0088 0x1d242 15-0 reserved 0x0064 0x1d244 15-0 reserved 0x017a 0x1d246 15-0 reserved 0x0011 0x1d248 15-0 reserved 0x000c 0x1d280 15-0 reserved 0x0000 0x1d282 15-0 reserved 0x0000 0x1d284 15-0 reserved 0x0000 0x1d286 15-0 reserved 0x0000 0x1d690 15-0 reserved 0x0000 0x1d692 15-0 reserved 0x0000 0x1eac8 15-0 reserved 0x0000 0x1ebce 15-0 reserved 0x0000 0x1f0c0 15-0 reserved 0x0000 0x1f0c2 15-0 reserved 0x0000 0x1f0c4 15-0 reserved 0x0000 0x1f0c6 15-0 reserved 0x0000 0x1f0c8 15-0 reserved 0x0000 0x1f0ca 15-0 reserved 0x0000 0x1f0cc 15-0 reserved 0x0000 0x1f0ce 15-0 reserved 0x0000 0x1f0d0 15-0 reserved 0x0000 0x1f940 15-0 reserved 0x0000 table 309: reserved registers address bit hw symbol init description - 353 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers alarms, performance and fault monitoring this section details out the alarm/status and performance monitoring features for the ethermap-3 plus device. the general features are described herein, with specific listing of all alarms, performance counters appearing in the relevant sections. terminology system alarm (raw, unlatched alarm) a signal that traces in real time, the evolution of a system property (a system fault, statistic, or any other characteristic that needs monitoring) when appropriately enabled. this signal, then can be monitored for purposes of corrective action or for the purposes of status reporting. note that the terms system alarm, raw alarm or unlatched alarm may be used interchangeably. alarm event a transition in the state of a system alarm. note that there can be two types of transitions in a system alarm - a rising edge, or a falling edge corresponding to ? alarm entry ? or ? alarm exit ? respectively. latched alarm a latched alarm for a given unlatched alarm, is the associated latched memory for the occurrence of an alarm event (of a single type, or either type) in the unlatched alarm signal. this permits processing of the system alarm without real-time constraints. the active transition or level, which leads to setting of the latched alarm, in general may be software configurable. secondary alarm inhibition the process of filtering to provide data reduction and unnecessary generation of interrupts, when an alarm event that is at a higher hierarchy leads to the generation of multiple lower order alarms (in other words, lower order alarm events are triggered as a secondary effect). this filtering mechanism (termed herein as ? secondary alarm inhibition) prevents redundant data processing and also the unnecessary interrupt burden that may affect adversely the functioning of the system. the alarm inhibition function may be built at the unlatched alarm level, or, if gr-253 style reporting requirements need to be supported, then the alarm inhibition may be built at the latched alarm level. - 354 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers interrupt mask if interrupt generation is a function of a given latched alarm, there will be a corresponding dedicated interrupt mask bit, that may be set up to disable the particular interrupt. these bits will be software readable and writable. performance and fault monitoring (pm and fm) an unlatched alarm may have associated with it a corresponding pm/fm feature, that allows a system to monitor the long term evolution of the particular alarm, in a convenient manner. as an example, a system may wish to monitor if a defect occurred over only a single unit time interval, or, if the defect persisted over several unit time intervals with respect to a certain particular alarm, or a group of alarms. the unit time interval may be 1-second, or any other, as laid down by applicable standards (if any), or as required to implement a specified performance and fault monitoring system. performance monitoring (pm) the 1-second pm output bit associated with an unlatched alarm indicates the occurrence of an alarm event over the immediately preceding 1-second interval. fault monitoring (fm) the 1-second fm output bit associated with an unlatched alarm indicates that the unlatched alarm was continuously asserted, without any alarm events taking place, over the duration of at least the immediately preceding 1-second interval. 1-second clock the 1-second clock defines 1-second time intervals to serve as a time reference for the pm/fm scheme (see onesec page 43 ). this clock typically, may be provided from external sources to transwitch devices, and is also used to synchronize the external polling mechanism that would query the pm/fm registers on the transwitch device. performance counters certain alarm events or parameters are counted for system performance monitoring. the counter width (in bits) depends on the event being counted, and time-intervals (that is, estimated maximum counts) between reads. the performance counters may adopt one of two schemes: a. counters that either roll-over or saturate. here ? roll-over ? means that after the terminal count is reached, the counter wraps around, and continues to count from zero; ? saturate ? means that after terminal count is reached, the counter stops incrementing, and freezes at the terminal count. b. counters that clear on 1-second boundaries, with existing counts over the 1-second interval transferred to 1- second counter shadow registers (also on the 1-second boundaries). the main event counters are cleared by the microprocessor writing 0 ? s to the counter, or at 1-second boundaries. - 355 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers unlatched alarms all unlatched alarms are memory mapped and available to be read out from read-only type registers for the actual status. the unlatched alarm signal is high only when asserted. unlatched alarms can be both frame based, like sonet/sdh performance alarms, or, independent of framing, such as loss of signal alarms, or buffer overflow/underflow alarms etc. inhibition of secondary unlatched alarm generation the generation of secondary unlatched alarm may be inhibited dynamically, depending on system alarm hierarchy to prevent unnecessary automatic reporting of secondary alarms which arise as a consequence of some primary root cause alarm (the particular inhibiting conditions for a given device). this process is known as ? defect correlation ? in [g806]. defect correlation will also inhibit the generation of unnecessary interrupts at a lower layer. refer figures 6.1 and 6.2 in [g806], that illustrate the process of alarm supervision and defect correlation at each atomic function. each atomic function generates ais as appropriate, based on locally detected defects only. upstream ais or upstream tsf/ssf signals are inputs to the atomic function. the defect correlation process in [g806] terminology is described as c(defect) <--- d(defect) and (not(inhibition_condition) and (inhibition_enabled)) there are two components for the inhibition function: 1) active high alarm inhibition condition based on upstream or primary or root cause alarms; (active_hi_alarm_inhibition_cond). this includes possibly an upstream tsf/ssf. 2) static, software configurable bit inhib_alarm_name_en, that enables such a correlation. note that provision for the inhib_alarm_name_en control bit is optional. on power up, or on a hw reset, this control bit is set up with a zero. the presence of this control gives the system the flexibility to implement defect correlation. the correlated defect (unlatched alarm generated after being operated on by the inhibition function) gives rise to two possible sets of latched alarm event bits, discussed below. latched alarms every unlatched alarm bit (alarm_name) has a corresponding latched alarm bit for interrupt generation (called lalarm_name, if there is no associated pm/fm). if there is performance and fault monitoring associated with an unlatched alarm, then there are two separate latched alarm bits: (1) one for generating hardware/software interrupts (called l1alarm_name); and (2) another to be used for pm/fm circuits (called l2alarm_name) for pm and fm functionality. it should be noted that it is not necessary for pm/fm to be associated with every unlatched alarm, while a latched alarm must exist for every unlatched alarm. the purpose of the latched alarm(s) is two-fold: 1. to generate a hardware or software interrupt to flag the occurrence of an alarm event to the external host processor. 2. to derive the performance and fault monitoring (pm/fm) conditions. the l1alarm_name bits are latched read-only (r(l)), cleared on a microprocessor read (or on a system reset). the l2alarm_name bits, for pm/fm, are read/write, cleared either by the microprocessor writing a zero to this bit, or on 1-second clock boundaries (or on system reset). the general scheme for latched alarm processing is shown below. - 356 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers latched alarm bits for interrupt generation (lalarm_name/l1alarm_name) the ethermap-3 plus is capable of latching according to the states given in the following table. inrt(1-0) (actual symbol names are cinrt_grp125m ( table 48, on page 236 ), cinrt_grp100m ( table 98, on page 298 ), cinrt_grptx20m ( table 65, on page 270 ), cinrt_grprx20m ( table 76, on page 283 ) and cinrt_sotern_core ( table 30, on page 217 )) are global configuration bits for the group of latched alarm bits for interrupt generation (labelled as lalarm_name in systems without pm/fm, for example llos; and labelled as l1alarm_name in systems with pm/fm, for example l1los). the case for level triggering is included for completeness; most transwitch devices are doing away with that option. at minimum, all transwitch devices are configurable for the positive edge only and positive/negative edge events. the negative edge only and the level triggering events are additional optional features of particular devices. for devices that do not incorporate these options, the inrt(1-0) = (0,0) or (1,0) settings are invalid. table 310: latched alarm bit (l1alarm_name) transition selection software access to this set of latched alarm bits is as follows: normal operation: latched read only, and clears on a microprocessor read, or on global resets. all l /l1alarm_name values are readable by software, before application of masking. the following diagram of figure 59 illustrates the above described options. inrt1 inrt0 action 0 0 all latched alarm bits (event bits) latch on the positive level (i.e., true state) of the unlatched alarm. when a latched alarm bit position is cleared, it re- latches if the unlatched alarm is still active (true). (this mode is no longer favored in transwitch devices; the only purpose of its inclusion is when pm/fm is not provided, this may be one option of monitoring a persistent fault). 0 1 all latched alarm bits (event bits) latch on the positive transition of an unlatched alarm. when a latched alarm bit position is cleared, it remains reset unless the alarm goes inactive and then active again. this is expected to be the most frequently used mode for the latched alarm bits. 1 0 all latched alarm bits (event bits) latch on the negative transition of an unlatched alarm. when a latched alarm bit position is cleared, it remains reset unless the alarm goes active and then inactive again. the purpose of these bits is added flexibility, in configuring all events for alarm exit conditions. 1 1 all latched alarm bits (event bits) latch on either the positive or negative transition of an unlatched alarm. when a latched alarm bit position is cleared, it remains reset unless the alarm transitions again. - 357 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 59. latched alarm bit (l1alarm_name) transitions latched alarm masking bits (malarm_name) each latched alarm l/l1alarm_name has its own static masking bit that is software configurable, and is named malarm_name. the latched alarm combined with the state of the mask bit may generate an interrupt. these individual interrupts are grouped at various levels of hierarchy (with masking provided at each level) and finally be consolidated at a top level software polling register. depending on individual device requirements, there could also be a single global interrupt mask bit. the hardware interrupt capability is enabled by writing a 1 into the hinten control bit. when disabled, the hardware interrupt indication int/irq lead is tri-stated (for a device/chip-level output) or, at the ip core level, the o_int/irq signal is in the inactive state, even when a latched indication (event) bit is set. a software polling bit and the hardware interrupt state (when enabled by writing a 1 to hinten) indication occurs when one or positive level inrt1, inrt0=00 clear on read alarm bit (unlatched) event bit (latched) alarm bit (unlatched) alarm bit (unlatched) event bit (latched) event bit (latched) positive transition inrt1, inrt0=01 negative transition inrt1, inrt0=10 set on pos. transition clear on read set on neg. transition clear on read alarm bit (unlatched) event bit (latched) positive/negative transition inrt1, inrt0=11 set on transition clear on read - 358 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers more bit locations in the interrupt mask bit locations are written with a ? 0 ? , and the corresponding latched alarm occurs. note that the polarity of the int/irq output signal for the intel/motorola processor interface is selectable by selecting the appropriate microprocessor interface (not in the scope of the present specification). please note that setting of a mask bit to 0 enables the actions by an alarm. the hardware interrupt state is exited when any one (or more) of the following occurs: hinten control bit is written with a 0 alarm mask bit is written with a 1 latched alarm bit position is cleared the software polling indication is zero when any one (or more) of the following occurs: alarm mask bit is written with a 1 latched alarm bit position is cleared please note that a latched alarm will re-latch if the alarm is active for a positive level transition. secondary latched alarm inhibition the process of ? defect correlation ? in [g806] (refer section 3.2.1 for references to defect correlation), maybe done at the latched alarm level. this process is optional to the process described in section 3.2.1. note the difference: the process in section 3.2.1 suppresses generation of the unlatched alarms, whereas, this process allows the unlatched alarm to be generated. the latched alarm is inhibited dynamically, depending on system alarm hierarchy to prevent unnecessary automatic latching of secondary alarms which arise as a consequence of some primary root cause alarm. the above inhibits the generation of unnecessary interrupts, while at the same time, allow the monitoring of the secondary alarms for optional report generation, as certain standards require, since the unlatched alarms are readable, and their generation is not suppressed (as an example of such a standard, the bellcore/telcordia gr-253, sept. 2000: section 6.2.1.8.4, r6-293 and r6-294, may be cited). there are three components for the function: 1) active high alarm inhibition condition based on upstream or primary or root cause alarms; (active_hi_alarm_inhibition_cond). 2) static, software configurable bit inhib_alarm_name_en, that enables such an inhibit (note that provision for the inhib_alarm_name_en control bit is optional). on power up, or on a hw reset, this control bit is set up with a zero. 3) delayed release of unlatched alarm signal for interrupt generation when the inhibition condition for the secondary latched alarm is removed ( ? off-delay ? timer). this blocks the generated secondary alarm for sufficiently long duration so that its delayed exit after the exit of the primary alarm is kept from actuating the secondary latched event. for example, for a vt demapper, the vt ais alarm exit could take 3 sonet/sdh multiframes, or 1.5 milliseconds to integrate. if an upstream ais alarm is used to inhibit the vt ais alarm, the inhibit function could stay in effect for 1.5 ms after the upstream ais alarm exits. the unlatched alarm when not blocked by the inhibition function, gives rise to two possible sets of latched alarm event bits, discussed above and below. - 359 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers latched alarm bits for pm/fm (l2alarm_name), performance monitoring (pm bits; palarm_name) and fault monitoring (fm bits; falarm_name) the latched alarm bits for pm/fm are capable of latching according to the states given in the following table. lpf(1-0) are global configuration bits for the group of latched event bits for pm/fm. these bits are named l2alarm_name, corresponding to the unlatched alarm, alarm_name. also, the corresponding pm and fm bits are named palarm_name and falarm_name (as an example, the pm/fm bits for the oof alarm is called poof and foof respectively). software access to this set of latched event bits: normal mode: latched read only; writable for 0's only. these latched event bits for pm/fm are cleared by writing them with a zero by the microprocessor, or, on 1-second clock rising edges, or on global resets. writing 1 ? s have no effect. masking does not apply to these bits. however, inhibition does apply. pm/fm registers have a hierarchy that is identical to the basic system alarm hierarchy, that governs the interrupt hierarchy. note that 1-second interval boundaries are used to determine the state of a given alarm or event over the immediately preceding 1-second interval; whether an alarm persisted for multiple seconds; to obtain 1-second performance counts; and to operate the 1-second performance and fault monitoring registers, and performance counter shadow registers. the 1-second clock may be an external input, that is distributed globally throughout the device, or, obtained inside the device as a derivative of some other external reference input. the 1-second clock input is synchronized with respect to the time base that the host microprocessor uses to initiate the 1-second reads. it is extremely important that this be so since otherwise, pm/fm data and performance counts may be lost. the table below shows the action of these control bits, in selection of the active transition in the main unlatched alarm for setting the latched event bits: table 311: latched alarm bit (l2alarm_name) transition selection the pm/fm latched event bit and the main unlatched alarm together set up the pm/fm indication bits as shown in the following timing diagrams, for all the three active options of the lpf(1-0). the pm/fm 1-second shadow registers are enabled with the control bit srgen set to 1. this control bit also enables the 1-second pm counter shadow registers if applicable. note that the pm/fm registers can be cleared either by the microprocessor writing zeros to these locations of the memory map, or on the rising edges of the 1-second clock. lpf1 lpf0 action 00 latched status bits for pm/fm disabled. 01 latched status indication sets on positive alarm transition. 10 latched status indication sets on negative alarm transition. 11 latched status indication sets on both positive and negative alarm transitions. - 360 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers positive edge events the following diagram shows the case for the rising edge transition in the example unlatched alarm, loss of signal (los). assuming that control bits lpf(1-0) = 01, the transition from 0 to 1 of the los alarm will cause the l2los bit to latch. (the alarm status can be determined by reading periodically the unlatched alarm status bit, until it becomes 0, indicating that recovery has taken place). assume that the pm/fm shadow registers are enabled. then on rising edges of the input 1-second clock, the pm indication bit plos is set to indicate (a) the unlatched alarm entered in the preceding 1-second interval, or (b) the current unlatched alarm was active for at least the entire preceding 1-second interval. in addition, the fm indication bit flos is set if the alarm is active, but the transition to the active state did not occur in the last 1-second interval (i.e., the alarm has persisted for longer than 1-second). the rising edge of the 1-second pulse is also reset the latched event bit position l2los independent of the microprocessor. note that plos is set on rising edge of the 1-second clock, when, los+l2los = 1, evaluated just prior to the time l2los is reset to 0. this ensures that even if the duration of the fault event is much smaller than the 1- second interval, the plos signal captures it. note also that flos is set on rising edge of the 1-second clock, when, los&l2los = 1, evaluated just prior to the time l2los is reset to 0. this ensures that flos is set on a 1-second edge, only if the unlatched alarm was active, without the transition having occurred in the immediately previous interval. hence, the combination plos&flos = 1 is interpreted as an alarm entry in the immediately previous interval; and flos = 1 shows a persistent fault. figure 60. positive edge event - pm/fm signal generation one sec. pulse los l2los plos flos t=0 sec t=1 sec t=2 sec t=3 sec t=4 sec t=5 sec t=6 sec (input) note 1: for this example, latched events are set only on positive event transitions. note 2: plos = los + l2los evaluated at 1-second boundaries (where ? + ? is a logical or). note 3: flos = los & l2los evaluated at 1-second boundaries (where ? & ? is a logical and, and x is a logical inversion). - 361 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers negative edge events the following diagram shows the case for the falling edge transition in the example unlatched alarm, loss of signal (los). assuming that control bits lpf(1-0) = 10, the transition from 1 to 0 of the los alarm causes the l2los bit to latch. the l2los alarm event now signifies an alarm exit. as in the previous case for the rising edge transition, the alarm status can be determined by periodically reading the unlatched alarm status bit, until it becomes 0, indicating that recovery has taken place. assume that the pm/fm shadow registers are enabled. then, on rising edges of the input 1-second clock, the pm indication bit plos is set to indicate either: (a) the unlatched alarm exited in the preceding 1-second interval, or (b) the current unlatched alarm was active for at least the entire preceding 1-second interval. for the negative transition case, the fm indication bit flos is set if the alarm is active, and the alarm did not clear in the last 1-second interval. the rising edge of the 1-second pulse is also reset the latched event bit position l2los independent of the microprocessor. note that plos is set on rising edge of the 1-second clock, when, los+l2los = 1, evaluated just prior to the time l2los is reset to 0. this ensures that even if the duration of the fault event is much smaller than the 1- second interval, the plos signal captures it. note also that flos is set on rising edge of the 1-second clock, when, los&l2los = 1, evaluated just prior to the time l2los is reset to 0. this ensures that flos is set on a 1-second edge, only if the unlatched alarm was active, without the negative edge transition having occurred in the immediately previous interval. hence, for the neg edge event, the combination plos&flos = 1 is interpreted as the alarm los cleared in the immediately previous interval; and flos = 1 shows a persistent fault, or the unlatched alarm occurred in the previous interval. figure 61. negative edge event - pm/fm signal generation one sec. pulse los l2los plos flos t=0 sec t=1 sec t=2 sec t=3 sec t=4 sec t=5 sec t=6 sec (input) note 1: for this example, latched events are set only on negative event transitions. note 2: plos = los + l2los evaluated at 1-second boundaries (where ? + ? is a logical or). note 3: flos = los & l2los evaluated at 1-second boundaries (where ? & ? is a logical and, and x is a logical inversion). - 362 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers positive or negative edge events the following diagram shows the case for the rising or falling edge transition in the example unlatched alarm, loss of signal (los). assuming that control bits lpf(1-0) = 11, the transition from 1 to 0, or, from 0 to 1, of the los alarm causes the l2los bit to latch. the l2los event now signifies either an alarm entry or exit. the alarm status can, as in the previous cases, be determined by reading periodically the unlatched alarm status bit, until it becomes 0, indicating that recovery has taken place. assume that the pm/fm shadow registers are enabled. then, as before (for the rising edge only or falling edge only cases), on rising edges of the input 1-second clock, the pm indication bit plos is set to indicate either: (a) there was an alarm event, either entry or exit, in the unlatched alarm in the previous 1-second interval; or (b) the unlatched alarm has been asserted over the past 1-second interval. for the positive or negative transition case, the fm indication bit flos is set if the alarm is active, and the alarm did not enter or clear in the last 1- second interval (i.e., the alarm has persisted for longer than 1-second). the rising edge of the 1-second pulse is also reset the latched event bit position l2los independent of the microprocessor. note that plos is set on rising edge of the 1-second clock, when, los+l2los = 1, evaluated just prior to the time l2los is reset to 0. this ensures that even if the duration of the fault event is much smaller than the 1- second interval, the plos signal captures it. note also that flos is set on rising edge of the 1-second clock, when, los&l2los = 1, evaluated just prior to the time l2los is reset to 0. this ensures that flos is set on a 1-second edge, only if the unlatched alarm was active, without the transition having occurred in the immediately previous interval. hence, for the pos or neg edge event, the combination plos&flos = 1 is interpreted as the alarm los entered or cleared in the immediately previous interval; and flos = 1 shows a persistent fault, with the unlatched alarm transition, pos- itive or negative, not having occurred in the previous interval. figure 62. positive/negative edge event - pm/fm signal generation one sec. pulse los l2los plos flos t=0 sec t=1 sec t=2 sec t=3 sec t=4 sec t=5 sec t=6 sec (input) note 1: for this example, latched events are set on positive or negative event transitions. note 2: plos = los + l2los evaluated at 1-second boundaries (where ? + ? is a logical or). note 3: flos = los & l2los evaluated at 1-second boundaries (where ? & ? is a logical and, and x is a logical inversion). - 363 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers overall alarm generation and pm/fm process diagram the following is a signal flow diagram that illustrates the process of generating the l1alarm_name and l2alarm_name bits from the common starting input of the unlatched alarm (alarm_name). the diagram is based on the alarm inhibition process. included is a basic view of the logic diagram used for setting the software polling bits and the hardware interrupt (where & is an ? and ? function, and + is an ? or ? function), using the l1alarm_name, and the corresponding mask bit. note the diagram shows a simplified situation, without any hierarchies. the ? off delay ? is the time for which the inverter output is held low after the alarm inhibition condition is removed (when inhib_alarm_name_en = 1). a clock together with a counter could be used to realize this delay; the clock is such that counter sizes are minimized, while providing the appropriate level of granularity, so that the smallest required delay can be realized efficiently. the pm/fm bit generation starting from the l2alarm_name bit is included. note that both the l1alarm_name and the l2alarm_name bits are subject to the same inhibiting condition. figure 63. alarm, interrupt and pm/fm generation process if the alarm inhibition function is adopted, then the signal simplifies as follows: figure 64. alarm, interrupt and pm/fm generation process (inhibition function) + & & latched alarm hinten=1(hardware interrupt enabled) software polling bit hardware interrupt (raw) unlatched alarm (alarm_name) inhib_alarm_name_en = 0 active_hi_alarm_inhibition_cond & inv & other_latched_unmasked_alarms (l1alarm_name) latched alarm (l2alarm_name) pm/fm gen. block delay off- edge cfg 1: edge cfg 2: inrt (1-0) lpf (1-0) (palarm_name) (falarm_name) pm fm mask bit (malarm_name) = 0 + latched alarm hinten=1(hardware interrupt enabled) software polling bit hardware interrupt (correlated) unlatched alarm (alarm_name) & & other_latched_unmasked_alarms (l1alarm_name) latched alarm (l2alarm_name) pm/fm gen. block edge cfg 1: edge cfg 2: inrt (1-0) lpf (1-0) (palarm_name) (falarm_name) pm fm mask bit (malarm_name) = 0 (see [g806] fig 6.1 and 6.2) defect correlator active_hi_alarm_inhibition_cond (includes inhib_alarm_name_en tsf/ssf) - 364 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers performance counters performance counters in the ethermap-3 plus device use two different schemes, as dictated by their respective functions: scheme a - counters with roll-over/saturation option these performance counters are configurable to be either saturating or non-saturating. when the performance counters are configured to be saturating, the counters stop at their maximum count. in the saturating mode, counts that occur during a micro read cycle, are held off and the counter updates later. a saturating counter is reset to zero on a microprocessor read cycle. when the performance counters are configured to be non-saturating they roll over to 0 on the next count after the maximum count is reached (i.e., all ones). in this mode, the counters do not clear on a microprocessor read cycle, but continue to count. when a ? reset counters ? operation is performed, these performance counters are set to an all-zeros value. this type of counter is used in the following two areas: the encapsulation and decapsulation blocks, with performance counters described in tables 43 and 60 . control bit crov (0x194a6, ta b l e 1 0 ) selects between saturate and roll-over. the ethernet mac blocks, with performance counters described in tables 13 , 14 and 15 . control bit autoz (0x1d340, ta b l e 3 0 ) selects between saturate and roll-over. all performance counters may be reset simultaneously by writing a 91h to top level register resetc. all counters in the device that can be read by the microprocessor, are of the 'read/write' type, and for test pur- poses, the microprocessor is able to write any value to them. a status alarm bit count with an associated interrupt mask bit mcount is provided. the count status bit is set when any of the performance counters has reached its maximum value in the saturating mode of operation only. when a microprocessor reads the saturated counter, the counter is cleared, but the latched alarm (lcount) is not cleared unless read and cleared separately. scheme b - performance counters with 1-second shadow register option the differences from scheme a, are: 1. there are designated bits (1 bit for each counter) available, that take up counter overflow, for each counter. 2. in the event that a terminal count is reached, the overflow bit is used as an indicator. there is no equivalent of the crov configuration bit as in the case of scheme a. 3. the counters can only be cleared by the rising edge of a 1-second interval boundary, or, if the microprocessor writes 0 ? s to the counters. the counters are reset to all 0 ? s. 4. at the 1-second boundary, the contents of the performance counter are transferred, along with the overflow indication bit, to a 1-second shadow register for the particular counter, after which the counter is cleared. thus, the 1-second shadow register for the performance counter updates only on 1-second boundaries. 5. the 1-second shadow registers are enabled with the common shadow register enable control bit, srgen. 6. there is no equivalent of the count alarm, for saturated counter operation, as with scheme a. clearing/resetting of performance counters in scheme b, is accomplished in a manner similar to that of scheme a. the shadow register holds its count during a microprocessor read cycle. however, the main performance counters may be updated internally on a coincident 1-second boundary, for a count update. this type of counter is used in the tx mapper and rx demapper block. - 365 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers alarm feature combinations each defined system alarm or event, have associated with it one of the following groups of features: group 1: a main unlatched alarm signal (alarm_name). a latched alarm indication an unlatched alarm, for the purpose of status and interrupt generation (l1alarm_name). latched alarm interrupt mask bit (malarm_name). group 2: features group 1. a latched alarm indication for an unlatched alarm, for the purpose of 1-second performance and fault monitoring (l2alarm_name). 1-second pm bit (palarm_name). 1-second fm bit (falarm_name). group 3: features group 1. performance counter. group 4: features group 2. performance counter. group 5: performance counter only; note that there may be performance counters that are not associated with any alarm (for example, sonet/sdh pointer justification counters). group 6: a latched alarm indication for the main unlatched system alarm or event, for the purpose of 1-second performance and fault monitoring (alarm 2). 1-second pm bit. 1-second fm bit. performance counter. it is the responsibility of the individual device ? s specification to completely specify for each alarm, the following: 1. group of features applicable. 2. main unlatched alarm entry condition, with standard reference if applicable. 3. main unlatched alarm exit condition, with standard reference if applicable. - 366 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 4. alarm action. 5. hierarchical position of the alarm, that is what secondary alarms and performance counter(s) are inhibited on its occurrence. 6. the decision to implement a scheme a or scheme b performance counters (on a per counter basis, if applicable). 7. inhibition definition, inhibition extension times, and enable control bits as applicable. system alarm, interrupt, and pm/fm hierarchy the system alarm and interrupt hierarchy are device specific, and aimed towards providing a convenient software interrupt nesting, so that poll times are considerably reduced. the pm/fm registers follow a similar hierarchy, only difference being that the pm/fm bits are not subject to masking (they are subject to inhibition however). in general, the alarm and interrupt hierarchy follow one or more of the following grouping schemes: protocol layers, example for sonet/sdh devices, section layer, line/ho path layer, lo path layer. channel numbers (example, alarms/masks grouped based on vt numbers for hdm, or channel numbers for framers, etc.). alarm functionality (e.g., global alarm for a vt lop condition). receive/transmit or other special hierarchical groupings). each latched alarm bit has a mask bit. in addition, depending on the grouping chosen, each hierarchical level has a consolidated latched alarm and associated mask; may also have pm/fm bits, depending on alarm feature group specified. the software polling interrupt register provides a way to have the processor poll a register in memory (provided the proper interrupt mask disable bits are set) to indicate the alarms that causes the interrupt or the alarms that are set without having to read all the alarm registers until the active alarm is found. there is also a hierarchical alarm inhibition scheme that may be implemented, based on needs and standards. the diagram of figure 65 below illustrates how an alarm and interrupt hierarchy is to be achieved: - 367 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 65. alarm interrupt hierarchy hinten=1(hardware interrupt enabled) hardware interrupt & + & latched alarm mask bit = 0 software polling bit unlatched alarm & alarm inhibit + & latched alarm mask bit = 0 unlatched alarm & alarm inhibit (group #1) for group # 1 & & + + mask bit = 0 group # 1 software polling bit for group # 2 mask bit = 0 group # 2 software polling bit for group # 3 mask bit = 0 group # 3 overall ip core mask bit = 0 overall ip core software polling bit note : (1) depending on actual needs, there may be several polling bits from a given ip block. this figure shows the concept of hierarchy in a simplified manner. + & latched alarm mask bit = 0 unlatched alarm & alarm inhibit + & latched alarm mask bit = 0 unlatched alarm & alarm inhibit (group #2) + & latched alarm mask bit = 0 unlatched alarm & alarm inhibit + & latched alarm mask bit = 0 unlatched alarm & alarm inhibit (group #3) (up readable) (up readable) (up readable) (2) based on device specification, there can be a single global mask bit that can disable the hw interrupt for the entire device. & & + - 368 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers alarm interrupt tree figure 66. alarm interrupt tree part a a + & mavtmd_interrupt vtmd_20m_global_interrupt vtmd_interrupt (from mapper/demapper) & maesa_global_interrupt esa_125m_global_interrupt + & & matetherr0 matetherr7 l1atetherr0 l1atetherr7 mac#1 mac#8 + & mamac_global_interrupt mac_125m_global_interrupt + & & macarry0 macarry7 l1acarry0 l1acarry7 mac#1 mac#8 (from mac) + & madftc_100m_interrupt dftc_100m_global_interrupt + & & madftc_holptrramerr_interrupt madftc_holfifo_interrupt + & & maholptrramerr7 & lcount_dftc_100m + & & maholfifo0 blk#1 blk#8 l1aholptrramerr7 maholptrramerr0 l1aholptrramerr0 mcount_dftc_100m l1aholfifo0 l1aholfifo7 - 369 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 67. alarm interrupt tree part a to part b b + & maencap_20m_interrupt encap_20m_global_interrupt + & & maglobaltxctl maglobaltxlaps + & & blk#1 blk#8 tctl + & & maenc0_laps_interrupt all txl1atlpxxx type alarms with mattlpxxx bits for laps block #1 blk#1 blk#8 laps a same as for laps all txl1atlfxxx type alarms with matlfxxx bits for lapf block #1 to block #8 & maglobaltxlapf + & & maenc7_lapf_interrupt blk#1 blk#8 lapf & maglobaltxgfp + & & maenc7_gfp_interrupt all txl1agfpxxx type alarms with matgfpxxx bits for gfp block #1 blk#1 blk#8 gfp matctlx0 l1atctlx0 l1atctlx7 & maglobaltxppp + & & maenc0_ppp_interrupt all txl1atpppxxx type alarms with matpppxxx bits for ppp block #1 blk#1 blk#8 ppp & mcount_decap_100m_interrupt + & & blk#1 blk#8 mcount_enc0 lcount_enc0 lcount_enc7 + + + - 370 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 68. alarm interrupt tree part b to part c c b + & madecap_100m_interrupt decap_100m_global_interrupt & & maglobalrxgfp maglobalrxlaps + & & maegen0_gfp_interrupt all rxl1argfpxxx type alarms with margfpxxx bits for gfp block #1 blk#1 blk#8 gfp & maglobalrxlapf same as for laps all rxl1arlfxxx type alarms with marlfxxx bits for lapf block #1 to block #8 lapf + & & maege0_laps_interrupt all rxl1arlpsxxx type alarms with marlpsxxx bits for laps block #1 blk#1 blk#8 laps + & maglobalrxgfpcid + & & maegen0_gfpcid_interrupt all rxl1argfpfecsfcid0x type alarms with margfpfecsfcid0x bits for gfp block #1 blk#1 blk#8 gfp cid & maglobalrxppp + & & magen0_ppp_interrupt all rxl1arpppxxx type alarms with marpppxxx bits for ppp block #1 blk#1 blk#8 ppp & mcount_decap_100m + & & blk#1 blk#8 mcount_decap0 lcount_decap0 & maglobalrxctl + & & blk#1 blk#8 tctl maegen0_ctlrx_interrupt & & marctlrx0 l1arctlrx0 marctlberr0 l1arctlberr0 + + + + - 371 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 69. alarm interrupt tree part c to parts d1, d2 and d3 d1 c + & marxtxholo_interrupt rxtxconc_20m_global_interrupt & & marxtxlo_interrupt mavcr_rxfifo_interrupt + & & l1arxfifo_0 + marxfifo_0 l1arxfifo_7 marxfifo_7 rxfifo_7 rxfifo_0 lo + & marxtxlcaslo_interrupt + & & mavcr_locrce_interrupt rem mavcr_rxlcaslo_interrupt + fa il added } these are structured same as lo crce & crce malrlolcscrceklm l1alcscrceklm crceklm d2 & & mavct_locprd1_interrupt dnu mavct_txlcaslo_interrupt + rem added } these are structured same as lo prd1 & prd1 matlcprd1klm l1atlcprd1klm prd1klm dnuok d3 prd3 - 372 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 70. alarm interrupt tree parts d1, d2 and d3 to parts e1 and e2 e1 d1 e2 d2 + & mavcr_lovcg_interrupt + & mavcr_loloa_interrupt d3 + & maloloa_0 loloa0 loloa7 l1aloloa_0 & mavct_txloprd2vcg_interrupt + & matloprd2_1 l1atlcprd2_1 + & mavct_txloprd3vcg_interrupt + & matloprd3_1 l1atlcprd3_1 & mavcr_losqm_interrupt + & malosqm_klm l1alosqm_klm losqmklm & mavcr_lolcasgid_interrupt + & marlolcasgidm_0 l1arlolcasgidm_0 + - 373 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 71. alarm interrupt tree parts e1 and e2 to parts f1 and f2 f1 e1 & marxtxho_interrupt + ho + & marxtxlcasho_interrupt + & & mavcr_hocrce_interrupt rem mavcr_rxlcasho_interrupt + fa il added } these are structured same as ho crce & crce malrholcscrce_1 l1arholcscrce_1 crce_1 & & mavct_hocprd1_interrupt dnu mavct_txlcasho_interrupt + rem added } these are structured same as ho prd1 & prd1 matlcprd1_1 l1atlcprd1_1 prd1_1 dnuok e2 + & device interrupt hinten + crce_2 crce_3 prd1_2 prd1_3 + f2 prd3 - 374 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 72. alarm interrupt tree parts f1 and f2 to part g g f1 + & mavcr_hovcg_interrupt + & mavcr_holoa_interrupt f2 + & maholoa_0 holoa0 holoa7 l1aholoa_0 & mavct_txhoprd2vcg_interrupt + & mathoprd2_1 l1athoprd2_1 + & mavct_txhoprd3vcg_interrupt + & mathoprd3_1 l1athoprd3_1 & mavcr_hosqm_interrupt + & mahosqm_k l1ahosqm_k hosqm_k & mavcr_holcasgid_interrupt + & marholcasgidm_0 l1arholcasgidm_0 + - 375 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 73. alarm interrupt tree part g g + & mashtc_100m_interrupt shtc_100m_global_interrupt & mashtc_ptrramerr_interrupt + & & maptrramerr0 + l1aptrramerr0 l1aptrramerr7 maptrramerr7 ptrramerr & mashtc_txfifo_interrupt + & & matxfifo0 l1atxfifo0 l1atxfifo7 matxfifo7 txfifo + & mashrc_rxfifovc4_interrupt l1arxfifovc4 rxfifovc4 + & mackrst_lossdclk_interrupt l1alossdclk lossdclk & lcount_shtc_100m mcount_shtc_100m - 376 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers register tree figure 74. register tree parts a1, a2 and a3 a1 register: perfcntr_status_level1 mac1_perf cnt_status_ lvl2 mac2_perf cnt_status_ lvl2 mac3_perf cnt_status_ lvl2 mac4_perf cnt_status_ lvl2 mac5_perf cnt_status_ lvl2 mac6_perf cnt_status_ lvl2 mac7_perf cnt_status_ lvl2 mac8_perf cnt_status_ lvl2 or laps cntrs lapf cntrs ppp cntrs gfp cntrs cmm cntrs rx fifo discard cntr rx pause frame cntr or register: mac0_laps_status_lvl3 rx laps flag error cntr flag srlpsflager0 rx sapi field mismatch cntr flag srlpssapier0 rx laps invalid frame cntr flag srlpsbad0 rx laps abort frame cntr flag srlpsabtd0 rx total no. of laps control frame payloads cntr flag srlpshost0 register: mac0_perfcntr_status_level2 or register: mac0_lapf_status_lvl3 rx lapf flag error cntr flag srlffla ger0 rx lapf address field mismatch cntr flag srlfadd er0 rx lapf invalid frame cntr flag srlfba d0 rx lapf abort frame cntr flag srlfabt d0 rx lapf control field mismatch cntr flag srlfcnt er0 rx lapf dlci field mismatch cntr flag srlfdlci er0 rx lapf bit destuffing violations cntr flag srlfdst ufer0 rx lapf nlpid field mismatch cntr flag srlfnlpi der0 rx lapf pid field mismatch cntr flag srlfpid er0 rx lapf oui field mismatch cntr flag srlfoui er0 rx lapf lmi frame cntr flag srlflmi 0 a2 a3 - 377 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 75. register tree parts a1, a2 and a3 (continued) a1 or register: mac0_ppp_status_lvl3 rx ppp flag error cntr flag srpppflage r0 rx ppp address field mismatch cntr flag srpppprote r0 rx ppp invalid frame cntr flag srpppbad0 rx ppp abort frame cntr flag srpppabtd0 rx ppp bcp mac type field mismatch cntr flag srpppmactyper0 rx ppp lcp frame cntr flag srppplcp0 rx ppp ncp- lcp frame cntr flag srpppncp0 or register: mac0_gfp_status_lvl3 rx gfp chec single bit error cntr flag srgfpc hecer0 rx gfp cid mismatch cntr flag srgfpci der0 rx gfp ehec single bit error cntr flag srgfpe hecer0 rx gfp multibit error cntr flag srgfpe hecme r0 rx gfp exi mismatch cntr flag srgfpex ier0 rx gfp idle frame error cntr flag srgfpid ler0 rx gfp valid client managem ent frame cntr flag srgfpm gt0 rx gfp pti mismatch cntr flag srgfppt ier0 rx gfp thec single bit error cntr flag srgfpth ecer0 rx gfp thec multibit error cntr flag srgfpth ecmer0 rx gfp upi mismatch cntr flag srgfpup ier0 a2 a3 or register: mac0_cmmperf_status_lvl3 rx pyld max length violation cntr flag (laps/lapf/ ppp/gfp) srmaxer0 rx pyld min length violation cntr flag (laps/lapf/ ppp) srminer0 rx fcs error cntr flag (laps/lapf/ ppp/gfp) srfcser0 rx address field mismatch cntr flag (laps/ppp) srlspppadder0 rx control field mismatch cntr flag (laps/ppp) srlspppcnter0 rx byte destuff violation cntr flag (laps/ppp) srlspppdstufer0 - 378 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers mapper/demapper performance monitoring pointer adjustment counters per level 3 high order path: - incoming positive pointer adjustment count, - incoming negative pointer adjustment count. pointer adjustment counters per low order path: - incoming positive pointer adjustment count, - incoming negative pointer adjustment count. poh counters per high order path: - b3 near-end errored bip count, - b3 near-end errored block count, - g1 far-end error count, configurable to count either rei errors or errored blocks, - near-end defect second, - far-end defect second. poh counters per low order path: - v5 near-end errored bip count, - v5 near-end errored block count, - v5 far-end errored block count, - near-end defect second, - far-end defect second. all performance counters are one second shadow registers and at the one second boundary, the contents of each performance counter is latched into its one second shadow register, after which the performance counter is cleared. these one second shadow registers will hold their value during the entire period between two subsequent one second boundaries. the one second shadow registers are available for software read-only access. all performance counters are saturating: counting will stop when the maximum count value is reached. all errored bip and block counters are dimensioned to cover the maximum count value during a one second interval meaning they can never reach saturation. - 379 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers mapper/demapper interrupt tree - [lo] ranges from 0 to 83 (84 low order channels) - [ho] ranges from 0 to 2 (3 high order channels) - [aip] ranges from 0 to 1 (internal and external alarm indication port) figure 76. mapper/demapper interrupt tree part a vtmp_top_ic (mapper/demapper top level) a + vtmp_top_ic (mapper/demapper top level) + + + txap defects (transmit low order alarm indication port) + latchforint[aip].loc & defectinterruptmask[aip].loc txap events (transmit low order alarm indication port) + latchforint[aip].crc & defectinterruptmask[aip].crc lodmp_pohmonitor defects (low order poh monitor) + summary[lo].latchforint & summary[lo].mask + latch[lo].ssf & mask[lo].ssf + latch[lo].deg & mask[lo].deg + latch[lo].ais & mask[lo].ais + latch[lo].plm & mask[lo].plm + latch[lo].uneq & mask[lo].uneq + latch[lo].rfi & mask[lo].rfi + latch[lo].rdi & mask[lo].rdi + latch[lo].erdi_s & mask[lo].erdi_s + latch[lo].erdi_c & mask[lo].erdi_c + latch[lo].erdi_p & mask[lo].erdi_p + latch[lo].lom & mask[lo].lom + latch[lo].tim & mask[lo].tim + latch[lo].tti_zero & mask[lo].tti_zero + lodmp_ptr defects (low order pointer tracker) + latch[lo].ais_detected & mask[lo].ais_detected + latch[lo].lossofpointer & mask[lo].lossofpointer - 380 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers . figure 77. mapper/demapper interrupt tree part a to parts b1 and b2 b1 + c3_to_aug1_ic (high order mapper/demapper) + + + txap defects (transmit high order alarm indication port) + latchforint[aip].loc & defectinterruptmask[aip].loc txap events (transmit high order alarm indication port) + latchforint[aip].crc & defectinterruptmask[aip].crc rx_vc4_poh_monitor defects (high order vc-4 poh monitor) + summary.latchforint + latchforint.ssf & mask.ssf + latchforint.tim & mask.tim + latchforint.ttizero & mask.ttizero + latchforint.crc & mask.crc + latchforint.deg & mask.deg + latchforint.plm & mask.plm + latchforint.uneq & mask.uneq + latchforint.incais & mask.incais + latchforint.rdi & mask.rdi + latchforint.rdi_s & mask.rdi_s + latchforint.rdi_c & mask.rdi_c + latchforint.rdi_p & mask.rdi_p + latchforint.lom & mask.lom a b2 - 381 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 78. mapper/demapper interrupt tree parts b1 and b2 to part c c + rx_vc3_poh_monitor defects (high order vc-3 poh monitor) + summary[ho].latchforint + latchforint[ho].ssf & mask[ho].ssf + latchforint[ho].tim & mask[ho].tim + latchforint[ho].ttizero & mask[ho].ttizero + latchforint[ho].crc & mask[ho].crc + latchforint[ho].deg & mask[ho].deg + latchforint[ho].plm & mask[ho].plm + latchforint[ho].uneq & mask[ho].uneq + latchforint[ho].incais & mask[ho].incais + latchforint[ho].rdi & mask[ho].rdi + latchforint[ho].rdi_s & mask[ho].rdi_s + latchforint[ho].rdi_c & mask[ho].rdi_c + latchforint[ho].rdi_p & mask[ho].rdi_p + latchforint[ho].lom & mask[ho].lom b1 b2 + + + rx_vc4_poh_monitor events (high order vc-4 poh monitor) + latch.k3_aps & mask.k3_aps rx_vc3_poh_monitor events (high order vc-3 poh monitor) + latch[ho].k3_aps & mask[ho].k3_aps rx_tu3_ptr defects (tu-3 pointer tracker) + summary[ho].latchforint + latch[ho].ais_detected & mask[ho].ais_detected + latch[ho].lossofpointer & mask[ho].lossofpointer + tx_tu3_ptr defects (tu-3 pointer generator) + summary[ho].latchforint + latch[ho].fifoerror & mask[ho].fifoerror l3_retimer defects (level 3 retimer) + latch[ho].fifoerror & mask[ho].fifoerror + au_retimer defects (high order retimer) + latch[ho].fifoerror & mask[ho].fifoerror + - 382 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers figure 79. mapper/demapper interrupt tree part c - [lo] ranges from 0 to 83 (84 low order channels) - [ho] ranges from 0 to 2 (3 high order channels) - [aip] ranges from 0 to 1 (internal and external alarm indication port) + combus_ic (telecom bus) + rx_combus global defects (drop telecom bus) + global_latch.c1_lossofframe & global_mask.c1_lossofframe c + global_latch.parityerror & global_mask.parityerror + rx_combus per au-3/sts-1 channel defects (drop telecom bus) + summary[ho].latchforint perchannel_latch[ho].ais_detected & perchannel_mask[ho].ais_detected + perchannel_latch[ho].v1_lossofframe & perchannel_mask[ho].v1_lossofframe + perchannel_latch[ho].j1_lossofframe & perchannel_mask[ho].j1_lossofframe + + tx_combus global defects (add telecom bus) + latchforint.c1_lossofframe & mask.c1_lossofframe + tx_combus per au-3/sts-1 channel defects (add telecom bus) + summary.latchforint[ho] & summary_mask.mask[ho] latchforint[ho].j1_lossofframe & mask[ho].j1_lossofframe + latchforint[ho].v1_lossofframe & mask[ho].v1_lossofframe + latchforint[ho].fifoerror & mask[ho].fifoerror + - 383 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers mapper/demapper pm/fm tree per block rx_vc3_poh_monitor (high order vc-3/sts-1 poh monitor): - [ho] ranges from 0 to 2 (3 high order channels) figure 80. mapper/demapper rx_vc3_poh_monitor pm/fm trees + summary[ho].pm & summary_mask[ho].pm + pm[ho].ssf + pm[ho].tim + pm[ho].ttizero + pm[ho].crc + pm[ho].deg + pm[ho].plm + pm[ho].uneq + pm[ho].incais + pm[ho].rdi + pm[ho].rdi_s + pm[ho].rdi_c + pm[ho].rdi_p + pm[ho].lom groupsummary.pm + summary[ho].fm & summary_mask[ho].fm + fm[ho].ssf + fm[ho].tim + fm[ho].ttizero + fm[ho].crc + fm[ho].deg + fm[ho].plm + fm[ho].uneq + fm[ho].incais + fm[ho].rdi + fm[ho].rdi_s + fm[ho].rdi_c + fm[ho].rdi_p + fm[ho].lom groupsummary.fm - 384 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers rx_vc4_poh_monitor (high order vc-4/sts-3c poh monitor): figure 81. mapper/demapper rx vc-4 poh monitor pm/fm trees + summary.pm & summary_mask.pm + pm.ssf + pm.tim + pm.ttizero + pm.crc + pm.deg + pm.plm + pm.uneq + pm.incais + pm.rdi + pm.rdi_s + pm.rdi_c + pm.rdi_p + pm.lom groupsummary.pm + summary.fm & summary_mask.fm + fm.ssf + fm.tim + fm.ttizero + fm.crc + fm.deg + fm.plm + fm.uneq + fm.incais + fm.rdi + fm.rdi_s + fm.rdi_c + fm.rdi_p + fm.lom groupsummary.fm - 385 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers tx_combus (transmit add telecom bus): - [ho] ranges from 0 to 2 (3 high order channels) figure 82. mapper/demapper tx combus pm/fm trees groupsummary.fm + tx_combus global defects (add telecom bus) + fm.c1_lossofframe + summary.fm[ho] fm[ho].j1_lossofframe + fm[ho].v1_lossofframe + fm[ho].fifoerror + + tx_combus per au-3/sts-1 channel defects (add telecom bus) groupsummary.pm + tx_combus global defects (add telecom bus) + pm.c1_lossofframe + summary.pm[ho] pm[ho].j1_lossofframe + pm[ho].v1_lossofframe + pm[ho].fifoerror + + tx_combus per au-3/sts-1 channel defects (add telecom bus) - 386 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers rx_tu3_ptr (tu-3 pointer tracker): - [ho] ranges from 0 to 2 (3 high order channels) figure 83. mapper/demapper rx_tu3_ptr pm/fm trees tx_tu3_ptr (tu-3 pointer generator): - [ho] ranges from 0 to 2 (3 high order channels) figure 84. mapper/demapper tx_tu3_ptr pm/fm trees groupsummary.pm + summary[ho].pm & summarymask[ho].pm + pm[ho].ais_detected groupsummary.fm + summary[ho].pm & summarymask[ho].fm + fm[ho].ais_detected + pm[ho].lossofpointer + fm[ho].lossofpointer groupsummary.pm + summary[ho].pm & summarymask[ho].pm + pm[ho].fifoerror groupsummary.fm + summary[ho].pm & summarymask[ho].fm + fm[ho].fifoerror - 387 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers rx_combus (receive drop telecom bus): - [ho] ranges from 0 to 2 (3 high order channels) figure 85. mapper/demapper rx combus pm/fm trees groupsummary.fm + rx_combus global defects (drop telecom bus) + fm.c1_lossofframe + summary.fm[ho] fm[ho].j1_lossofframe + fm[ho].v1_lossofframe + fm[ho].ais_detected + + rx_combus per au-3/sts-1 channel defects (drop telecom bus) groupsummary.pm + rx_combus global defects (drop telecom bus) + pm.c1_lossofframe + summary.pm[ho] pm[ho].j1_lossofframe + pm[ho].v1_lossofframe + pm[ho].ais_detected + + rx_combus per au-3/sts-1 channel defects (drop telecom bus) - 388 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers lodmp_pohmonitor (low order poh monitor): - [lo] ranges from 0 to 83 (84 low order channels) figure 86. mapper/demapper lodmp_pohmonitor pm/fm trees groupsummary.pm + summary[lo].pm + pm[lo].ssf + pm[lo].deg + pm[lo].ais + pm[lo].plm + pm[lo].uneq + pm[lo].rfi + pm[lo].rdi + pm[lo].erdi_s + pm[lo].erdi_c + pm[lo].erdi_p + pm[lo].lom + pm[lo].tim groupsummary.fm + summary[lo].fm + fm[lo].ssf + fm[lo].deg + fm[lo].ais + fm[lo].plm + fm[lo].uneq + fm[lo].rfi + fm[lo].rdi + fm[lo].erdi_s + fm[lo].erdi_c + fm[lo].erdi_p + fm[lo].lom + fm[lo].tim - 389 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers lodmp_ptr (low order pointer tracker): - [lo] ranges from 0 to 83 (84 low order channels) figure 87. mapper/demapper lodmp_ptr pm/fm trees summary.pm + pm[lo].ais_detected summary.fm + fm[lo].ais_detected + pm[lo].lossofpointer + fm[lo].lossofpointer - 390 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers mapper/demapper consequent actions per block rx_vc4_poh_monitor (high order vc-4/sts-3c poh monitor): the high order vc-4/sts-3c poh monitor will insert ais per high order path according to the following expression: the high order vc-4/sts-3c poh monitor will insert rdi per high order path towards the rx high order path alarm indication port according to the following expressions: the high order vc-4/sts-3c poh monitor will forward the dplm and dlom indications to the subsequent adaptation blocks (low order pointer processors or virtual concatenation receiver blocks) depending on the configured sdh/sonet mapping: aais = dais and not ais_incais_disable or dssf and not ais_ssf_disable or duneq and not ais_uneq_disable or dtim and not ais_tim_disable or insertais ardi-s = dssf and not rdi_ssf_disable or insertais ardi-c = duneq and not rdi_uneq_disable or dtim and not rdi_tim_disable ardi = ardi-s or ardi-c ardi-p = dplm and not rdi_plm_disable aplm = dplm and not plm_plm_disable alom = dlom and not lom_lom_disable - 391 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers rx_vc3_poh_monitor (high order vc-3/sts-1 poh monitor): - [ho] ranges from 0 to 2 (3 high order channels) the high order vc-3/sts-1 poh monitor will insert ais per high order path according to the following expres- sion: the high order vc-3/sts-1 poh monitor will insert rdi per high order path towards the rx high order path alarm indication port according to the following expressions: the high order vc-3/sts-1 poh monitor will forward the dplm and dlom indications to the subsequent adaptation blocks (low order pointer processors or virtual concatenation receiver blocks) depending on the configured sdh/sonet mapping: aais [ho] =dais [ho] and not ais_incais_disable [ho] or dssf [ho] and not ais_ssf_disable [ho] or duneq [ho] and not ais_uneq_disable [ho] or dtim [ho] and not ais_tim_disable [ho] or insertais [ho] ardi-s [ho] =dssf [ho] and not rdi_ssf_disable or insertais [ho] ardi-c [ho] =duneq [ho] and not rdi_uneq_disable or dtim [ho] and not rdi_tim_disable ardi [ho] = ardi-s [ho] or ardi-c [ho] ardi-p [ho] =dplm [ho] and not rdi_plm_disable aplm [ho] =dplm [ho] and not plm_plm_disable alom [ho] = dlom [ho] and not lom_lom_disable - 392 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers rx_tu3_ptr (tu-3 pointer tracker): - [tu3] ranges from 0 to 2 (3 high order channels) the tu-3 pointer tracker will insert ais per tu-3 towards the high order vc-3 poh monitors according to the following expression: lodmp_ptr (low order pointer tracker): - [lo] ranges from 0 to 83 (84 low order channels) the low order pointer tracker will insert ais per low order path towards the low order poh monitors according to the following expression: aais [tu3] =dais [tu3] and not insertais_on_ais_disable or dlop [tu3] and not insertais_on_lop_disable or dplm and not insertais_on_plm_disable (from high order vc-4 poh monitor) aais [lo] =dais [lo] or dlop [lo] or dplm (from high order poh monitor) or dlom (from high order poh monitor) - 393 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers lodmp_pohmonitor (low order poh monitor): - [lo] ranges from 0 to 83 (84 low order channels) the low order poh monitor will insert ais per low order path according to the following expression: the low order poh monitor will insert rdi per low order path towards the rx low order path alarm indication port according to the following expressions: the low order poh monitor will forward the dplm and dlom indications to the subsequent adaptation blocks (virtual concatenation receiver blocks) depending on the configured sdh/sonet mapping: aais [lo] =dais [lo] and not ais_incais_disable or dssf [lo] and not ais_ssf_disable or duneq [lo] and not ais_uneq_disable or dtim [lo] and not ais_tim_disable or insertais [lo] ardi-s [lo] =dssf [lo] and not rdi_ssf_disable or insertais [lo] ardi-c [lo] =duneq [lo] and not rdi_uneq_disable or dtim [lo] and not rdi_tim_disable ardi [lo] = ardi-s [lo] or ardi-c [lo] ardi-p [lo] =dplm [lo] and not rdi_plm_disable aplm [lo] =dplm [lo] and not plm_plm_disable alom [lo] = dlom [lo] and not lom_lom_disable - 394 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers package information the ethermap-3 plus device is packaged in a 400-lead plastic ball grid array (pbga) suitable for surface mounting, as illustrated in figure 88 . figure 88. ethermap-3 plus txc-04236 package diagram 1 y b e e2 e d2 d note 2 d1/4 e1/4 -d1- -e1- a2 (a3) a a1 dimension (note 1) min max a (nom.) 2.33 notes: 1. all dimensions are in millimeters. values shown are for refer- ence only. 2. identification of the solder ball a1 corner is contained within this shaded zone. this package corner may be a 90 angle, or chamfered for a1 identification. a1 a2 0.50 1.12 0.70 1.22 a3 (nom.) 0.56 b (ref.) 0.76 d 27.00 d1 (nom.) 24.13 d2 24.95 25.70 e 27.00 e1 (nom.) 24.13 e2 24.95 25.70 e (ref.) 1.27 bottom view transwitch txc-04236aibg a 2 3 4 5 6 7 8 10 9 11 13 12 15 14 wvut rpnmlkjhgfedcb 17 16 18 20 19 - 395 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ordering information part number: txc-04236aibg 400-lead plastic ball grid array package related products txc-03453, tl3m device (triple level 3 mapper). maps three 44.736 mbit/s ds3 to an stm- 1, tug-3 or sts-3 sts-1 spe sdh/sonet signal. an 34.368 mbit/s e3 signal is mapped in to an stm-1 tug-3. the tl3m ? s sdh/sonet interface format is combus, byte wide parallel. the tl3m supports drop bus and add bus sdh/sonet timing modes. drop bus timing provides timing signals for the add side while timing for both busses is independent for the add bus timing mode. txc-04222, temx28 device (28 channel dual bus high density mapper). an add/drop multiplexer, terminal multiplexer, and dual and single unidirectional ring applications. up to 28 e1, ds1, or vt/tu payloads are mapped to and from vt1.5/tu-11s and vt2/tu-12s carried in an stm-1 vc-4 or sts-3 format. txc-06103, phast-3n device (sdh/sonet stm-1, sts-3 or sts-3c overhead terminator) this phast-3n device provides a telecom bus interface for downstream devices and operates from a power supply of 3.3 volts. txc-06212, phast-12e device (programmable, high-performance atm/packet/transmission sonet/sdh terminator for level 12). a highly integrated sonet/sdh terminator device designed for atm cell, frame, higher-order multiplexing, and transmission applications. this phast-12 device provides a telecom bus interface for downstream devices and operates from a power supply of 3.3 volts. txc-06312, phast-12n device (stm-4/oc-12 sdh/sonet overhead terminator with telecom bus interface). the phast-12n is a highly integrated sdh/sonet overhead terminator device designed for tdm payload mappings. a single phast-12n can terminate four individual stm-1/oc-3 lines or a single stm-4/oc-12 line. txc-06603, pop-12 device (oc-12 sonet/sdh path overhead processor, retimer, and cross connect). the pop-12 integrates vc-3/vc-4 poh processing, au-3/au-4 pointer processing retiming, and vc-3/vc-4 cross connect for four telecom bus interfaces into one package. it provides an interface to high density mapper applications when used with the transwitch phast-12e (txc-06212), and mapper and framer devices. the pop-12 device is designed to provide a seamless interface to the phast-12e device. txc-06712, etherphast-48 device (oc-48 sonet/sdh ethernet mapper). the etherphast-48 device is a highly integrated, sts-48/stm-16 rate sonet/sdh device, for mapping of ieee 802.3 100/1000 mbps ethernet and block encoded fibre channel, ficon, escon and dvb-asi into sonet/sdh transport. - 396 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers standards documentation sources telecommunication technical standards and reference documentation may be obtained from the following organizations: ansi (u.s.a.): american national standards institute tel: (212) 642-4900 25 west 43 rd street fax: (212) 398-0023 new york, new york 10036 web: www.ansi.org the atm forum (u.s.a., europe, asia): 404 balboa street tel: (415) 561-6275 san francisco, ca 94118 fax: (415) 561-6120 web: www.atmforum.com atm forum europe office kingsland house - 5 th floor tel: 20 7837 7882 361-373 city road fax: 20 7417 7500 london ec1 1pq, england atm forum asia-pacific office hamamatsucho suzuki building 3f tel: 3 3438 3694 1-2-11, hamamatsucho, minato-ku fax: 3 3438 3698 tokyo 105-0013, japan bellcore (see telcordia) ccitt (see itu-t) eia (u.s.a.): electronic industries association tel: (800) 854-7179 (within u.s.a.) global engineering documents tel: (303) 397-7956 (outside u.s.a.) 15 inverness way east fax: (303) 397-2740 englewood, co 80112 web: www.global.ihs.com etsi (europe): european telecommunications standards institute tel: 4 92 94 42 00 fax: 4 93 65 47 16 650 route des lucioles web: www.etsi.org 06921 sophia-antipolis cedex, france go-mvip (u.s.a.): the global organization for multi-vendor integration protocol (go-mvip) tel: (800) 669-6857 (within u.s.a.) tel: (903) 769-3717 (outside u.s.a.) 3220 n street nw, suite 360 fax: (903) 769-3818 washington, dc 20007 web: www.mvip.org - 397 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers ieee (corporate office): american institute of electrical engineers tel: (212) 419-7900 (within u.s.a.) 3 park avenue, 17th floor tel: (800) 678-4333 (members only) new york, new york 10016-5997 u.s.a. fax: (212) 752-4929 web: www.ieee.org itu-t (international): publication services of international telecommunication union tel: 22 730 5852 fax: 22 730 5853 telecommunication standardization sector web: www.itu.int place des nations, ch 1211 geneve 20, switzerland jedec (international): joint electron device engineering council tel: (703) 907-7559 2500 wilson boulevard fax: (703) 907-7583 arlington, va 22201-3834 web: www.jedec.org mil-std (u.s.a.): dodssp standardization documents ordering desk tel: (215) 697-2179 fax: (215) 697-1462 building 4 / section d web: www.dodssp.daps.mil 700 robbins avenue philadelphia, pa 19111-5094 pci sig (u.s.a.): pci special interest group tel: (800) 433-5177 (within u.s.a.) 5440 sw westgate dr., #217 tel: (503) 291-2569 (outside u.s.a.) portland, or 97221 fax: (503) 297-1090 web: www.pcisig.com telcordia (u.s.a.): telcordia technologies, inc. tel: (800) 521-2673 (within u.s.a.) attention - customer service tel: (732) 699-2000 (outside u.s.a.) 8 corporate place rm 3a184 fax: (732) 336-2559 piscataway, nj 08854-4157 web: www.telcordia.com ttc (japan): ttc standard publishing group of the telecommunication technology committee tel: 3 3432 1551 fax: 3 3432 1553 hamamatsu-cho suzuki building web: www.ttc.or.jp 1-2-11, hamamatsu-cho, minato-ku tokyo 105-0013, japan - 398 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers list of data sheet changes this change list identifies those areas within this updated ethermap-3 plus txc-04236 data sheet that have significant differences relative to the previous and now superseded ethermap-3 plus txc-04236 data sheet. updated ethermap-3 plus txc-04236 data sheet: preliminary edition 3, july 2004 previous ethermap-3 plus txc-04236 data sheet: preliminary edition 2, march 2004 the page numbers indicated below of this updated data sheet include significant changes relative to the previous data sheet. page number of updated data sheet summary of the change all changed edition number and date. 2 - 14 updated table of contents, list of figures and list of tables. 19 changed data processing/flow section. 22 changed 10/100/1000 mbit/s ethernet media access controller (mac) block section. 23 added sonet/sdh mapping section. changed mapper block section. 25 changed demapper block section. 47 changed conditions column for parameter moisture exposure level in the absolute maximum ratings and environmental limitations (referenced to vss) table. changed note 3 below the table. 48 changed note 1 below the table. 55, 57 changed max value for symbol t d(3) . 58 changed the diagram of figure 10 . 59 changed the diagram of figure 11 . 86 modified for symbol t d(4) in figure 35 . 116 changed sixth and sixteenth bullets. 119 changed sixth and sixteenth bullets. changed configuration for virtual concatenation and lcas section. 124 changed sentence ? the value 0x0300 represents... ? . changed heading to vcg tributary assignments (adding and removing members) and made changes to this section. added title dynamic mapping and virtual concatenation changes . 131 changed heading to ethernet support and added sub-heading smii and gmii interfaces . 133 changed last two bulleted sections of ethernet mac blocks section. 134 added ethernet frame size section. 136 changed flow control operation section. 139 added heading setting the encapsulation mode . added heading changing the encapsulation mode and changed the content of this section. 186 changed microprocessor controlled hardware reset section. 200 changed descriptions for symbols reseth, tx_resetsx, rx_resetsx and ccrov in ta b l e 1 0 . changed description for symbol versionmask in table 12 . 206 changed bit 3 of register 0x0003c to reserved in ta b l e 1 6 . - 399 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers 210 changed descriptions for symbols synchronized enable and synchronized received enable in ta b l e 1 8 . 215 changed description for symbol read cycle in ta b l e 2 5 . 216 changed description for symbol mii mgmt control in table 27 . 217 changed descriptions for symbols rhwpt_x, rlwpt_x and rhispse_x in ta b l e 3 0 . 247 added note at the top of ta b l e 5 6 . 249 changed description for symbol argfpfecsfx in ta b l e 5 6 . 270 changed descriptions for symbols cthovc3_3, cthovc3_2 and cthovc3_1 in ta b l e 6 5 . 283 changed descriptions for symbols crhovc3_3, crhovc3_2 and crhovc3_1 in ta b l e 7 6 . 285 changed description for symbol alosqm_x in table 77 . 286 changed descriptions for symbols aloloa_x and aloloa_aiivt_x in ta b l e 7 7 . 293 changed descriptions for symbols srlopool_x, srlovcg_x, srloctrl_x, srlosq_x, srhosq_x, srhopool_x, srhovcg_x and srhoctrl_x in ta b l e 8 3 . 295 changed description for symbol ctfcmodex in table 86 . 299 changed description for symbol ctrstram in table 98 . changed description for symbol atxfifox in ta b l e 9 9 . 300 changed description for symbol l1aptrramerrx in table 101 . 303 changed ta b l e 1 1 2 heading. changed description for symbol aumode in table 112 . 310 added note at bottom of table 137 . 323 added note at bottom of table 186 . 364 modified fifth paragraph under scheme a - counters with roll-over/saturation option. 370 changed the diagram of figure 68 . 398 added list of data sheet changes section. page number of updated data sheet summary of the change - 400 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers - notes - transwitch reserves the right to make changes to the product(s) or circuit(s) described herein without notice. no liability is assumed as a result of their use or application. transwitch assumes no liability for transwitch applications assistance, customer product design, soft- ware performance, or infringement of patents or services described herein. nor does transwitch warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of transwitch cov- ering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. preliminary information documents contain information on products in the sampling, pre-pro- duction or early production phases of the product life cycle. characteristic data and other specifica- tions are subject to change. contact transwitch applications engineering for current information on this product. - 401 of 402 - preliminary txc-04236-mb, ed. 3 july 2004 ethermap-3 plus txc-04236 data sheet proprietary transwitch corporation information for use solely by its customers - notes - transwitch corporation 3 enterprise drive shelton, ct 06484 usa www.transwitch.com tel: 203-929-8810 fax: 203-926-9453 |
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